a Complete 12-Bit 1.25 MSPS Monolithic A/D Converter AD1671 FEATURES FUNCTIONAL BLOCK DIAGRAM Conversion Time: 800 ns SHA 1.25 MHz Throughput Rate OUT UPO/BPO ENCODE VCC ACOM VEE VLOGIC DCOM Complete: On-Chip Sample-and-Hold Amplifier and 5k Voltage Reference AIN1 S/H Low Power Dissipation: 570 mW RANGE AIN2 No Missing Codes Guaranteed 5k SELECT X4 Signal-to-Noise Plus Distortion Ratio 3-BIT 3-BIT COARSE 8-BIT f = 100 kHz: 70 dB FLASH DAC FLASH DAC 4-BIT LADDER IN FLASH MATRIX Pin Configurable Input Voltage Ranges Twos Complement or Offset Binary Output Data 3 3 4 FINE 4-BIT 28-Pin DIP and 28-Pin Surface Mount Package REF IN CORRECTION LOGIC FLASH Out of Range Indicator REF OUT 2.5V 8 4 REF LATCHES AD1671 12 REF COM OTR MSB BIT 1 –12 DAV PRODUCT DESCRIPTION The performance of the AD1671 is made possible by using high The AD1671 is a monolithic 12-bit, 1.25 MSPS analog-to- speed, low noise bipolar circuitry in the linear sections and low digital converter with an on-board, high performance sample- power CMOS for the logic sections. Analog Devices’ ABCMOS-1 and-hold amplifier (SHA) and voltage reference. The AD1671 process provides both high speed bipolar and 2-micron CMOS guarantees no missing codes over the full operating tempera- devices on a single chip. Laser trimmed thin-film resistors are ture range. The combination of a merged high speed bipolar/ used to provide accuracy and temperature stability. CMOS process and a novel architecture results in a combi- The AD1671 is available in two performance grades and three nation of speed and power consumption far superior to pre- temperature ranges. The AD1671J and K grades are available viously available hybrid implementations. Additionally, the over the 0(cid:176) C to +70(cid:176) C temperature range. The AD1671A grade greater reliability of monolithic construction offers improved is available over the –40(cid:176) C to +85(cid:176) C temperature range. The system reliability and lower costs than hybrid designs. AD1671S grade is available over the –55(cid:176) C to +125(cid:176) C tempera- The fast settling input SHA is equally suited for both multi- ture range. plexed systems that switch negative to positive full-scale voltage levels in successive channels and sampling inputs at PRODUCT HIGHLIGHTS frequencies up to and beyond the Nyquist rate. The AD1671 The AD1671 offers a complete single chip sampling 12-bit, provides both reference output and reference input pins, al- 1.25 MSPS analog-to-digital conversion function in a 28-pin lowing the on-board reference to serve as a system reference. package. An external reference can also be chosen to suit the dc accu- The AD1671 at 570 mW consumes a fraction of the power of racy and temperature drift requirements of the application. currently available hybrids. The AD1671 uses a subranging flash conversion technique, An OUT OF RANGE output bit indicates when the input sig- with digital error correction for possible errors introduced in nal is beyond the AD1671’s input range. the first part of the conversion cycle. An on-chip timing gen- erator provides strobe pulses for each of the four internal Input signal ranges are 0 V to +5 V unipolar or – 5 V bipolar, flash cycles. A single ENCODE pulse is used to control the selected by pin strapping, with an input resistance of 10 kW . converter. The digital output data is presented in twos The input signal range can also be pin strapped for 0 V to +2.5 V complement or offset binary output format. An out-of-range unipolar or – 2.5 V bipolar with an input resistance of 10 MW . signal indicates an overflow condition. It can be used with Output data is available in unipolar, bipolar offset or bipolar the most significant bit to determine low or high overflow. twos complement binary format. REV.B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. otherwise under any patent or patent rights of Analog Devices. Tel: 617/329-4700 Fax: 617/326-8703

AD1671–SPECIFICATIONS DC SPECIFICATIONS (T to T with V = +5 V (cid:54) 5%, V = +5 V (cid:54) 10%, V = –5 V (cid:54) 5%, unless otherwise noted) MIN MAX CC LOGIC EE AD1671J/A/S AD1671K Parameter Min Typ Max Min Typ Max Units RESOLUTION 12 12 Bits CONVERSION TIME 800 800 ns ACCURACY Integral Nonlinearity (INL) – 1.5 – 2.5 – 0.7 – 2.5 LSB (S Grade) – 3.0 Differential Nonlinearity (DNL) 11 12 Bits No Missing Codes 11 Bits Guaranteed 12 Bits Guaranteed Unipolar Offsets1 (+25(cid:176)C) – 9 – 9 LSB Bipolar Zero1 (+25(cid:176) C) – 10 – 10 LSB Gain Error1, 2 (+25(cid:176) C) 0.1 0.35 0.1 0.35 % FSR TEMPERATURE COEFFICIENTS3 Unipolar Offset – 25 – 25 ppm/(cid:176) C (S Grade) – 25 Bipolar Zero – 25 – 25 ppm/(cid:176) C (S Grade) – 30 Gain Error3 – 30 – 30 ppm/(cid:176) C (S Grade) – 40 Gain Error4 – 20 – 20 ppm/(cid:176) C POWER SUPPLY REJECTION5 V (+5 V – 0.25 V) – 4 – 4 LSB CC (S Grade) – 5 V (+5 V – 0.25 V) – 4 – 4 LSB LOGIC (S Grade) – 5 V (–5 V – 0.25 V) – 4 – 4 LSB EE (S Grade) – 5 ANALOG INPUT Input Ranges Bipolar –2.5 +2.5 –2.5 +2.5 Volts –5.0 +5.0 –5.0 +5.0 Volts Unipolar 0 +2.5 0 +2.5 Volts 0 +5.0 0 +5.0 Volts Input Resistance (0 V to +2.5 V or – 2.5 V Range) 10 10 MW (0 V to +5.0 V or – 5 V Range) 8 10 12 8 10 12 kW Input Capacitance 10 10 pF Aperture Delay 15 15 ns Aperture Jitter 20 20 ps INTERNAL VOLTAGE REFERENCE Output Voltage 2.475 2.5 2.525 2.475 2.5 2.525 Volts Output Current Unipolar Mode +2.5 +2.5 mA Bipolar Mode +1.0 +1.0 mA LOGIC INPUTS High Level Input Voltage, V 2.0 2.0 Volts IH Low Level Input Voltage, V 0.8 0.8 Volts IL High Level Input Current, I (V = V ) –10 +10 –10 +10 m A IH IN LOGIC Low Level Input Current, I (V = 0 V) –10 +10 –10 +10 m A LL IN Input Capacitance, C 5 5 pF IN LOGIC OUTPUTS High Level Output Voltage, V (I = 0.5 mA) 2.4 2.4 Volts OH OH Low Level Output Voltage, V (I = 1.6 mA) 0.4 0.4 Volts OL OL POWER SUPPLIES Operating Voltages V +4.75 +5.25 +4.75 +5.25 Volts CC V +4.5 +5.5 +4.5 +5.5 Volts LOGIC V –4.75 –5.25 –4.75 –5.25 Volts EE Operating Current I 55 68 55 68 mA CC I 6 3 5 3 5 mA LOGIC I –55 –68 –55 –68 mA EE POWER CONSUMPTION 570 750 570 750 mW TEMPERATURE RANGE (SPECIFIED) J/K 0 +70 0 +70 (cid:176) C A –40 +85 –40 +85 (cid:176) C S –55 +125 –55 +125 (cid:176) C NOTES 1Adjustable to zero with external potentiometers. 2Includes internal voltage reference error. 3+25(cid:176)C to TMIN and +25(cid:176)C to TMAX 4Excludes internal reference drift. 5Change in gain error as a function of the dc supply voltage. 6Tested under static conditions. See Figure 15 for typical curve of ILOGIC vs. load capacitance at maximum tC. Specifications subject to change without notice. –2– REV. B

AD1671 (T to T with V = +5 V (cid:54) 5%, V = +5 V (cid:54) 10%, V = –5 V (cid:54) 5%, f = 1 MSPS, AC SPECIFICATIONS MIN MAX CC LOGIC EE SAMPLE f = 1OO kHz, unless otherwise noted)1 lNPUT AD1671J/A/S AD1671K Parameter Min Typ Max Min Typ Max Units SIGNAL-TO-NOISE PLUS DISTORTION RATIO (S/N + D) –0.5 dB Input 68 70 68 71 dB –20 dB Input 50 51 dB EFFECTIVE NUMBER OF BITS (ENOB) 11.2 11.2 Bits TOTAL HARMONIC DISTORTION (THD) –80 –75 –83 –75 dB PEAK SPURIOUS OR PEAK HARMONIC COMPONENT –80 –77 –81 –77 dB SMALL SIGNAL BANDWIDTH 12 12 MHz FULL POWER BANDWIDTH 2 2 MHz INTERMODULATION DISTORTION (IMD)2 2nd Order Products –80 –75 –80 –75 dB 3rd Order Products –85 –75 –85 –75 dB NOTES 1f amplitude = –0.5 dB (9.44 V p-p) bipolar mode full scale unless otherwise indicated. All measurements referred to a 0 dB (– 5 V) input signal, unless otherwise IN indicated. 2f = 99 kHz, f = 100 kHz with f = 1 MSPS. A B SAMPLE Specifications subject to change without notice. (For all grades T to T with V = +5 V (cid:54) 5%, V = +5 V (cid:54) 10%, SWITCHING SPECIFICATIONS MIN MAX CC LO61C V = –5 V (cid:54) 5%; V = 0.8 V, V = 2.0 V, V = 0.4 V and V = 2.4 V) EE IL IH OL OH Parameters Symbol Min Typ Max Units Conversion Time t 800 ns C Sample Rate F 1.25 MSPS S ENCODE Pulse Width High (Figure 1a) t 20 50 ns ENC ENCODE Pulse Width Low (Figure 1b) t 20 ns ENCL DAV Pulse Width t 150 300 ns DAV ENCODE Falling Edge Delay t 0 ns F Start New Conversion Delay t 0 ns R Data and OTR Delay from DAV Falling Edge t 1 20 75 ns DD Data and OTR Valid before DAV Rising Edge t 2 20 75 ns SS NOTES 1t is measured from when the falling edge of DAV crosses 0.8 V to when the output crosses 0.4 V or 2.4 V with a 25 pF load capacitor on each output pin. DD 2t is measured from when the outputs cross 0.4 V or 2.4 V to when the rising edge of DAV crosses 2.4 V with a 25 pF load capacitor on each output pin. SS Specifications subject to change without notice. t ENC t C ENCODE t ENCL tC ENCODE t R t t t DAV F R DAV t DAV DAV tDD tSS M S BBIT, 1O–T1R2 DATA 0 (PREVIOUS) DATA 1 tDD tSS BIT 1–12 DATA 0 (PREVIOUS) DATA 1 MSB, OTR Figure 1a.Encode Pulse HIGH Figure 1b.Encode Pulse LOW REV. B –3–

AD1671 PIN DESCRIPTION Symbol Pin No. Type Name and Function ACOM 27 P Analog Ground. AIN 22, 23 AI Analog Inputs, AIN1 and AIN2. The AD1671 can be pin strapped for four input ranges: Range Pin Strap Signal Input 0 to +2.5 V, – 2.5 V Connect AIN1 to AIN2 AIN1 or AIN2 0 to +5 V, – 5 V Connect AIN1 or AIN2 to ACOM AIN1 or AIN2 BIT 1 (MSB) 13 DO Most Significant Bit. BIT 2–BIT 11 12-3 DO Data Bits 2 through 11. BIT 12 (LSB) 2 DO Least Significant Bit. BPO/UPO 26 AI Bipolar or Unipolar Configuration Pin. See section on Input Range Connections for details. DAV 16 DO Data Available Output. The rising edge of DAV indicates an end of conversion and can be used to latch current data into an external register. The falling edge of DAV can be used to latch previous dam into an external register. DCOM 19 P Digital Ground. ENCODE 17 DI The analog input is sampled on the rising edge of ENCODE. MSB 14 DO Inverted Most Significant Bit. Provides twos complement output data format. OTR 15 DO Out of Range is Active HIGH when the analog input is out of range. See Output Data Format, Table III. REF COM 20 AI REF COM is the internal reference ground pin. REF COM should be connected as indicated in the Grounding and Decoupling Rules and Optional External Reference Connection Sections. REF IN 24 AI REF IN is the external 2.5 V reference input. REF OUT 21 AO REF OUT is the internal 2.5 V reference output. SHA OUT 25 AO No Connect for bipolar input ranges. Connect SHA OUT to BPO/UPO for unipolar input ranges. V 28 P +5 V Analog Power. CC V 1 P –5 V Analog Power. EE V 18 P +5 V Digital Power. LOGIC TYPE: AI = Analog Input; AO = Analog Output; DI = Digital Input; DO = Digital Outputs; P = Power. PIN CONFIGURATION VEE 1 28 VCC BIT 12 (LSB) 2 27 ACOM BIT 11 3 26 BPO/UPO BIT 10 4 25 SHA OUT BIT 9 5 24 REF IN BIT 8 6 23 AIN1 BIT 7 7 AD1671 22 AIN2 TOP VIEW BIT 6 8 (Not to Scale) 21 REF OUT BIT 5 9 20 REF COM BIT 4 10 19 DCOM BIT 3 11 18 VLOGIC BIT 2 12 17 ENCODE BIT 1 (MSB) 13 16 DAV MSB 14 15 OTR –4– REV. B

AD1671 ABSOLUTE MAXIMUM RATINGS* ORDERING GUIDE Parameter With Respect to Min Max Units Temperature Package Model1 Linearity Range Option2, 3 V ACOM –0 5 +6.5 Volts CC VEE ACOM –6.5 +0.5 Volts AD1671JQ – 2.5 LSB 0(cid:176) C to +70(cid:176) C Q-28 VLOGIC DCOM –0.5 +6.5 Volts AD1671KQ – 2 LSB 0(cid:176) C to +70(cid:176) C Q-28 ACOM DCOM –1.0 +1.0 Volts AD1671JP – 2.5 LSB 0(cid:176) C to +70(cid:176) C P-28A VCC VLOGIC –6.5 +6.5 Volts AD1671KP – 2 LSB 0(cid:176) C to +70(cid:176) C P-28A ENCODE DCOM –0.5 VLOGIC + 0.5 Volts AD1671AQ – 2.5 LSB –40(cid:176) C to +85(cid:176) C Q-28 REF IN ACOM –0.5 VCC + 0.5 Volts AD1671AP – 2.5 LSB –40(cid:176) C to +85(cid:176) C P-28A AIN ACOM –11.0 +11.0 Volts AD1671SQ – 3 LSB –55(cid:176) C to +125(cid:176) C Q-28 BPO/UPO ACOM –0.5 V + 0.5 Volts CC Junction Temperature +150 (cid:176) C NOTES Storage Temperature –65 +150 (cid:176) C 1For details on grade and package offerings screened in accordance with MIL-STD-883, refer to Analog Devices’ Military Products Databook or Lead Temperature (10 sec) +300 (cid:176) C current AD1671/883 data sheet. 2P = Plastic Leaded Chip Carrier, Q = Cerdip. *Stresses above those listed under “Absolute Maximum Ratings” may cause 3Analog Devices reserves the right to ship side brazed ceramic packages in permanent damage to the device. This is a stress rating only and functional lieu of cerdip. operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may effect device reliability. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily WARNING! accumulate on the human body and test equipment and can discharge without detection. Although the AD1671 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. ESD SENSITIVE DEVICE REV. B –5–

AD1671 DEFINITIONS OF SPECIFICATIONS DYNAMIC SPECIFICATIONS INTEGRAL NONLINEARITY (INL) SIGNAL-TO-NOISE PLUS DISTORTION (S/ N+D) RATIO Integral nonlinearity refers to the deviation of each individual S/N+D is the ratio of the rms value of the measured input signal code from a line drawn from “zero” through “full scale.” The to the rms sum of all other spectral components, including har- point used as “zero” occurs 1/2 LSB (1.22 mV for a 10 V span) monics but excluding dc. The value for S/N+D is expressed in before the first code transition (all zeros to only the LSB on). decibels. “Full-scale” is defined as a level 1 1/2 LSB beyond the last code transition (to all ones). The deviation is measured from the low EFFECTIVE NUMBER OF BITS (ENOB) side transition of each particular code to the true straight line. ENOB is calculated from the expression (S/N+D) = 6.02N + 1.76 dB, where N is equal to the effective number of bits. DIFFERENTIAL LINEARITY ERROR (NO MISSING CODES) TOTAL HARMONIC DISTORTION (THD) An ideal ADC exhibits code transitions that are exactly 1 LSB THD is the ratio of the rms sum of the first six harmonic com- apart. DNL is the deviation from the ideal value. Thus every ponents to the rms value of the measured input signal and is ex- code has a finite width. Guaranteed no missing codes to 11- or pressed as a percentage or in decibels. 12-bit resolution indicates that all 2048 and 4096 codes, respec- tively, must be present over all operating ranges. No missing INTERMODULATION DISTORTION (IMD) codes to 11 bits (in the case of a 12-bit resolution ADC) also With inputs consisting of sine waves at two frequencies, fa and means that no two consecutive codes are missing. fb, any device with nonlinearities will create distortion products of order (m + n), at sum and difference frequencies of mfa – UNIPOLAR OFFSET nfb, where m, n = 0, 1, 2, 3....Intermodulation terms are The first transition should occur at a level 1/2 LSB above analog those for which m or n is not equal to zero. For example, the common. Unipolar offset is defined as the deviation of the ac- second order terms are (fa + fb) and (fa – fb), and the third or- tual from that point. This offset can be adjusted as discussed der terms are (2 fa + fb), (2 fa – fb), (fa + 2 fb) and (2fb – fa). later. The unipolar offset temperature coefficient specifies the The IMD products are expressed as the decibel ratio of the rms maximum change of the transition point over temperature, with sum of the measured input signals to the rms sum of the distor- or without external adjustments. tion terms. The two signals are of equal amplitude and the peak value of their sum is –0.5 dB from full scale. The IMD products BIPOLAR ZERO are normalized to a 0 dB input signal. In the bipolar mode the major carry transition (0111 1111 1111 to 1000 0000 0000) should occur for an analog value 1/2 LSB be- PEAK SPURIOUS OR PEAK HARMONIC COMPONENT low analog common. The bipolar offset error and temperature The peak spurious or peak harmonic component is the largest coefficient specify the initial deviation and maximum change in spectral component, excluding the input signal and dc. This the error over temperature. value is expressed in decibels relative to the rms value of a full- scale input signal. GAIN ERROR The last transition (from 1111 1111 1110 to 1111 1111 1111) APERTURE DELAY should occur for an analog value 1 1/2 LSB below the nominal Aperture delay is the difference between thc switch delay and full scale (4.9963 volts for 5.000 volts full scale). The gain error the analog delay of the SHA. This delay represents the point in is the deviation of the actual level at the last transition from the time, relative to the rising edge of ENCODE input, that the ideal level. The gain error can be adjusted to zero as shown in analog input is sampled. Figures 4 through 7. APERTURE JITTER TEMPERATURE COEFFICIENTS Aperture jitter is the variation in aperture delay for successive The temperature coefficients for unipolar offset, bipolar zero samples. and gain error specify the maximum change from the initial (+25(cid:176) C) value to the value at T or T . MIN MAX FULL POWER BANDWIDTH The input frequency at which the amplitude of the recon- POWER SUPPLY REJECTION structed fundamental is reduced by 3 dB for a full-scale input. One of the effects of power supply error on the performance of the device will be a small change in gain. The specifications show the maximum full-scale change from the initial value with the supplies at the various limits. –6– REV. B

AD1671 THEORY OF OPERATION an input range that is configured with one bit of overlap with the The AD1671 uses a successive subranging architecture. The previous DAC. The overlap allows for errors during the flash analog-to-digital conversion takes place in four independent conversion. The first residue voltage is connected to the second steps or flashes. The sampled analog input signal is subranged 3-bit flash and to the noninverting input of a high speed, differ- to an intermediate residue voltage for the final 12-bit result by ential, gain of eight amplifier. The second flash result is passed utilizing multiple flashes with subtraction DACs (see the AD1671 to the correction logic register and to the second segmented cur- functional block diagram). rent output DAC. The output of the second DAC is connected The AD1671 can be configured to operate with unipolar (0 V to to the inverting input of the differential amplifier. The differen- +5 V, 0 V to +2.5 V) or bipolar (– 5 V, – 2.5 V) inputs by con- tial amplifier output is connected to a two-step, backend, 8-bit necting AIN (Pins 22, 23), SHA OUT (Pin 25) and BPO/UPO flash. This 8-bit flash consists of coarse and fine flash convert- (Pin 26) as shown in Figure 2. ers. The result of the coarse 4-bit flash converter, also config- ured to overlap one bit of DAC 2, is connected to the correction logic register and selects one of 16 resistors from which the fine 0 AIN1 5k –2.5V AIN1 5k 4-bit flash will establish its span voltage. The fine 4-bit flash is TO SHA TO SHA +2.5V +2.5V connected directly to the output latches. AIN2 5k AIN2 5k The internal timing generator automatically places the SHA into the acquire mode when DAV goes LOW. Upon completion of SHA OUT SHA OUT conversion (when DAV is set HIGH), the SHA has acquired the AD1671 AD1671 analog input to the specified level of accuracy and will remain in BPO/UPO BPO/UPO the sample mode until the next ENCODE command. The AD1671 will flag an out-of-range condition when the input REF IN REF IN voltage exceeds the analog input range. OTR (Pin 15) is active HIGH when an out-of-range high or low condition exists. Bits REF OUT REF OUT 1–12 are HIGH when the analog input voltage is greater than a. 0 V to +2.5V Input Range b. – 2.5 V Input Range the selected input range and LOW when the analog input is less than the selected input range. 0 AIN1 5k AIN1 5k TO SHA – 5V SHA AD1671 DYNAMIC PERFORMANCE +5V The AD1671 is specified for dc and dynamic performance. A AIN2 5k AIN2 5k sampling converter’s dynamic performance reflects both quan- tizer and sample-and-hold amplifier (SHA) performance. Quan- SHA OUT SHA OUT tizer nonlinearities, such as INL and DNL, can degrade dynamic AD1671 AD1671 performance. However, a SHA is the critical element which has to BPO/UPO BPO/UPO accurately sample fast slewing analog input signals. The AD1671’s high performance, low noise, patented on-chip SHA minimizes REF IN REF IN distortion and noise specifications. Nonlinearities are minimized by using a fast slewing, low noise architecture and subregulation REF OUT REF OUT of the sampling switch to provide constant offsets (therefore reducing input signal dependent nonlinearities). c. 0 V to +5 V Input Range d. – 5 V Input Range Figure 3 is a typical 2k point Fast Fourier Transform (FFT) Figure 2.AD1671 Input Range Connections plot of a 100 kHz input signal sampled at 1 MHz. The funda- mental amplitude is set at –0.5 dB to avoid input signal clipping The AD1671 conversion cycle begins by simply providing an of offset or gain errors. Note the total harmonic distortion is ap- active HIGH level on the ENCODE pin (Pin 17). The rising proximately –81 dB, signal to noise plus distortion is 71 dB and edge of the ENCODE pulse starts the conversion. The falling the spurious free dynamic range is 84 dB. edge of the ENCODE pulse is specified to operate within a win- dow of time, less than 50 ns after the rising edge of ENCODE 0 or after the falling edge of DAV. The time window prevents digitally coupled noise from being introduced during the final B –25 stages of conversion. An internal timing generator circuit accu- – d E rately controls SHA, flash and DAC timing. D TU –50 Upon receipt of an ENCODE command the input voltage is LI P M held by the front-end SHA and the first 3-bit flash converts the A –75 L analog input voltage. The 3-bit result is passed to a correction A N logic register and a segmented current output DAC. The DAC SIG –100 output is connected through a resistor (within the Range/Span Select Block) to SHA OUT. A residue voltage is created by sub- tracting the DAC output from SHA OUT, which is less than 0 FREQUENCY one eighth of the full-scale analog input. The second flash has Figure 3.AD1671 FFT Plot, f = 100 kHz, f = 1 MHz IN SAMPLE REV. B –7–

AD1671 Figure 4 plots both S/(N+D) and Effective Number of Bits B 85 d (ENOB) for a 100 kHz input signal sampled from 666 kHz to E – 80 G 1.25 MHz. AN 75 R C 70 MI 72.5 11.75 NA 65 Y 72 TS E D 60 71.5 F BI FRE 55 S/(N+D) – dB7077.501 11.50E NUMBER O SPURIOUS 454005 69.5 11.25TIV –50 –45 –40 –35 –30 –25 –20 –15 –10 –5 0 69 EC ANALOG INPUT – dB F 68.5 EF Figure 7.Spurious Free Dynamic Range vs. Input 68 11.00 Amplitude, fIN = 250 kHz 666 714 769 833 909 1000 1111 1250 SAMPLING FREQUENCY – kHz APPLYING THE AD1671 Figure 4.S/(N/D) vs. Sampling Frequency, f = 100 kHz IN GROUNDING AND DECOUPLING RULES Figure 5 is a THD plot for a full-scale 100 kHz input signal with Proper grounding and decoupling should be a primary design the sample frequency swept from 666 kHz to 1.25 MHz. objective in any high speed, high resolution system. The AD1671 separates analog and digital grounds to optimize the management of analog and digital ground currents in a system. –68 The AD1671 is designed to minimize the current flowing from –70 REF COM (Pin 20) by directing the majority of the current –72 from VCC (+5 V–Pin 28) to VEE (–5 V–Pin 1). Minimizing ana- –74 log ground currents hence reduces the potential for large ground voltage drops. This can be especially true in systems that do not B –76 HD – d –78 ucotinlifzieg ugrreodu ntod bpel acnoedse o irn wdeidpee ngdroenutn,d t hreurnesf.o RreE rFed CuOcinMg iisn palusto de- T –80 pendent analog ground voltage drops and errors. Code depen- –82 dent ground current is diverted to ACOM (Pin 27). Also critical –84 in any high speed digital design is the use of proper digital –86 grounding techniques to avoid potential CMOS “ground 666 714 769 833 909 1000 1111 1250 bounce.” Figure 3 is provided to assist in the proper layout, SAMPLING FREQUENCY – kHz grounding and decoupling techniques. Figure 5.THD vs. Sampling Rate, f = 100 kHz IN The AD1671’s SFDR performance is ideal for use in communi- +5V –5V +5V cation systems such as high speed modems and digital radios. The SFDR is better than 84 dB with sample rates up to 1.11 MHz 0.1m F 10m F 0.1m F 10m F 0.1m F 10m F and increases as the input signal amplitude is attenuated by ap- proximately 3 dB. Note also the SFDR is typically better than 80 dB with input signals attenuated by up to –7 dB. 28 1 18 VCC VEE VLOGIC 23 AIN1 BIT 1 13 B –68 AD1671 d E – –70 VI N (– 5V) 22 AIN2 BIT 12 2 G –72 N RA –74 20 REF COM NAMIC ––7768 AGP* 27 ACOM ENCODE 17 EE DY ––8820 DGP* 19 DCOM DAV 16 R OUS F ––8864 25 SHA OUT OTR 15 URI –88 26 BPO/UPO MSB 14 P S –90 24 REF IN 666 714 769 833 909 1000 1111 1250 SAMPLING FREQUENCY – kHz 21 REF OUT Figure 6.Spurious Free Dynamic Range vs. Sampling 1m F Rate, f = 100 kHz IN *GROUND PLANE RECOMMENDED Figure 8.AD1671 Grounding and Decoupling –8– REV. B

AD1671 Table I is a list of grounding and decoupling rules that should The gain trim is done by applying a signal 1 1/2 LSBs below the be reviewed before laying out a printed circuit board. nominal full scale (4.998 V for a 5 V range). Trim R2 to give the last transition (1111 1111 1110 to 1111 1111 1111). This Table I. Grounding and Decoupling Guidelines circuit will give approximately – 0.5% FS of adjustment range. Power Supply Decoupling Comment 0 TOVIN +5V 25W AIN1 5k SHA Capacitor Values 0.1 m F (Ceramic) and 1 m F +5V 50k AIN2 5k (Tantalum) Surface Mount Chip OFFSET R1 ADJ 10k Capacitors Recommended to Reduce Lead Inductance –5V GAADINJ R502W SHA OUTAD1671 Capacitor Locations Directly at Positive and Negative BPO/UPO Supply Pins to Common Ground Plane REF IN Reference (REF OUT) REF OUT 1µF Capacitor Value 1 m F (Tantalum) to ACOM Grounding Figure 9.Unipolar (0 V to +5 V) Calibration Analog Ground Ground Plane or Wide Ground BIPOLAR ((cid:54)5 V) CALIBRATION Return Connected to the Analog The connections for the bipolar – 5 V input range is shown in Power Supply Figure 10. Reference Ground Critical Common Connections (REF COM) SChOoMuld ( abse SShtoawr Cn oinn nFeicgtuerde t8o) REF –5V TVOIN +5V 25W AIN1 5k SHA +5V Digital Ground Ground Plane or Wide Ground 50k AIN2 5k Return Connected to the Digital OFFASEDTJ 1R0k1 Power Supply –5V R2 SHA OUT Analog and Digital Ground Connected Together Once at the GAADINJ 50W AD1671 AD1671 BPO/UPO REF IN UNIPOLAR (0 V TO +5 V) CALIBRATION The AD1671 is factory trimmed to minimize offset, gain and REF OUT 1µF linearity errors. In some applications the offset and gain errors of the AD1671 need to be externally adjusted to zero. This is accomplished by trimming the voltage at AIN2 (Pin 22). The Figure 10. Bipolar (– 5 V) Calibration circuit in Figure 9 is recommended for calibrating offset and Bipolar calibration is similar to unipolar calibration. First, a sig- gain errors of the AD1671 when configured in the 0 V to +5 V nal 1/2 LSB above negative full scale (–4.9988 V) is applied and input range. If the offset trim resistor R1 is used, it should be R1 is trimmed to give the first transition (0000 0000 0000 to trimmed as follows, although a different offset can be set for a 0000 0000 0001). Then a signal 1 1/2 LSB below positive full particular system requirement. This circuit will give approxi- scale (+4.9963 V) is applied and R2 is trimmed to give the last mately – 5 mV of offset trim range. Nominally the AD1671 is transition (1111 1111 1110 to 1111 1111 1111). intended to have a 1/2 LSB offset so that the exact analog input for a given code will be in the middle of that code (halfway be- tween the transitions to the codes above it and below it). Thus, the first transition (from 0000 0000 0000 to 0000 0000 0001) will occur for an input level of +1/2 LSB (0.61 mV for 5 V range). REV. B –9–

AD1671 UNIPOLAR (0 V TO +2.5 V) CALIBRATION and t minimum). To satisfy the requirements of the 574 type SS The connections for the 0 V to +2.5 V input range calibration is latch the recommended logic families are S, AS, ALS, F or shown in Figure 11. Figure 11 shows an example of how the BCT. New data from the AD1671 is latched on the rising edge offset error can be trimmed in front of the AD1671. The proce- of the DAV (Pin 16) output pulse. Previous data can be latched dure for trimming the offset and gain errors is the same as for by inverting the DAV output with a 7404 type inverter. the unipolar 5 V range. DATA BUS 74HC574 +15V BIT 1 1D 1Q BIT 2 2D 2Q VIN 390W BIT 3 3D 3Q BIT 4 4D 4Q 0 TO +2.5V OFFSET ADJ BIT 5 5D 5Q R1 BIT 6 6D 6Q 1kW BIT 7 7D 7Q GAADINJ R22k AIN1 5k BIT 8 8D 8Q AD845 SHA DAV CLOCK OC 10k AIN2 5k 1k 74HC574 BIT 9 1D 1Q 10k SHA OUATD1671 BBIITT 1101 32DD 32QQ BIT 12 4D 4Q BPO/UPO 5D 5Q 6D 6Q REF IN 7D 7Q AD1671 8D 8Q 3-STATE CLOCK OC REF OUT CONTROL 1µF Figure 13.AD1671 to Output Latches Figure 11. Unipolar (0 V to +2.5 V) Calibration OUT OF RANGE An out-of-range condition exists when the analog input voltage BIPOLAR ((cid:54)2.5 V) CALIBRATION is beyond the input range (0 V to +2.5 V, 0 V to +5 V, – 2.5 V, The connections for the bipolar – 2.5 V input range is shown in – 5 V) of the converter OTR (Pin 15) is set low when the analog Figure 12. input voltage is within the analog input range. OTR is set HIGH and will remain HIGH when the analog input voltage exceeds +15V the input range by typically 1/2 LSB (OTR transition is tested to – 6 LSBs of accuracy) from the center of the – full-scale output VIN 390W codes. OTR will remain HIGH until the analog input is within –2.5V TO +2.5V OFFSET ADJ the input range and another conversion is completed. By logical R1 ANDing OTR with the MSB and its complement, overrange 1kW high or underrange low conditions can be detected. Table II is a GAADINJ R22k AD845 AIN1 5k SHA truth table for the over/under range circuit in Figure 14. Sys- tems requiring programmable gain conditioning prior to the 10k AIN2 5k 1k AD1671 can immediately detect an out-of-range condition, thus eliminating gain selection iterations. 10k SHA OUT AD1671 Table II. Out-of-Range Truth Table BPO/UPO OTR MSB Analog Input Is REF IN 0 0 In Range REF OUT 0 1 In Range 1µF 1 0 Underrange 1 1 Overrange Figure 12.Bipolar (– 2.5 V) Calibration OUTPUT LATCHES MSB Figure 13 shows the AD1671 connected to the 74HC574 octal OVER = "1" OTR D-type edge-triggered latches with 3-state outputs. The latch can drive highly capacitive loads (i.e., bus lines, I/O ports) while maintaining the data signal integrity. The maximum setup and hold times of the 574 type latch must be less than 20 ns (tDD UNDER = "1" MSB Figure 14. Overrange or Underrange Logic –10– REV. B

AD1671 Table III. Output Data Format Input Analog Digital Range Coding Inputl Output OTR2 0 V to +2.5 V Straight Binary £ –0.0003 V 000000000000 1 0 V 000000000000 0 +2.5 V 111111111111 0 ‡ +2.5003 V 111111111111 1 0 V to +5 V Straight Binary £ –0.0006 V 0000 0000 0000 1 0 V 000000000000 0 +5 V 111111111111 0 ‡ +5.0006 V 111111111111 1 –2.5 V to +2.5 V Offset Binary £ –2.5006 V 000000000000 1 –2.5 V 0000 0000 0000 0 +2.5 V 1111 1111 1111 0 ‡ +2.4994 V 111111111111 1 –5 V to +5 V Offset Binary £ –5.0012 V 0000 0000 0000 1 –5 V 0000 0000 0000 0 +5 V 111111111111 0 ‡ +4.9988 V 111111111111 1 –2.5 V to +2.5 V Twos Complement £ –2.5006 V 100000000000 1 (Using MSB) –2.5 V 100000000000 0 +2.5 V 011111111111 0 ‡ +2.4994 V 011111111111 1 –5 V to +5 V Twos Complement £ –5.0012 V 100000000000 1 (Using MSB) –5 V 1000 0000 0000 0 +5 V 011111111111 0 ‡ +4.9988 V 011111111111 1 NOTES 1Voltages listed are with offset and gain errors adjusted to zero. 2Typical performance. OUTPUT DATA FORMAT connected to +5 V. It is possible to connect REF OUT to +5 V The AD1671 provides both MSB and MSB outputs, delivering due to its output circuit implementation which shuts down the data in positive true straight binary for unipolar input ranges reference. and positive true offset binary or twos complement for bipolar input ranges. Straight binary coding is used for systems that ac- ILOGIC VS. CONVERSION RATE cept positive-only signals. If straight binary coding is used with Figure 15 is the typical logic supply current vs. conversion rate bipolar input signals, a 0 V input would result in a binary output for various capacitor loads on the digital outputs. of 2048. The application software would have to subtract 2048 to determine the true input voltage. Host registers typically per- 6.5 form math on signed integers and assume data is in that format. 6.0 Twos complement format minimizes software overhead which is 5.5 especially important in high speed data transfers, such as a 5.0 DMA operation. The CPU is not bogged down performing data 4.5 conversion steps, hence the total system throughput is increased. 4.0 mA 3.5 CL = 50pF OPTIONAL EXTERNAL REFERENCE 3.0 The AD1671 includes an onboard +2.5 V reference. The refer- 2.5 ence input pin (REF IN) can be connected to reference output pin (REF OUT) or a standard external +2.5 V reference can be 2.0 CL = 30pF selected to meet specific system requirements. Fast switching in- 1.5 put dependent currents are modulated at the reference input. 1.0 CL = 0pF The reference input voltage can be held with the use of a capaci- 0.5 tor. To prevent the AD1671’s onboard reference from oscil- 1k 10k 100k 1M CONVERSION RATE – Hz lating when not connected to REF IN, REF OUT must be Figure 15.I vs. Conversion Rate for Various LOGIC Capacitive Loads on the Digital Outputs REV. B –11–

AD1671 APPLICATIONS AD1671 TO ADSP-2101/2102 AD1671 TO ADSP-2100A Figure 17 is identical to the 2100A interface except the sam- Figure 16 demonstrates the AD1671 to ADSP-2100A interface. pling clock is used to generate an interrupt (IRQ2) for the pro- The 2100A with a clock frequency of 12.5 MHz can execute an cessor. Upon interrupt the ADSP-2100A starts a data memory instruction in one 80 ns cycle. The AD1671 is configured to read by providing an address on the address (A) bus. The de- perform continuous time sampling. The DAV output of the code address generates OE for the D-latches and the processor AD1671 is asserted at the end of each conversion. DAV can be reads their output over the Data (D) bus. Reading the conver- used to latch the conversion result into the two 574 octal sion result is thus completed within a single processor cycle. D-latches. The falling edge of the sampling clock is used to generate an interrupt (IRQ3) for the processor. Upon interrupt, the ADSP-2100A starts a data memory read by providing an RD OE DAV address on the DMA bus. The decoded address generates OE A0:13 ADDRESS BUS 8 574 for the latches and the processor reads their output over the Q0:7 AD1671 DMA bus. The conversion result is read within a single proces- DECODE 8 ADSP-2101 D0:7 sor cycle. 16 OE BIT1:12 DMRD OE DAV D0:15 DATA BUS 574 4 8 D0:3 574 DMA0:13 ADDRESS BUS 8 Q0:7 4 D0:7 Q0:7 8 AD1671 DECODE SAMPLING ADSP- D0:7 IRQ2 CLOCK ENCODE 2100A 16 OE BIT1:12 Figure 17.AD1671 to ADSP-2101/ADSP-2102 Interface 574 DMA0:15 DATA BUS 4 8 D0:3 DMACK +5V Q0:7 4 D0:7 SAMPLING IRQ3 ENCODE CLOCK Figure 16.AD1671 to ADSP-2100A Interface –12– REV. B

AD1671 COMPONENT LIST Parts List Type Reference Designator Description R1, R2 Resistor, 5%, 0.5 W, 100 W R3, R4, R5 Resistor, 1%, 49.9 W R6 100 W Trim Potentiometer R7 Resistor 1%, 4.99 kW Optional R8 X W Trim Potentiometer, Optional R9, R11 Resistor, 1%, 4.99 kW R10 Resistor, 1%, 10 kW R12 Resistor, 1%, 2.49 kW R13 Resistor, 1%, 787 W R14 Resistor, 1%, 249 W R15–R28 Resistor, 5%, 22 W C1, C3, C5 Cap, Tantalum, 22 m F C2, C4, C6, C8, C10 Cap, Ceramic, 0.01 m F C7, C9, C15, C16 Cap, Tantalum, 10 m F C11, C12, C13, C14, C17 Cap, Ceramic, 0.1 m F C18 Cap, Ceramic, 1.0 m F C19–C22 Cap, Ceramic, 0.1 m F C23 Cap, Mica, 100 pF C24 Cap, Ceramic, 0.001 m F U1 78L05 +5 V Regulator U2 79L05 –5 V Regulator U3 AD1671 U4–U5 74HC573 Drivers U6 AD568 W1–W3 BNC Jacks J1–J15 Jumpers and Headers Metal Binding Posts S1 Wide 28-Pin Socket S2 Narrow 20-Pin Socket S3 Narrow 24-Pin Socket SW1–SW3 SECMA SPDT Switch TP1, TP2, TP4–TP6 Test Point, Red TP3, TP7, TP10, TP13 Test Point, Black TP8, TP9, TP11, TP12, TP14 Test Point, White P1 40-Pin Connector Male + Hooks REV. B –13–

AD1671 Figure 18.AD1671/EB PCB Layout—Silkscreen Layer –14– REV. B

AD1671 Figure 19. AD1671/EB PCB Layout—Component Side Figure 20. AD1671/EB PCB Layout—Solder Side REV. B –15–

AD1671 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 28-Lead PLCC (P-28A) Package 3 9 0/ 1 – 0 1 – a 6 1 6 1 C 28-Pin Cerdip (Q-28) Package A. S. U. N D I E T N RI P –16– REV. B