ACPL-330J 1.5 Amp Output Current IGBT Gate Driver Optocoupler with Integrated (V ) Desaturation Detection, UVLO, CE Fault Feedback, Active Miller Clamp and Auto-Fault Reset Data Sheet Lead (Pb) Free RoHS 6 fully compliant RoHS 6 fully compliant options available; -xxxE denotes a lead-free product Description Features The ACPL-330J is an advanced 1.5 A output current, easy- • 1.5 A maximum peak output current to-use, intelligent gate driver which makes IGBT VCE fault • 1.0 A minimum peak output current protection compact, affordable, and easy-to implement. • 250 ns maximum propagation delay over Features such as integrated VCE detection, under temperature range voltage lockout (UVLO), “soft” IGBT turn-off, isolated open collector fault feedback and active Miller clamping • 1.0A Active Miller Clamp. Clamp pin short to VEE if not provide maximum design flexibility and circuit protec- in used tion. • Miller Clamping The ACPL-330J contains a AlGaAs LED. The LED is • Desaturation Detection optically coupled to an integrated circuit with a power • Under Voltage Lock-Out Protection (UVLO) output stage. ACPL-330J is ideally suited for driving with Hysteresis power IGBTs and MOSFETs used in motor control inverter applications. The voltage and current supplied by these • Open Collector Isolated fault feedback optocouplers make them ideally suited for directly • “Soft” IGBT Turn-off driving IGBTs with ratings up to 1200 V and 100 A. For • Automatic Fault Reset after fixed Mute Time , typically IGBTs with higher ratings, the ACPL-330J can be used to 26ms drive a discrete power stage which drives the IGBT gate. The ACPL-330J has an insulation voltage of VIORM = 1414 • Available in SO-16 package VPEAK. • 100 ns maximum pulse width distortion (PWD) Block Diagram • 50 kV/µs minimum common mode rejection (CMR) at VCM = 1500 V 13 VCC2 • ICC(max) < 5 mA maximum supply current UVLO 6, 7 D • Wide VCC operating range: 15 V to 30 V over ANODE R temperature range CATHODE 5, 8 LED1 VEI 1114 DVOESUATT • Wide operating temperature range: –40°C to 105°C R DESAT • Safety Approvals: SHIELD 9, 12VEE UIELC,/ 5E0N0/0D VINR-MESN f o6r0 17 4m7i-n5u-5t eV, ICORSMA =A p1p4r1o4v VaPl,E AK VCLAMP 2 10 Applications VCC1 VCLAMP FAULT 3 LED2 16 VE • Isolated IGBT/Power MOSFET gate drive • AC and brushless DC motor drives • Industrial inverters and Uninterruptible Power Supply 1, 4 15 VS SHIELD VLED (UPS) CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD. The components featured in this datasheet are not to be used in military or aerospace applications or environments.

Pin Description Pin Symbol Description 1 VS Input Ground 11 VVSS VVEE 1166 2 VCC1 Positive input supply voltage. (3.3 V to 5.5 V) 3 FAULT Fault output. FAULT changes from a high impedance state 22 VV VV 1155 to a logic low output within 5 µs of the voltage on the CCCC11 LLEEDD DESAT pin exceeding an internal reference voltage of 6.5 V. FAULT output is an open collector which allows the FAULT 33 FFAAUULLTT DDEESSAATT 1144 outputs from all ACPL-330J in a circuit to be connected together in a “wired OR” forming a single fault bus for inter- 44 VV VV 1133 facing directly to the micro-controller. SS CCCC22 4 VS Input Ground 55 CCAATTHHOODDEE VV 1122 EEEE 5 CATHODE Cathode 6 ANODE Anode 66 AANNOODDEE VV 1111 OOUUTT 7 ANODE Anode 8 CATHODE Cathode 77 AANNOODDEE VV 1100 CCLLAAMMPP 9 VEE Output supply voltage. 88 CCAATTHHOODDEE VVEEEE 99 10 VCLAMP Miller clamp 11 VOUT Gate drive voltage output 12 VEE Output supply voltage. 13 VCC2 Positive output supply voltage 14 DESAT Desaturation voltage input. When the voltage on DESAT exceeds an internal reference voltage of 6.5 V while the IGBT is on, FAULT output is changed from a high impedance state to a logic low state within 5 µs. 15 VLED LED anode. This pin must be left unconnected for guaran- teed data sheet performance. (For optical coupling testing only) 16 VE Common (IGBT emitter) output supply voltage. Ordering Information ACPL-330J is UL Recognized with 5000 Vrms for 1 minute per UL1577. Option Surface IEC/EN/DIN EN Part number RoHS Compliant Package Mount Tape& Reel 60747-5-5 Quantity ACPL-330J -000E SO-16 X X 45 per tube -500E X X X 850 per reel To order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. Example 1: ACPL-330J-500E to order product of SO-16 Surface Mount package in Tape and Reel packaging with IEC/EN/DIN EN 60747-5-5 Safety Approval in RoHS compliant. Example 2: ACPL-330J-000E to order product of SO-16 Surface Mount package in tube packaging with IEC/EN/DIN EN 60747-5-5 Safety Approval and RoHS compliant. Option datasheets are available. Contact your Avago sales representative or authorized distributor for information. Remarks: The notation ‘#XXX’ is used for existing products, while (new) products launched since 15th July 2001 and RoHS compliant option will use ‘-XXXE‘. 2

Package Outline Drawings 16-Lead Surface Mount 0.457 LAND PATTERN RECOMMENDATION 1.270 (0.018) (0.050) 0.64 (0.025) 16 15 14 13 12 11 10 9 TYPE NUMBER DATE CODE AVAGO A XXXX LEAD-FREE YYWW 7.493 ± 0.254 11.63 (0.458) EEE (0.295 ± 0.010) PIN 1 DOT LOT ID 2.16 (0.085) 1 2 3 4 5 6 7 8 10.312 ± 0.254 (0.406 ± 0.10) 8.763 ± 0.254 ALL LEADS TO 9° (0.345 ± 0.010) BE COPLANAR ± 0.05 (0.002) 3.505 ± 0.127 0.457 0-8° 0.203 ± 0.076 (0.138 ± 0.005) (0.018) 0.64 (0.025) MIN. (0.008 ± 0.003) STANDOFF 10.363 ± 0.254 Dimensions in Millimeters (Inches) (0.408 ± 0.010) Floating lead protrusion is 0.25 mm (10 mils) Max. Note: Initial and continued variation in color of the white mold compound is normal and does not affect performance or reliability of the device 3

Recommended Pb-Free IR Profile Recommended reflow condition as per JEDEC Standard, J-STD-020 (latest revision). Non-Halide Flux should be used. Regulatory Information The ACPL-330J has been approved by the following organizations: IEC/EN/DIN EN 60747-5-5 Approval under: DIN EN 60747-5-5 (VDE 0884-5):2011-11 EN 60747-5-5:2011 UL Approval under UL 1577, component recognition program up to VISO = 5000 VRMS. File E55361. CSA Approval under CSA Component Acceptance Notice #5, File CA 88324. Table 1. IEC/EN/DIN EN 60747-5-5 Insulation Characteristics* Description Symbol Characteristic Unit Installation classification per DIN VDE 0110/39, Table 1 for rated mains voltage ≤ 150 Vrms I – IV for rated mains voltage ≤ 300 Vrms I – IV for rated mains voltage ≤ 600 Vrms I – IV for rated mains voltage ≤ 1000Vrms I – III Climatic Classification 40/100/21 Pollution Degree (DIN VDE 0110/39) 2 Maximum Working Insulation Voltage VIORM 1414 Vpeak Input to Output Test Voltage, Method b**, VPR 2652 Vpeak VIORM x 1.875=VPR, 100% Production Test with tm=1 sec, Partial discharge < 5 pC Input to Output Test Voltage, Method a**, VPR 2262 Vpeak VIORM x 1.6=VPR, Type and Sample Test, tm=10 sec, Partial discharge < 5 pC Highest Allowable Overvoltage (Transient Overvoltage tini = 60 sec) VIOTM 8000 Vpeak Safety-limiting values – maximum values allowed in the event of a failure Case Temperature TS 175 °C Input Current IS, INPUT 400 mA Output Power PS, OUTPUT 1200 mW Insulation Resistance at TS, VIO = 500 V RS >109 W * Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits in application. Surface mount classification is class A in accordance with CECCOO802. ** Refer to IEC/EN/DIN EN 60747-5-5 Optoisolator Safety Standard section of the Avago Regulatory Guide to Isolation Circuits, AV02-2041EN for a detailed description of Method a and Method b partial discharge test profiles. Dependence of Safety Limiting Values on Temperature. (take from DS AV01-0579EN Pg.7) 1400 PS , OUTPUT 1200 PS , INPUT 1000 W m R - 800 E W O 600 P P - S 400 200 0 0 25 50 75 100 125 150 175 200 TS - CASE TEMPERATURE - °C 4

Table 2. Insulation and Safety Related Specifications Parameter Symbol ACPL-330J Units Conditions Minimum External Air L(101) 8.3 mm Measured from input terminals to output terminals, Gap (Clearance) shortest distance through air. Minimum External L(102) 8.3 mm Measured from input terminals to output terminals, Tracking (Creepage) shortest distance path along body. Minimum Internal 0.5 mm Through insulation distance conductor to conductor, Plastic Gap (Internal usually the straight line distance thickness between the Clearance) emitter and detector. Tracking Resistance CTI >175 V DIN IEC 112/VDE 0303 Part 1 (Comparative Tracking Index) Isolation Group IIIa Material Group (DIN VDE 0110, 1/89, Table 1) Table 3. Absolute Maximum Ratings Parameter Symbol Min. Max. Units Note Storage Temperature TS -55 125 °C Operating Temperature TA -40 105 °C 2 Output IC Junction Temperature TJ 125 °C 2 Average Input Current IF(AVG) 25 mA 1 Peak Transient Input Current IF(TRAN) 1.0 A (<1 µs pulse width, 300pps) Reverse Input Voltage VR 5 V “High” Peak Output Current IOH(PEAK) 1.5 A 3 “Low” Peak Output Current IOL(PEAK) 1.5 A 3 Positive Input Supply Voltage VCC1 -0.5 7.0 V FAULT Output Current IFAULT 8.0 mA FAULT Pin Voltage VFAULT -0.5 VCC1 V Total Output Supply Voltage (VCC2 - VEE) -0.5 33 V Negative Output Supply Voltage (VE - VEE) -0.5 15 V 6 Positive Output Supply Voltage (VCC2 - VE) -0.5 33 - (VE - VEE) V Gate Drive Output Voltage VO(PEAK) -0.5 VCC2 V Peak Clamping Sinking Current IClamp 1.0 A Miller Clamping Pin Voltage VClamp -0.5 VCC2 V DESAT Voltage VDESAT VE VE + 10 V Output IC Power Dissipation PO 600 mW 2 Input IC Power Dissipation PI 150 mW 2 Solder Reflow Temperature Profile See Package Outline Drawings section Table 4. Recommended Operating Conditions Parameter Symbol Min. Max. Units Note Operating Temperature TA - 40 105 °C 2 Total Output Supply Voltage (VCC2 - VEE) 15 30 V 7 Negative Output Supply Voltage (VE - VEE) 0 15 V 4 Positive Output Supply Voltage (VCC2 - VE) 15 30 - (VE - VEE) V Input Current (ON) IF(ON) 8 12 mA Input Voltage (OFF) VF(OFF) - 3.6 0.8 V 5

Table 5. Electrical Specifications (DC) Unless otherwise noted, all typical values at TA = 25°C, VCC2 - VEE = 30 V, VE - VEE = 0 V; all Minimum/Maximum specifications are at Recommended Operating Conditions. Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Note FAULT Logic Low VFAULTL 0.1 0.4 V IFAULT = 1.1 mA, VCC1 = 5.5V Output Voltage 0.1 0.4 V IFAULT = 1.1 mA, VCC1 = 3.3V FAULT Logic High IFAULTH 0.02 0.5 µA VFAULT = 5.5 V, VCC1 = 5.5V Output Current 0.002 0.3 µA VFAULT = 3.3 V, VCC1 = 3.3V High Level IOH -0.3 -0.75 A VO = VCC2 – 4 4, 18 5 Output Current -1.0 A VO = VCC2 – 15 3 Low Level IOL 0.3 0.75 A VO = VEE + 2.5 5, 19 5 Output Current 1.0 A VO = VEE + 15 3 Low Level Output Current IOLF 90 140 230 mA VOUT - VEE = 14 V 6 During Fault Condition High Level VOH VCC-2.9 VCC-2.0 V IO = -650 µA 2, 4, 7, 8,9 Output Voltage 20 23 Low Level VOL 0.17 0.5 V IO = 100 mA 3, 5, Output Voltage 21 Clamp Pin Threshold VtClamp 2.0 V Voltage Clamp Low Level ICL 0.21 0.7 A VO = VEE + 2.5 Sinking Current High Level Supply Current ICC2H 2.5 5 mA IO = 0 mA 6, 7, 9 23 Low Level Supply Current ICC2L 2.5 5 mA IO = 0 mA Blanking Capacitor ICHG 0.13 -0.24 -0.33 mA VDESAT = 2 V 8, 24 9, 10 Charging Current Blanking Capacitor IDSCHG 10 30 mA VDESAT = 7.0 V 25 Discharge Current DESAT Threshold VDESAT 6 6.5 7.5 V VCC2 -VE >VUVLO- 9, 27 9 UVLO Threshold VUVLO+ 10.5 11.6 12.5 V VO > 5 V 7, 9, 11 VUVLO- 9.2 10.3 11.1 V VO < 5 V 7, 9, 12 UVLO Hysteresis (VUVLO+ 0.4 1.3 V - VUVLO-) Threshold Input Current IFLH 2.0 6 mA IO = 0 mA, VO > 5 V Low to High Threshold Input Voltage VFHL 0.8 V High to Low Input Forward Voltage VF 1.2 1.6 1.95 V IF = 10 mA Temperature Coefficient DVF/DTA -1.3 mV/°C of Input Forward Voltage Input Reverse Breakdown BVR 5 V IR = 10 µA Voltage Input Capacitance CIN 70 pF f = 1 MHz, VF = 0 V 6

Table 6. Switching Specifications (AC) Unless otherwise noted, all typical values at TA = 25°C, VCC2 - VEE = 30 V, VE - VEE = 0 V; all Minimum/Maximum specifications are at Recommended Operating Conditions. Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Note Propagation Delay Time tPLH 100 180 250 ns Rg = 20 W, Cg = 5 nF, 1, 10, 13, 15 to High Output Level f = 10 kHz, 11, 12, Duty Cycle = 50%, 13, 26 Propagation Delay Time tPHL 100 180 250 ns to Low Output Level IF = 10 mA, VCC2 = 30 V Pulse Width Distortion PWD -100 20 100 ns 14, 17 Propagation Delay Difference (tPHL - tPLH) -150 150 ns 17, 16 Between Any Two Parts or PDD Channels Rise Time tR 50 ns Fall Time tF 50 ns DESAT Sense to 90% VO Delay tDESAT(90%) 0.15 0.3 µs CDESAT = 100pF, RF=2.1kΩ, 14, 27, 19 Rg = 20 W, Cg = 5 nF, 34 VCC2 = 30 V DESAT Sense to 10% VO Delay tDESAT(10%) 1.1 1.5 µs CDESAT = 100pF, RF=2.1kΩ , 15, 16, Rg = 20 W, Cg = 5 nF, 17, 27, VCC2 = 30 V 34 DESAT Sense to Low Level tDESAT(FAULT) 0.25 0.5 µs CDESAT = 100 pF, RF = 2.1 27, 34 18 FAULT Signal Delay kΩ, CF = Open, Rg = 20 Ω, Cg = 5 nF, VCC2 = 30 V 0.8 CDESAT = 100 pF, RF = 2.1 kΩ, CF = 1 nF, Rg = 20 Ω, Cg = 5 nF, VCC2 = 30 V DESAT Sense to DESAT tDESAT(LOW) 0.25 µs CDESAT = 100pF, RF = 2.1 27, 34 19 Low Propagation Delay kW, Rg = 20 W, Cg = 5 nF, VCC2 = 30 V DESAT Input Mute tDESAT(MUTE) 15 26 40 µs CDESAT = 100pF, RF = 2.1 34 20 kW, Rg = 20 W, Cg = 5 nF, VCC1 = 5.5V, VCC2 = 30 V Output High Level Common |CMH| 15 25 kV/µs TA = 25°C, IF = 10 mA 28, 29, 21 Mode Transient Immunity VCM = 1500 V, VCC2 = 30 V, 30, 31 RF = 2.1 kΩ, CF = 15 pF 50 60 TA = 25°C, IF = 10 mA 21, 26 VCM = 1500 V, VCC2 = 30 V, RF = 2.1 kΩ, CF = 1 nF Output Low Level Common |CML| 15 25 kV/µs TA = 25°C, VF = 0 V 28, 29, 22 Mode Transient Immunity VCM = 1500 V, VCC2 = 30 V, 30, 31 RF = 2.1 kΩ, CF = 15 pF 50 60 TA = 25°C, VF = 0 V VCM = 1500 V, VCC2 = 30 V, RF = 2.1 kΩ, CF = 1 nF 7

Table 7. Package Characteristics Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Note Input-Output Momentary VISO 5000 Vrms RH < 50%, t = 1 min., 24, 25 Withstand Voltage TA = 25°C Input-Output Resistance RI-O > 109 W VI-O = 500 V 25 Input-Output Capacitance CI-O 1.3 pF freq=1 MHz Output IC-to-Pins 9 &10 q09-10 30 °C/W TA = 25°C Thermal Resistance Notes: 1. Derate linearly above 70°C free air temperature at a rate of 0.3 mA/°C. 2. In order to achieve the absolute maximum power dissipation specified, pins 4, 9, and 10 require ground plane connections and may require airflow. See the Thermal Model section in the application notes at the end of this data sheet for details on how to estimate junction temperature and power dissipation. In most cases the absolute maximum output IC junction temperature is the limiting factor. The actual power dissipation achievable will depend on the application environment (PCB Layout, air flow, part placement, etc.). See the Recommended PCB Layout section in the application notes for layout considerations. Output IC power dissipation is derated linearly at 10 mW/°C above 90°C. Input IC power dissipation does not require derating. 3. Maximum pulse width = 10 µs. This value is intended to allow for component tolerances for designs with IO peak minimum = 1.0 A. Derate linearly from 2.0 A at +25°C to 1.5 A at +105°C. This compensates for increased IOPEAK due to changes in VOL over temperature. 4. This supply is optional. Required only when negative gate drive is implemented. 5. Maximum pulse width = 50 µs. 6. See the Slow IGBT Gate Discharge During Fault Condition section in the applications notes at the end of this data sheet for further details. 7. 15 V is the recommended minimum operating positive supply voltage (VCC2 - VE) to ensure adequate margin in excess of the maximum VUVLO+ threshold of 12.5 V. For High Level Output Voltage testing, VOH is measured with a dc load current. When driving capacitive loads, VOH will approach VCC as IOH approaches zero units. 8. Maximum pulse width = 1.0 ms. 9. Once VO of the ACPL-330J is allowed to go high (VCC2 - VE > VUVLO+), the DESAT detection feature of the ACPL-330J will be the primary source of IGBT protection. UVLO is needed to ensure DESAT is functional. Once VCC2 is increased from 0V to above VUVLO+, DESAT will remain functional until VCC2 is decreased below VUVLO-. Thus, the DESAT detection and UVLO features of the ACPL-330J work in conjunction to ensure constant IGBT protection. 10. See the DESAT fault detection blanking time section in the applications notes at the end of this data sheet for further details. 11. This is the “increasing” (i.e. turn-on or “positive going” direction) of VCC2 - VE 12. This is the “decreasing” (i.e. turn-off or “negative going” direction) of VCC2 - VE 13. This load condition approximates the gate load of a 1200 V/75A IGBT. 14. Pulse Width Distortion (PWD) is defined as |tPHL - tPLH| for any given unit. 15. As measured from IF to VO. 16. The difference between tPHL and tPLH between any two ACPL-330J parts under the same test conditions. 17. As measured from ANODE, CATHODE of LED to VOUT 18. This is the amount of time from when the DESAT threshold is exceeded, until the FAULT output goes low. 19. This is the amount of time the DESAT threshold must be exceeded before VOUT begins to go low, and the FAULT output to go low. This is supply voltage dependent. 20. Auto Reset: This is the amount of time when VOUT will be asserted low after DESAT threshold is exceeded. See the Description of Operation (Auto Reset) topic in the application information section. 21. Common mode transient immunity in the high state is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to assure that the output will remain in the high state (i.e., VO > 15 V or FAULT > 2 V). 22. Common mode transient immunity in the low state is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to assure that the output will remain in a low state (i.e., VO < 1.0 V or FAULT < 0.8 V). 23. To clamp the output voltage at VCC - 3 VBE, a pull-down resistor between the output and VEE is recommended to sink a static current of 650 µA while the output is high. See the Output Pull-Down Resistor section in the application notes at the end of this data sheet if an output pull-down resistor is not used. 24. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 6000 Vrms for 1 second. This test is performed before the 100% production test for partial discharge (method b) shown in IEC/EN/DIN EN 60747-5-5 Insulation Characteristic Table. 25. This is a two-terminal measurement: pins 1-8 are shorted together and pins 9-16 are shorted together. 26. Split resistors network with a ratio of 1:1 is needed at input LED1. See Figure 31. 8

IF tr tf 90% 50% VOUT 10% tPLH tPHL Figure 1. Timing Curve 0 0.25 V P - ____I = -650µA O OUT GE DR-0.5 GE - V 0.2 A A VOLT -1 VOLT 0.15 UT W P O OUT-1.5 UT L 0.1 GH UTP HI O V) - CC -2 V - OL 0.05 - H VO-2.5 0 ( -40 -20 0 20 40 60 80 105 -40 -20 0 20 40 60 80 105 TA- TEMPERATURE -°C TA- TEMPERATURE -°C Figure 2. VOH vs. temperature Figure 3. VOL vs. temperature 4 30 _ _ _ _ 100°C V E DROP - 29 _-_-_ -_-_- -__-- __- _ - 1 4 02055°°C°CC AGE - V3 --------- -4205°°CC G T A L T O UTPUT VOL 2278 PUT LOW V2 - HIGH O 26 V - OUTOL1 H O V 25 0 0.0 0.2 0.4 0.6 0.8 1.0 0 0.5 1 1.5 IOH - OUTPUT HIGH CURRENT - A IOL - OUTPUT LOW CURRENT - A Figure 4. VOH vs. IOH Figure 5. VOL vs. IOL 9

3.50 2.65 A ICC2H mA ICC2H NT - m 3.25 ICC2L ENT - 2.55 ICC2L E R R 3.00 R R U U C Y C LY PL 2.75 PP 2.45 P U U S UT S 2.50 PUT P T T U 2.35 U O I - OCC2 2.25 I - CC2 2.00 2.25 -40 -20 0 20 40 60 80 105 15 20 25 30 TA- TEMPERATURE -°C VCC2 - SUPPLY VOLTAGE - V Figure 6. ICC2 vs. temperature Figure 7. ICC2 vs. VCC2 -0.20 7.5 V CAPACITORRENT - mA-0.25 HRESHOLD - 7.0 I - BLANKING CHCHARGING CUR-0.30 DESATV - DESAT T6.5 -0.35 6.0 -40 -20 0 20 40 60 80 105 -40 -20 0 20 40 60 80 105 TA- TEMPERATURE -°C TA- TEMPERATURE -°C Figure 8. ICHG vs. temperature Figure 9. DESAT threshold vs. temperature 300 300 tPLH tPLH t t T - PROPAGATION DELAY - nsP122505000 PHL T - PROPAGATION DELAY - nsP122505000 PHL 100 100 -40 -20 0 20 40 60 80 105 15 20 25 30 TA- TEMPERATURE -°C VCC - SUPPLY VOLTAGE - V Figure 10. Propagation delay vs. temperature Figure 11. Propagation delay vs. supply voltage 10

300 300 t PLH t T - PROPAGATION DELAY - nsP122505000 tPHL T - PROPAGATION DELAY - nsP120000 tPPHLHL 100 0 0 10 20 30 40 50 0 10 20 30 40 50 LOAD RESISTANCE - ohm LOAD CAPACITANCE - nF Figure 12. Propagation delay vs. load resistance Figure 13. Propagation delay vs. load capacitance ay - ns 250 y - us 2.0 Vcc2 =15V Del ela Vcc2 =30V Vo o D 1.5 0% 200 % V 9 0 ense to nse to 1 1.0 S e SAT 150 AT S E S DESAT90%T - D 100 DESAT10% - DE 00..05 T -40 -20 0 20 40 60 80 105 -40 -20 0 20 40 60 80 105 TA- TEMPERATURE -°C TA- TEMPERATURE -°C Figure 14. DESAT sense to 90% VOUT delay vs. temperature Figure 15. DESAT sense to 10% VOUT delay vs. temperature 4.0 elay - us Vcc2 =15V ay - ms 0.012 Vcc2 =15V o D 3.0 Vcc2 =30V Del Vcc2 =30V % V Vo 0 % 0.008 o 1 10 DESAT10%T - DESAT Sense t 012...000 DESAT10% - DESAT Sense to 00..000004 10 20 30 40 50 T 0 10 20 30 40 50 LOAD RESISTANCE-ohm LOAD CAPACITANCE-nF Figure 16. DESAT sense to 10% VOUT delay vs. load resistance Figure 17. DESAT sense to 10% VOUT delay vs. load capacitance 11

11 VVSS VVEE 1166 22 VVCCCC11 VVLLEEDD 1155 33 FFAAUULLTT DDEESSAATT 1144 000...111µµµFFF 44 VVSS VVCCCC22 1133 1155VV PPuullsseedd ++ 55 CCAATTHHOODDEE VV 1122 __ EEEE II OOUUTT 66 AANNOODDEE VV 1111 OOUUTT 3300VV 000...111µµµFFF ++ __ 77 AANNOODDEE VV 1100 CCLLAAMMPP 1100mmAA 88 CCAATTHHOODDEE VV 99 EEEE Figure 18. IOH Pulsed test circuit 11 VVSS VVEE 1166 22 VVCCCC11 VVLLEEDD 1155 33 FFAAUULLTT DDEESSAATT 1144 000...111µµµFFF 44 VVSS VVCCCC22 1133 1155VV PPuullsseedd 55 CCAATTHHOODDEE VV 1122 EEEE II OOUUTT 66 AANNOODDEE VV 1111 OOUUTT 3300VV 000...111µµµFFF ++ __ 77 AANNOODDEE VVCCLLAAMMPP 1100 ++__ 88 CCAATTHHOODDEE VV 99 EEEE Figure 19. IOL Pulsed test circuit 1 V V 16 S E 2 VCC1 VLED 15 3 FAULT DESAT 14 0.1µF 4 V V 13 S CC2 5 CATHODE V 12 EE V OUT 6 ANODE V 11 OUT 30V 0.1µF + _ 7 ANODE V 10 CLAMP 650µA 10mA 8 CATHODE V 9 EE Figure 20. VOH Pulsed test circuit 12

11 VVSS VVEE 1166 22 VV VV 1155 CCCC11 LLEEDD 33 FFAAUULLTT DDEESSAATT 1144 000...111µµµFFF 44 VV VV 1133 SS CCCC22 110000mmAA 55 CATHODE VV 1122 EEEE VV OOUUTT 66 AANNOODDEE VV 1111 OOUUTT 3300VV 000...111µµµFFF ++ __ 77 AANNOODDEE VV 1100 CCLLAAMMPP 88 CCAATTHHOODDEE VV 99 EEEE Figure 21. VOL Pulsed test circuit 11 VV VV 1166 SS EE 22 VVCCCC11 VVLLEEDD 1155 33 FFAAUULLTT DDEESSAATT 1144 000...111µµµFFF 44 VV VV 1133 SS CCCC22 II CCCC22 55 CCAATTHHOODDEE VV 1122 EEEE 66 AANNOODDEE VV 1111 OOUUTT 3300VV 000...111µµµFFF ++ __ 77 AANNOODDEE VV 1100 CCLLAAMMPP 111000mmmAAA 88 CCAATTHHOODDEE VV 99 EEEE Figure 22. ICC2H test circuit 11 VVSS VVEE 1166 22 VV VV 1155 CCCC11 LLEEDD 33 FFAAUULLTT DDEESSAATT 1144 000...111µµµFFF 44 VV VV 1133 SS CCCC22 II CCCC22 55 CCAATTHHOODDEE VV 1122 EEEE 66 AANNOODDEE VV 1111 OOUUTT 3300VV 000...111µµµFFF ++ __ 77 AANNOODDEE VV 1100 CCLLAAMMPP 88 CCAATTHHOODDEE VV 99 EEEE Figure 23. ICC2L test circuit 13

11 VV VV 1166 SS EE II CCHHGG 22 VVCCCC11 VVLLEEDD 1155 33 FFAAUULLTT DDEESSAATT 1144 000...111µµµFFF 44 VV VV 1133 SS CCCC22 55 CCAATTHHOODDEE VV 1122 EEEE 66 AANNOODDEE VV 1111 OOUUTT 3300VV 000...111µµµFFF ++ __ 77 AANNOODDEE VV 1100 CCLLAAMMPP 111000mmmAAA 88 CCAATTHHOODDEE VV 99 EEEE Figure 24. ICHG Pulsed test circuit 11 VVSS VVEE 1166 22 VV VV 1155 ++__ 77VV CCCC11 LLEEDD 33 FFAAUULLTT DDEESSAATT 1144 000...111µµµFFF IIDDSSCCHHGG 44 VV VV 1133 SS CCCC22 55 CCAATTHHOODDEE VV 1122 EEEE 66 AANNOODDEE VV 1111 OOUUTT 3300VV 000...111µµµFFF ++ __ 77 AANNOODDEE VV 1100 CCLLAAMMPP 88 CCAATTHHOODDEE VV 99 EEEE Figure 25. IDSCHG test circuit 11 VV VV 1166 SS EE 22 VVCCCC11 VVLLEEDD 1155 33 FFAAUULLTT DDEESSAATT 1144 000...111µµµFFF 44 VV VV 1133 SS CCCC22 55 CCAATTHHOODDEE VV 1122 EEEE VV OOUUTT 66 AANNOODDEE VV 1111 OOUUTT 3300VV 20Ω 000...111µµµFFF ++ __ 77 AANNOODDEE VV 1100 CCLLAAMMPP 555nnnFFF 88 CCAATTHHOODDEE VV 99 1100mmAA,, 1100kkHHzz,, EEEE 5500%% DDuuttyy CCyyccllee Figure 26. tPLH, tPHL, tf, tr, test circuit 14

11 VVSS VVEE 1166 22 VVCCCC11 VVLLEEDD 1155 VVIINN RF=2.1kΩ VV FFAAUULLTT 33 FAULT DDEESSAATT 1144 000...111µµµFFF CF ++ 44 VVSS VVCCCC22 1133 55VV __ 55 CATHODE VV 1122 EEEE VV OOUUTT 66 ANODE VV 1111 OOUUTT 3300VV 20Ω 000...111µµµFFF ++ __ 77 ANODE VV 1100 CCLLAAMMPP 111000mmmAAA 55nnFF 88 CATHODE VV 99 EEEE Figure 27. tDESAT fault test circuit 11 VVSS VVEE 1166 5V 22 VVCCCC11 VVLLEEDD 1155 RF=2.1kΩ SCOPE 33 FAULT DDEESSAATT 1144 CF=15pF or 1nF 3300VV 44 VVSS VVCCCC22 1133 0.1µF 55 CATHODE VV 1122 EEEE 20Ω 66 ANODE VV 1111 OOUUTT 000...111µµµFFF 360Ω 77 ANODE VV 1100 CCLLAAMMPP 555nnnFFF 88 CATHODE VV 99 EEEE VV CCMM Figure 28. CMR Test circuit LED2 off 11 VVSS VVEE 1166 555VVV 22 VVCCCC11 VVLLEEDD 1155 RF=2.1kΩ SCOPE 33 FAULT DDEESSAATT 1144 CF=15pF or 1nF 3300VV 44 VVSS VVCCCC22 1133 000...111µµµFFF 55 CATHODE VV 1122 EEEE 20Ω 66 ANODE VV 1111 OOUUTT 000...111µµµFFF 360Ω 77 ANODE VV 1100 CCLLAAMMPP 555nnnFFF 88 CATHODE VV 99 EEEE VV CCMM Figure 29. CMR Test Circuit LED2 on 15

11 VVSS VVEE 1166 5V 22 VVCCCC11 VVLLEEDD 1155 RF=2.1kΩ CF=15pF 33 FAULT DESAT 1144 or 1nF 30V 44 VVSS VVCCCC22 1133 0.1µµF 55 CATHODE VV 1122 SCOPE EEEE 20Ω 66 ANODE VV 1111 OOUUTT 0.1µµµF 360Ω 77 ANODE VV 1100 CCLLAAMMPP 5nF 88 CATHODE VV 99 EEEE VVV CCCMMM Figure 30. CMR Test circuit LED1 off 11 VVSS VVEE 1166 5V 22 VVCCCC11 VVLLEEDD 1155 RF=2.1kΩ 33 FAULT DESAT 1144 CF=15pF or 1nF 30V 44 VVSS VVCCCC22 1133 5 CATHODE 0.1µF 55 CATHODE VV 1122 SCOPE EEEE 20Ω 6 ANODE 66 ANODE VVOOUUTT 1111 0.1µF 5V 180Ω 7 ANODE 360Ω 77 ANODE VV 1100 180Ω CCLLAAMMPP 5nF 8 CATHODE 88 CATHODE VV 99 EEEE Split resistors network with a ratio of 1:1 VV CCMM Figure 31. CMR Test Circuit LED1 on 16

Application Information 13 VCC2 UVLO Product Overview Description 6, 7 D ANODE R Tdheev icAeC tPhLa-t3 3in0cJ o rpiso raa tehsig ahllly t hinet engercaetsesda rpy ocwoemr pcoonnetnrotsl CATHODE 5, 8 LED1 VEI 1114 DVOESUATT for a complete, isolated IGBT / MOSFET gate drive circuit R DESAT with fault protection and feedback into one SO-16 9, 12 package. Active Miller clamp function eliminates the SHIELD VEE need of negative gate drive in most application and VCLAMP allows the use of simple bootstrap supply for high side 2 10 dIGrBivTesr . wAitnh oppotwicearll yr aitsionlgast eodf pupow toer 1o0u0t pAu at nsdta 1g2e0 0d rViv. eAs FAVUCLCT1 3 LED2 16 VVECLAMP high speed internal optical link minimizes the propaga- tion delays between the microcontroller and the IGBT 1, 4 15 while allowing the two systems to operate at very large VS SHIELD VLED common mode voltage differences that are common in industrial motor drives and other power switching Figure 32. Block Diagram of ACPL-330J applications. An output IC provides local protection for the IGBT to prevent damage during over current, Recommended Application Circuit and a second optical link provides a fully isolated fault status feedback signal for the microcontroller. A built The ACPL-330J has an LED input gate control, and an in “watchdog” circuit, UVLO monitors the power stage open collector fault output suitable for wired ‘OR’ ap- supply voltage to prevent IGBT caused by insufficient plications. The recommended application circuit shown gate drive voltages. This integrated IGBT gate driver is in Figure 33 illustrates a typical gate drive implementa- designed to increase the performance and reliability of tion using the ACPL-330J. The following describes about a motor drive without the cost, size, and complexity of a driving IGBT. However, it is also applicable to MOSFET. discrete design. Depending upon the MOSFET or IGBT gate threshold requirements, designers may want to adjust the VCC Two light emitting diodes and two integrated circuits housed in the same SO-16 package provide the input supply voltage (Recommended VCC = 17.5V for IGBT and 12.5V for MOSFET). control circuitry, the output power stage, and two optical channels. The output Detector IC is designed manufac- The two supply bypass capacitors (0.1 µF) provide the tured on a high voltage BiCMOS/Power DMOS process. large transient currents necessary during a switching The forward optical signal path, as indicated by LED1, transition. Because of the transient nature of the transmits the gate control signal. The return optical signal charging currents, a low current (5mA) power supply path, as indicated by LED2, transmits the fault status suffices. The desaturation diode DDESAT 600V/1200V feedback signal. fast recovery type, trr below 75ns (e.g. ERA34-10) and Under normal operation, the LED1 directly controls the capacitor CBLANK are necessary external components for IGBT gate through the isolated output detector IC, and the fault detection circuitry. The gate resistor RG serves to limit gate charge current and controls the IGBT collector LED2 remains off. When an IGBT fault is detected, the voltage rise and fall times. The open collector fault output detector IC immediately begins a “soft” shutdown sequence, reducing the IGBT current to zero in a con- output has a passive pull-up resistor RF (2.1 kW) and a trolled manner to avoid potential IGBT damage from 1000 pF filtering capacitor, CF. A 47 kW pull down resistor inductive over voltages. Simultaneously, this fault status RPULL-DOWN on VOUT provides a predictable high level is transmitted back to the input via LED2, where the fault output voltage (VOH). In this application, the IGBT gate driver will shut down when a fault is detected and fault latch disables the gate control input and the active low reset by next cycle of IGBT turn on. Application notes are fault output alerts the microcontroller. mentioned at the end of this datasheet. During power-up, the Under Voltage Lockout (UVLO) feature prevents the application of insufficient gate voltage to the IGBT, by forcing the ACPL-330J’s output low. Once the output is in the high state, the DESAT (VCE) detection feature of the ACPL-330J provides IGBT pro- tection. Thus, UVLO and DESAT work in conjunction to provide constant IGBT protection. 17

1 VS VE 16 0.1µF 2 VCC1 VLED 15 CBLANK + 0.1µF RF 100 Ω DDESAT _ 3 FAULT DESAT 14 C F 4 VS VCC2 13 5 CATHODE VEE 12 ++__ + HVDC RG + 6 ANODE VOUT 11 VCE R Q1 - 3-PHASE + 77 ANODE VCLAMP 10 RPULL--DOWN AC _ + 8 CATHODE VEE 9 Q2 V-CE -HVDC Figure 33. Recommended application circuit (Single Supply) with desaturation detection and active Miller Clamp Description of Operation Normal Operation During normal operation, VOUT of the ACPL-330J is con- Figure 34. Fault Timing diagramactivated is an internal trolled by input LED current IF (pins 5, 6, 7 and 8), with feedback channel which brings the FAULT output low for the IGBT collector-to-emitter voltage being monitored the purpose of notifying the micro-controller of the fault through DESAT. The FAULT output is high. See Figure 34. condition. Fault Condition Fault Reset The DESAT pin monitors the IGBT Vce voltage. When the Once fault is detected, the output will be soft-shut down voltage on the DESAT pin exceeds 6.5 V while the IGBT to low. All input LED signals will be ignored during is on, VOUT is slowly brought low in order to “softly” the fault period to allow the driver to completely soft turn-off the IGBT and prevent large di/dt induced shut-down the IGBT. For ACPL-330J, the driver will auto- voltages. Also matically reset the FAULT pin after a fixed mute time of 25ms (typical). See Figure 34. t I DESAT(LOW) F 6.5V Automatic Reset V after mute time DESAT t t BLANK DESAT(10%) 90% V OUT 10% t DESAT(90%) FAULT 50% 50% t DESAT(FAULT) t DESAT(MUTE) Figure 34. Fault Timing diagram 18

Output Control Slow IGBT Gate Discharge during Fault Condition The outputs (VOUT and FAULT) of the ACPL-330J are con- When a desaturation fault is detected, a weak pull-down trolled by the combination of IF, UVLO and a detected device in the ACPL-330J output drive stage will turn on IGBT Desat condition. Once UVLO is not active (VCC2 - to ‘softly’ turn off the IGBT. This device slowly discharges VE > VUVLO), VOUT is allowed to go high, and the DESAT the IGBT gate to prevent fast changes in drain current (pin 14) detection feature of the ACPL-330J will be the that could cause damaging voltage spikes due to lead primary source of IGBT protection. Once VCC2 is increased and wire inductance. During the slow turn off, the large from 0V to above VUVLO+, DESAT will remain functional output pull-down device remains off until the output until VCC2 is decreased below VUVLO-. Thus, the DESAT voltage falls below VEE + 2 Volts, at which time the large detection and UVLO features of the ACPL-330J work in pull down device clamps the IGBT gate to VEE. conjunction to ensure constant IGBT protection. DESAT Fault Detection Blanking Time Desaturation Detection and High Current Protection The DESAT fault detection circuitry must remain disabled The ACPL-330J satisfies these criteria by combining a for a short time period following the turn-on of the IGBT high speed, high output current driver, high voltage to allow the collector voltage to fall below the DESAT optical isolation between the input and output, local threshold. This time period, called the DESAT blanking IGBT desaturation detection and shut down, and an time is controlled by the internal DESAT charge current, optically isolated fault status feedback signal into a single the DESAT voltage threshold, and the external DESAT 16-pin surface mount package. capacitor. The fault detection method, which is adopted in the The nominal blanking time is calculated in terms of ACPL-330J is to monitor the saturation (collector) external capacitance (CBLANK), FAULT threshold voltage voltage of the IGBT and to trigger a local fault shutdown (VDESAT), and DESAT charge current (ICHG) as tBLANK = sequence if the collector voltage exceeds a predeter- CBLANK x VDESAT / ICHG. The nominal blanking time with mined threshold. A small gate discharge device slowly the recommended 100pF capacitor is 100pF * 6.5 V / 240 reduces the high short circuit IGBT current to prevent µA = 2.7 µsec. damaging voltage spikes. Before the dissipated energy The capacitance value can be scaled slightly to adjust the can reach destructive levels, the IGBT is shut off. During blanking time, though a value smaller than 100 pF is not the off state of the IGBT, the fault detect circuitry is simply recommended. This nominal blanking time represents disabled to prevent false ‘fault’ signals. the longest time it will take for the ACPL-330J to respond The alternative protection scheme of measuring IGBT to a DESAT fault condition. If the IGBT is turned on while current to prevent desaturation is effective if the short the collector and emitter are shorted to the supply rails circuit capability of the power device is known, but (switching into a short), the soft shut-down sequence this method will fail if the gate drive voltage decreases will begin after approximately 3 µsec. If the IGBT collector enough to only partially turn on the IGBT. By directly and emitter are shorted to the supply rails after the IGBT measuring the collector voltage, the ACPL-330J limits is already on, the response time will be much quicker due the power dissipation in the IGBT even with insufficient to the parasitic parallel capacitance of the DESAT diode. gate drive voltage. Another more subtle advantage of the The recommended 100pF capacitor should provide desaturation detection method is that power dissipation adequate blanking as well as fault response times for in the IGBT is monitored, while the current sense method most applications. relies on a preset current threshold to predict the safe limit of operation. Therefore, an overly conservative over current threshold is not needed to protect the IGBT. IF UVLO(VCC2-VE) DESAT Function Pin 3 (FAULT) Output VOUT ON Active Not Active High Low ON Not Active Active (with DESAT fault) Low (FAULT) Low ON Not Active Active (no DESAT fault) High (or no fault) High OFF Active Not Active High Low OFF Not Active Not Active High Low 19

Under Voltage Lockout 11 VVSS VVEE 1166 The ACPL-330J Under Voltage Lockout (UVLO) feature is designed to prevent the application of insufficient gate 22 VVCCCC11 VVLLEEDD 1155 voltage to the IGBT by forcing the ACPL-330J output low during power-up. IGBTs typically require gate 33 FFAAUULLTT DDEESSAATT 1144 VVCCCC voltages of 15 V to achieve their rated VCE(ON) voltage. At gate voltages below 13 V typically, the VCE(ON) voltage 44 VVSS VVCCCC22 1133 increases dramatically, especially at higher currents. 55 CCAATTHHOODDEE VV 1122 EEEE At very low gate voltages (below 10 V), the IGBT may RR GG operate in the linear region and quickly overheat. 66 AANNOODDEE VV 1111 OOUUTT The UVLO function causes the output to be clamped whenever insufficient operating supply (VCC2) is applied. 77 AANNOODDEE VVCCLLAAMMPP 1100 RRPPUULLLL--DDOOWWNN Once VCC2 exceeds VUVLO+ (the positive-going UVLO 88 CCAATTHHOODDEE VV 99 threshold), the UVLO clamp is released to allow the EEEE device output to turn on in response to input signals. As VCC2 is increased from 0 V (at some level below VUVLO+), first the DESAT protection circuitry becomes active. As Figure 35. Output pull-down resistor. VCC2 is further increased (above VUVLO+), the UVLO clamp DESAT Pin Protection Resistor is released. Before the time the UVLO clamp is released, the DESAT protection is already active. Therefore, the The freewheeling of flyback diodes connected across UVLO and DESAT Fault detection feature work together the IGBTs can have large instantaneous forward voltage to provide seamless protection regardless of supply transients which greatly exceed the nominal forward voltage (VCC2). voltage of the diode. This may result in a large negative voltage spike on the DESAT pin which will draw substan- Active Miller Clamp tial current out of the driver if protection is not used. To limit this current to levels that will not damage the driver A Miller clamp allows the control of the Miller current IC, a 100 ohm resistor should be inserted in series with during a high dV/dt situation and can eliminate the use the DESAT diode. The added resistance will not alter the of a negative supply voltage in most of the applications. DESAT threshold or the DESAT blanking time. During turn-off, the gate voltage is monitored and the clamp output is activated when gate voltage goes below 2V (relative to VEE). The clamp voltage is VOL+2.5V typ 1 VS VE 16 for a Miller current up to 1100mA. The clamp is disabled when the LED input is triggered again. 2 VCC1 VLED 15 100pF 100 Ω DDESAT Other Recommended Components 3 FAULT DESAT 14 VV CCCC The application circuit in Figure 33 includes an output 4 VS VCC2 13 pull-down resistor, a DESAT pin protection resistor, a 5 CATHODE V 12 FAULT pin capacitor, and a FAULT pin pullup resistor and EE R Active Miller Clamp connection. G 6 ANODE V 11 OUT Output Pull-Down Resistor 7 ANODE V 10 CLAMP During the output high transition, the output voltage 8 CATHODE V 9 rapidly rises to within 3 diode drops of VCC2. If the output EE current then drops to zero due to a capacitive load, the output voltage will slowly rise from roughly VCC2-3(VBE) Figure 36. DESAT pin protection. to VCC2 within a period of several microseconds. To limit the output voltage to VCC2-3(VBE), a pull-down resistor, RPULL-DOWN between the output and VEE is recommend- ed to sink a static current of several 650 µA while the output is high. Pull-down resistor values are dependent on the amount of positive supply and can be adjusted according to the formula, Rpull-down = [VCC2-3 * (VBE)] / 650 µA. 20

Capacitor on FAULT Pin for High CMR Pull-up Resistor on FAULT Pin Rapid common mode transients can affect the fault pin The FAULT pin is an open collector output and therefore voltage while the fault output is in the high state. A 1000 requires a pull-up resistor to provide a high-level signal. pF capacitor should be connected between the fault pin Also the FAULT output can be wire ‘OR’ed together with and ground to achieve adequate CMOS noise margins at other types of protection (e.g. over-temperature, over- the specified CMR value of 50 kV/µs. voltage, over-current ) to alert the microcontroller. Other Possible Application Circuit (Output Stage) 1 VS VE 16 0(cid:141)1(cid:141)F 0(cid:141)1(cid:141)F 2 VCC1 VLED 15 3 FAULT DESAT 14 4 VS VCC2 13 0(cid:141)1(cid:141)F O(cid:141)(cid:141)(cid:141)(cid:141)(cid:141)(cid:141)(cid:141) R 2 5 CATHODE VEE 12 +_ + HVDC O(cid:141)(cid:141)(cid:141)(cid:141)(cid:141)(cid:141)(cid:141) R 1 RRGG + 6 ANODE VOUT 11 VCE Q1 - 3-PHASE 7 ANODE VCLAMP 10 + AC R _ PULL-DOWN + 8 CATHODE VEE 9 (cid:141) Q2 V-CE -HVDC Figure 37. IGBT drive with negative gate drive, external booster and desaturation detection (VCLAMP should be connected to VEE when it is not used) VCLAMP is used as secondary gate discharge path. * indicates component required for negative gate drive topology 1 VS VE 16 0(cid:141)1(cid:141)F 0(cid:141)1(cid:141)F 2 VCC1 VLED 15 3 FAULT DESAT 14 4 VS VCC2 13 0(cid:141)1(cid:141)F O(cid:141)(cid:141)(cid:141)(cid:141)(cid:141)(cid:141)(cid:141) R 2 5 CATHODE VEE 12 +_ + HVDC O(cid:141)(cid:141)(cid:141)(cid:141)(cid:141)(cid:141)(cid:141) R 1 RRGG + 6 ANODE VOUT 11 VCE Q1 - 3-PHASE 7 ANODE VCLAMP 10 + AC R _ PULL-DOWN + (cid:141) 8 CATHODE VEE 99 Q2 V-CE -HVDC RR 33 Figure 38. Large IGBT drive with negative gate drive, external booster. VCLAMP control secondary discharge path for higher power application. 21

Thermal Model The ACPL-330J is designed to dissipate the majority of where Pi = power into input IC and Po = power into the heat through pins 1, 4, 5 & 8 for the input IC and pins output IC. Since θ5A and θ9,12A are dependent on PCB 9 & 12 for the output IC. (There are two VEE pins on the layout and airflow, their exact number may not be output side, pins 9 and 12, for this purpose.) Heat flow available. Therefore, a more accurate method of calcu- through other pins or through the package directly into lating the junction temperature is with the following ambient are considered negligible and not modeled equations: here. Tji = Pi θi5 + TP5 In order to achieve the power dissipation specified in Tjo = Po θo9,12 + TP9,12 the absolute maximum specification, it is imperative that pins 5, 9, and 12 have ground planes connected to These equations, however, require that the pin 5 and pins them. As long as the maximum power specification is 9, 12 temperatures be measured with a thermal couple not exceeded, the only other limitation to the amount on the pin at the ACPL-330J package edge. of power one can dissipate is the absolute maximum If the calculated junction temperatures for the thermal junction temperature specification of 125°C. The junction model in Figure 39 is higher than 125°C, the pin tem- temperatures can be calculated with the following perature for pins 9 and 12 should be measured (at the equations: package edge) under worst case operating environment Tji = Pi (θi5 + θ5A) + TA for a more accurate estimate of the junction tempera- tures. Tjo = Po (θo9,12 + θ9,12A) + TA Tji Tjo Tji = junction temperature of input side IC Tjo = junction temperature of output side IC θI1 = 60°C/W θl9, 12 = 30°C/W TP5 = pin 5 temperature at package edge TP9,12 = pin 9 and 12 temperature at package edge θI5 = input side IC to pin 5 thermal resistance θo9,12 = output side IC to pin 9 and 12 thermal resistance TP1 TP9, 12 θ5A = pin 5 to ambient thermal resistance θ9,12A = pin 9 and 12 to ambient thermal resistance θ1A = 50°C/W* θ9, 12A = 50°C/W* *The θ5A and θ9,12A values shown here are for PCB layouts with reasonable air flow. This value may increase or decrease by a factor of 2 depending on PCB layout and/or airflow. TA Figure 39. ACPL-330J Thermal Model Related Application Notes AN5314 – Active Miller Clamp AN5315 – “Soft” Turn-off Feature AN1043 – Common-Mode Noise : Sources and Solutions AV02-0310EN - Plastic Optocouplers Product ESD and Moisture Sensitivity For product information and a complete list of distributors, please go to our web site: www.avagotech.com Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright © 2005-2015 Avago Technologies. All rights reserved. AV02-1280EN - November 20, 2015

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: B roadcom Limited: ACPL-330J-500E ACPL-330J-000E