93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C 2K Microwire Compatible Serial EEPROM Device Selection Table Part Number VCC Range ORG Pin Word Size Temp Ranges Packages 93AA56A 1.8-5.5 No 8-bit I P, SN, ST, MS, OT 93AA56B 1.8-5-5 No 16-bit I P, SN, ST, MS, OT 93LC56A 2.5-5.5 No 8-bit I, E P, SN, ST, MS, OT 93LC56B 2.5-5.5 No 16-bit I, E P, SN, ST, MS, OT 93C56A 4.5-5.5 No 8-bit I, E P, SN, ST, MS, OT 93C56B 4.5-5.5 No 16-bit I, E P, SN, ST, MS, OT 93AA56C 1.8-5.5 Yes 8 or 16-bit I P, SN, ST, MS 93LC56C 2.5-5.5 Yes 8 or 16-bit I, E P, SN, ST, MS 93C56C 4.5-5.5 Yes 8 or 16-bit I, E P, SN, ST, MS Features Description • Low-power CMOS technology The Microchip Technology Inc. 93XX56A/B/C devices (cid:127) ORG pin to select word size for ‘56C version are 2K bit low voltage serial Electrically Erasable PROMs (EEPROM). Word-selectable devices such as (cid:127) 256 x 8-bit organization ‘A’ ver. devices (no ORG) the 93AA56C, 93LC56C or 93C56C are dependent (cid:127) 128 x 16-bit organization ‘B’ ver. devices (no upon external logic levels driving the ORG pin to set ORG) word size. For dedicated 8-bit communication, the (cid:127) Self-timed ERASE/WRITE cycles (including 93AA56A, 93LC56A or 93C56A devices are available, auto-erase) while the 93AA56B, 93LC56B and 93C56B devices (cid:127) Automatic ERAL before WRAL provide dedicated 16-bit communication. Advanced (cid:127) Power on/off data protection circuitry CMOS technology makes these devices ideal for low (cid:127) Industry standard 3-wire serial I/O power, nonvolatile memory applications. The entire 93XX Series is available in standard packages includ- (cid:127) Device Status signal (READY/BUSY ) ing 8-lead PDIP and SOIC, and advanced packaging (cid:127) Sequential READ function including 8-lead MSOP, 6-lead SOT-23, and 8-lead (cid:127) 1,000,000 E/W cycles TSSOP. Pb-free (Pure Matte Sn) finish is also (cid:127) Data retention > 200 years available. (cid:127) Temperature ranges supported: Package Types (not to scale) - Industrial (I) -40°C to +85°C - Automotive (E) -40°C to +125°C ROTATED SOIC PDIP/SOIC (ex: 93LC56BX) (P, SN) Pin Function Table NC 1 8 ORG* CS 1 8 VCC Name Function VCC 2 7 VSS CLK 2 7 NC CS 3 6 DO DI 3 6 ORG* CS Chip Select CLK 4 5 DI DO 4 5 VSS CLK Serial Data Clock TSSOP/MSOP SOT-23 DI Serial Data Input (ST, MS) (OT) DO Serial Data Output CCLSK 12 87 VNCCC DO 1 6 VCC VSS Ground DDOI 34 65 OVSRSG* VSS 2 5 CS NC No internal connection DI 3 4 CLK * ORG pin is NC on A/B devices ORG Memory Configuration VCC Power Supply  2003 Microchip Technology Inc. DS21794B-page 1

93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings(†) VCC.............................................................................................................................................................................7.0V All inputs and outputs w.r.t. VSS.........................................................................................................-0.6V to VCC +1.0V Storage temperature...............................................................................................................................-65°C to +150°C Ambient temperature with power applied................................................................................................-40°C to +125°C ESD protection on all pins......................................................................................................................................................≥ 4kV †NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. TABLE 1-1: DC CHARACTERISTICS VCC = range by device (see Table on Page 1) All parameters apply over the specified Industrial (I): TA = -40°C to +85°C ranges unless otherwise noted. Automotive (E): TA = -40°C to +125°C Param. Symbol Parameter Min Typ Max Units Conditions No. D1 VIH1 High-level input voltage 2.0 — VCC +1 V VCC ≥ 2.7V VIH2 0.7 VCC — VCC +1 V VCC < 2.7V D2 VIL1 Low-level input voltage -0.3 — 0.8 V VCC ≥ 2.7V VIL2 -0.3 — 0.2 VCC V VCC < 2.7V D3 Vol1 Low-level output voltage — — 0.4 V IOL = 2.1 mA, VCC = 4.5V Vol2 — — 0.2 V IOL = 100 µA, VCC = 2.5V D4 VOH1 High-level output voltage 2.4 — — V IOH = -400 µA, VCC = 4.5V VOH2 VCC - 0.2 — — V IOH = -100 µA, VCC = 2.5V D5 ILI Input leakage current — — ±1 µA VIN = VSS to VCC D6 ILO Output leakage current — — ±1 µA VOUT = VSS to VCC D7 CIN, Pin capacitance (all inputs/ — — 7 pF VIN/VOUT = 0V (Note 1) COUT outputs) TA = 25°C, FCLK = 1 MHz D8 ICC write Write current — — 2 mA FCLK = 3 MHz, Vcc = 5.5V — 500 — µA FCLK = 2 MHz, Vcc = 2.5V D9 ICC read Read current — — 1 mA FCLK = 3 MHz, VCC = 5.5V — — 500 µA FCLK = 2 MHz, VCC = 3.0V — 100 — µA FCLK = 2 MHz, VCC = 2.5V D10 ICCS Standby current — — 1 µA I – Temp — — 5 µA E – Temp CLK = Cs = 0V ORG = DI = VSS or VCC (Note 2) (Note 3) D11 VPOR VCC voltage detect 93AA56A/B/C, 93LC56A/B/C — 1.5V — V (Note 1) 93C56A/B/C — 3.8V — V Note 1: This parameter is periodically sampled and not 100% tested. 2: ORG pin not available on ‘A’ or ‘B’ versions. 3: READY/BUSY status must be cleared from DO, see Section3.4 "Data Out (DO)". DS21794B-page 2  2003 Microchip Technology Inc.

93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C TABLE 1-2: AC CHARACTERISTICS VCC = range by device (see Table on Page 1) All parameters apply over the specified Industrial (I): TA = -40°C to +85°C ranges unless otherwise noted. Automotive (E): TA = -40°C to +125°C Param. Symbol Parameter Min Max Units Conditions No. A1 FCLK Clock frequency — 3 MHz 4.5V ≤ VCC < 5.5V, 93XX56C only 2 MHz 2.5V ≤ VCC < 5.5V 1 MHz 1.8V ≤ VCC < 2.5V A2 TCKH Clock high time 200 — ns 4.5V ≤ VCC < 5.5V, 93XX56C only 250 ns 2.5V ≤ VCC < 5.5V 450 ns 1.8V ≤ VCC < 2.5V A3 TCKL Clock low time 100 — ns 4.5V ≤ VCC < 5.5V, 93XX56C only 200 ns 2.5V ≤ VCC < 5.5V 450 ns 1.8V ≤ VCC < 2.5V A4 TCSS Chip Select setup time 50 — ns 4.5V ≤ VCC < 5.5V 100 ns 2.5V ≤ VCC < 4.5V 250 ns 1.8V ≤ VCC < 2.5V A5 TCSH Chip Select hold time 0 — ns 1.8V ≤ VCC < 5.5V A6 TCSL Chip Select low time 250 — ns 1.8V ≤ VCC < 5.5V A7 TDIS Data input setup time 50 — ns 4.5V ≤ VCC < 5.5V, 93XX56C only 100 ns 2.5V ≤ VCC < 5.5V 250 ns 1.8V ≤ VCC < 2.5V A8 TDIH Data input hold time 50 — ns 4.5V ≤ VCC < 5.5V, 93XX56C only 100 ns 2.5V ≤ VCC < 5.5V 250 ns 1.8V ≤ VCC < 2.5V A9 TPD Data output delay time — 200 ns 4.5V ≤ VCC < 5.5V, CL = 100 pF 250 ns 2.5V ≤ VCC < 4.5V, CL = 100 pF 400 ns 1.8V ≤ VCC < 2.5V, CL = 100 pF A10 TCZ Data output disable time — 100 ns 4.5V ≤ VCC < 5.5V, (Note 1) 200 ns 1.8V ≤ VCC < 4.5V, (Note 1) A11 TSV Status valid time — 200 ns 4.5V ≤ VCC < 5.5V, CL = 100 pF 300 ns 2.5V ≤ VCC < 4.5V, CL = 100 pF 500 ns 1.8V ≤ VCC < 2.5V, CL = 100 pF A12 TWC Program cycle time — 6 ms Erase/Write mode (AA and LC versions) A13 TWC — 2 ms Erase/Write mode (93C versions) A14 TEC — 6 ms ERAL mode, 4.5V ≤ VCC ≤ 5.5V A15 TWL — 15 ms WRAL mode, 4.5V ≤ VCC ≤ 5.5V A16 — Endurance 1M — cycles 25°C, VCC = 5.0V, (Note 2) Note 1: This parameter is periodically sampled and not 100% tested. 2: This application is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total Endurance™ Model which may be obtained from www.microchip.com.  2003 Microchip Technology Inc. DS21794B-page 3

93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C FIGURE 1-1: SYNCHRONOUS DATA TIMING VIH CS VIL TCSS TCKH TCKL TCSH VIH CLK VIL TDIS TDIH VIH DI VIL TPD TPD TCZ VOH DO (READ) VOL TCZ TSV DO VOH (PROGRAM) STATUS VALID VOL Note: TSV is relative to CS. TABLE 1-3: INSTRUCTION SET FOR X 16 ORGANIZATION (93XX56B OR 93XX56C WITH ORG = 1) Instruction SB Opcode Address Data In Data Out Req. CLK Cycles ERASE 1 11 X A6 A5 A4 A3 A2 A1 A0 — (RDY/BSY) 11 ERAL 1 00 1 0 X X X X X X — (RDY/BSY) 11 EWDS 1 00 0 0 X X X X X X — HIGH-Z 11 EWEN 1 00 1 1 X X X X X X — HIGH-Z 11 READ 1 10 X A6 A5 A4 A3 A2 A1 A0 — D15 – D0 27 WRITE 1 01 X A6 A5 A4 A3 A2 A1 A0 D15 – D0 (RDY/BSY) 27 WRAL 1 00 0 1 X X X X X X D15 – D0 (RDY/BSY) 27 TABLE 1-4: INSTRUCTION SET FOR X 8 ORGANIZATION (93XX56A OR 93XX56C WITH ORG = 0) Req. CLK Instruction SB Opcode Address Data In Data Out Cycles ERASE 1 11 X A7 A6 A5 A4 A3 A2 A1 A0 — (RDY/BSY) 12 ERAL 1 00 1 0 X X X X X X X — (RDY/BSY) 12 EWDS 1 00 0 0 X X X X X X X — HIGH-Z 12 EWEN 1 00 1 1 X X X X X X X — HIGH-Z 12 READ 1 10 X A7 A6 A5 A4 A3 A2 A1 A0 — D7 – D0 20 WRITE 1 01 X A7 A6 A5 A4 A3 A2 A1 A0 D7 – D0 (RDY/BSY) 20 WRAL 1 00 0 1 X X X X X X X D7 – D0 (RDY/BSY) 20 DS21794B-page 4  2003 Microchip Technology Inc.

93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C 2.0 FUNCTIONAL DESCRIPTION 2.2 Data In/Data Out (DI/DO) When the ORG* pin is connected to VCC, the (x16) It is possible to connect the Data In and Data Out pins organization is selected. When it is connected to together. However, with this configuration it is possible ground, the (x8) organization is selected. Instructions, for a “bus conflict” to occur during the “dummy zero” addresses and write data are clocked into the DI pin on that precedes the Read operation, if A0 is a logic high the rising edge of the clock (CLK). The DO pin is level. Under such a condition the voltage level seen at normally held in a HIGH-Z state except when reading Data Out is undefined and will depend upon the relative data from the device, or when checking the READY/ impedances of Data Out and the signal source driving BUSY status during a programming operation. The A0. The higher the current sourcing capability of A0, READY/BUSY status can be verified during an Erase/ the higher the voltage at the Data Out pin. In order to Write operation by polling the DO pin; DO low indicates limit this current, a resistor should be connected that programming is still in progress, while DO high between DI and DO. indicates the device is ready. DO will enter the HIGH-Z state on the falling edge of CS. 2.3 Data Protection 2.1 START Condition All modes of operation are inhibited when VCC is below a typical voltage of 1.5V for '93AA' and '93LC' devices The START bit is detected by the device if CS and DI or 3.8V for '93C' devices. are both high with respect to the positive edge of CLK The EWEN and EWDS commands give additional for the first time. protection against accidentally programming during Before a START condition is detected, CS, CLK, and DI normal operation. may change in any combination (except to that of a Note: For added protection, an EWDS command START condition), without resulting in any device should be performed after every write operation (READ, WRITE, ERASE, EWEN, EWDS, operation. ERAL, or WRAL). As soon as CS is high, the device is After power-up, the device is automatically in the no longer in Standby mode. EWDS mode. Therefore, an EWEN instruction must be An instruction following a START condition will only be performed before the initial ERASE or WRITE instruction executed if the required opcode, address and data bits can be executed. for any particular instruction are clocked in. Block Diagram VCC VSS Memory Address Array Decoder Address Counter DO Output Data Register Buffer DI Mode ORG* Decode CS Logic Clock CLK Register *ORG input is not available on A/B devices  2003 Microchip Technology Inc. DS21794B-page 5

93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C 2.4 ERASE The DO pin indicates the READY/BUSY status of the device if CS is brought high after a minimum of 250 ns The ERASE instruction forces all data bits of the speci- low (TCSL). DO at logical ‘0’ indicates that programming fied address to the logical ‘1’ state. CS is brought low is still in progress. DO at logical ‘1’ indicates that the following the loading of the last address bit. This falling register at the specified address has been erased and edge of the CS pin initiates the self-timed program- the device is ready for another instruction. ming cycle, except on ‘93C’ devices where the rising Note: Issuing a START bit and then taking CS low edge of CLK before the last address bit initiates the will clear the READY/BUSY status from write cycle. DO. FIGURE 2-1: ERASE TIMING FOR 93AA AND 93LC DEVICES TCSL CS CHECK STATUS CLK DI 1 1 1 AN AN-1 AN-2 (cid:127)(cid:127)(cid:127) A0 TSV TCZ HIGH-Z DO BUSY READY HIGH-Z TWC FIGURE 2-2: ERASE TIMING FOR 93C DEVICES TCSL CS CHECK STATUS CLK DI 1 1 1 AN AN-1 AN-2 (cid:127)(cid:127)(cid:127) A0 TSV TCZ HIGH-Z DO BUSY READY HIGH-Z TWC DS21794B-page 6  2003 Microchip Technology Inc.

93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C 2.5 ERASE ALL (ERAL) The DO pin indicates the READY/BUSY status of the device, if CS is brought high after a minimum of 250 ns The Erase All (ERAL) instruction will erase the entire low (TCSL). memory array to the logical ‘1’ state. The ERAL cycle is Note: Issuing a START bit and then taking CS low identical to the ERASE cycle, except for the different will clear the READY/BUSY status from opcode. The ERAL cycle is completely self-timed and DO. commences at the falling edge of the CS, except on ‘93C’ devices where the rising edge of CLK before the VCC must be ≥ 4.5V for proper operation of ERAL. last data bit initiates the write cycle. Clocking of the CLK pin is not necessary after the device has entered the ERAL cycle. FIGURE 2-3: ERAL TIMING FOR 93AA AND 93LC DEVICES TCSL CS CHECK STATUS CLK DI 1 0 0 1 0 X (cid:127)(cid:127)(cid:127) X TSV TCZ HIGH-Z DO BUSY READY HIGH-Z VCC must be ≥ 4.5V for proper operation of ERAL. TEC FIGURE 2-4: ERAL TIMING FOR 93C DEVICES TCSL CS CHECK STATUS CLK DI 1 0 0 1 0 X (cid:127)(cid:127)(cid:127) X TSV TCZ HIGH-Z DO BUSY READY HIGH-Z TEC  2003 Microchip Technology Inc. DS21794B-page 7

93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C 2.6 ERASE/WRITE DISABLE And ENABLE (EWDS/EWEN) The 93XX56A/B/C powers up in the ERASE/WRITE To protect against accidental data disturbance, the Disable (EWDS) state. All Programming modes must be EWDS instruction can be used to disable all ERASE/ preceded by an ERASE/WRITE Enable (EWEN) instruc- WRITE functions and should follow all programming tion. Once the EWEN instruction is executed, program- operations. Execution of a READ instruction is indepen- ming remains enabled until an EWDS instruction is dent of both the EWEN and EWDS instructions. executed or Vcc is removed from the device. FIGURE 2-5: EWDS TIMING TCSL CS CLK DI 1 0 0 0 0 X (cid:127)(cid:127)(cid:127) X FIGURE 2-6: EWEN TIMING TCSL CS CLK 1 0 0 1 1 X (cid:127)(cid:127)(cid:127) X DI 2.7 READ devices) output string. The output data bits will toggle on the rising edge of the CLK and are stable after the spec- The READ instruction outputs the serial data of the ified time delay (TPD). Sequential read is possible when addressed memory location on the DO pin. A dummy CS is held high. The memory data will automatically cycle zero bit precedes the 8-bit (If ORG pin is low or A-Version to the next register and output sequentially. devices) or 16-bit (If ORG pin is high or B-version FIGURE 2-7: READ TIMING CS CLK DI 1 1 0 An (cid:127)(cid:127)(cid:127) A0 HIGH-Z DO 0 Dx (cid:127)(cid:127)(cid:127) D0 Dx (cid:127)(cid:127)(cid:127) D0 Dx (cid:127)(cid:127)(cid:127) D0 DS21794B-page 8  2003 Microchip Technology Inc.

93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C 2.8 WRITE The DO pin indicates the READY/BUSY status of the device, if CS is brought high after a minimum of 250 ns The WRITE instruction is followed by 8 bits (If ORG is low (TCSL). DO at logical ‘0’ indicates that programming low or A-version devices) or 16 bits (If ORG pin is high is still in progress. DO at logical ‘1’ indicates that the or B-version devices) of data which are written into the register at the specified address has been written with specified address. For 93AA56A/B/C and 93LC56A/B/C the data specified and the device is ready for another devices, after the last data bit is clocked into DI, the instruction. falling edge of CS initiates the self-timed auto-erase and Note: Issuing a START bit and then taking CS low programming cycle. For 93C56A/B/C devices, the self- will clear the READY/BUSY status from timed auto-erase and programming cycle is initiated by DO. the rising edge of CLK on the last data bit. FIGURE 2-8: WRITE TIMING FOR 93AA AND 93LC DEVICES TCSL CS CLK DI 1 0 1 An (cid:127)(cid:127)(cid:127) A0 Dx (cid:127)(cid:127)(cid:127) D0 TSV TCZ HIGH-Z DO BUSY READY HIGH-Z Twc FIGURE 2-9: WRITE TIMING FOR 93C DEVICES TCSL CS CLK DI 1 0 1 An (cid:127)(cid:127)(cid:127) A0 Dx (cid:127)(cid:127)(cid:127) D0 TSV TCZ HIGH-Z DO BUSY READY HIGH-Z Twc  2003 Microchip Technology Inc. DS21794B-page 9

93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C 2.9 WRITE ALL (WRAL) automatic ERAL cycle for the device. Therefore, the WRAL instruction does not require an ERAL instruction The Write All (WRAL) instruction will write the entire but the chip must be in the EWEN status. memory array with the data specified in the command. The DO pin indicates the READY/BUSY status of the For 93AA56A/B/C and 93LC56A/B/C devices, after the device if CS is brought high after a minimum of 250 ns last data bit is clocked into DI, the falling edge of CS initiates the self-timed auto-erase and programming low (TCSL). cycle. For 93C56A/B/C devices, the self-timed auto- Note: Issuing a START bit and then taking CS low erase and programming cycle is initiated by the rising will clear the READY/BUSY status from edge of CLK on the last data bit. Clocking of the CLK DO. pin is not necessary after the device has entered the VCC must be ≥ 4.5V for proper operation of WRAL. WRAL cycle. The WRAL command does include an FIGURE 2-10: WRAL TIMING FOR 93AA AND 93LC DEVICES TCSL CS CLK DI 1 0 0 0 1 X (cid:127)(cid:127)(cid:127) X Dx (cid:127)(cid:127)(cid:127) D0 TSV TCZ HIGH-Z DO BUSY READY HIGH-Z TWL VCC must be ≥ 4.5V for proper operation of WRAL. FIGURE 2-11: WRAL TIMING FOR 93C DEVICES TCSL CS CLK DI 1 0 0 0 1 X (cid:127)(cid:127)(cid:127) X Dx (cid:127)(cid:127)(cid:127) D0 TSV TCZ HIGH-Z DO BUSY READY HIGH-Z TWL DS21794B-page 10  2003 Microchip Technology Inc.

93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C 3.0 PIN DESCRIPTIONS TABLE 3-1: PIN DESCRIPTIONS SOIC/PDIP/ Name SOT-23 Rotated SOIC Function MSOP/TSSOP CS 1 5 3 Chip Select CLK 2 4 4 Serial Clock DI 3 3 5 Data In DO 4 1 6 Data Out VSS 5 2 7 Ground ORG/NC 6 N/A 8 Organization / 93XX56C No Internal Connection / 93XX56A/B NC 7 N/A 1 No Internal Connection VCC 8 6 2 Power Supply 3.1 Chip Select (CS) data bits before an instruction is executed. CLK and DI then become don't care inputs waiting for a new START A high level selects the device; a low level deselects condition to be detected. the device and forces it into Standby mode. However, a programming cycle which is already in progress will be 3.3 Data In (DI) completed, regardless of the Chip Select (CS) input signal. If CS is brought low during a program cycle, the Data In (DI) is used to clock in a START bit, opcode, device will go into Standby mode as soon as the address and data synchronously with the CLK input. programming cycle is completed. CS must be low for 250 ns minimum (TCSL) between 3.4 Data Out (DO) consecutive instructions. If CS is low, the internal Data Out (DO) is used in the Read mode to output data control logic is held in a Reset status. synchronously with the CLK input (TPD after the posi- tive edge of CLK). 3.2 Serial Clock (CLK) This pin also provides READY/BUSY status informa- The Serial Clock is used to synchronize the communi- tion during ERASE and WRITE cycles. READY/BUSY cation between a master device and the 93XX series status information is available on the DO pin if CS is device. Opcodes, address and data bits are clocked in brought high after being low for minimum Chip Select on the positive edge of CLK. Data bits are also clocked low time (TCSL) and an ERASE or WRITE operation out on the positive edge of CLK. has been initiated. CLK can be stopped anywhere in the transmission The Status signal is not available on DO, if CS is held sequence (at high or low level) and can be continued low during the entire ERASE or WRITE cycle. In this anytime with respect to clock high time (TCKH) and case, DO is in the HIGH-Z mode. If status is checked clock low time (TCKL). This gives the controlling master after the ERASE/WRITE cycle, the data line will be high freedom in preparing opcode, address and data. to indicate the device is ready. CLK is a “Don't Care” if CS is low (device deselected). Note: Issuing a START bit and then taking CS low If CS is high, but the START condition has not been will clear the READY/BUSY status from detected (DI = 0), any number of clock cycles can be DO. received by the device without changing its status (i.e., waiting for a START condition). 3.5 Organization (ORG) CLK cycles are not required during the self-timed When the ORG pin is connected to VCC or Logic HI, the WRITE (i.e., auto ERASE/WRITE) cycle. (x16) memory organization is selected. When the ORG After detection of a START condition the specified pin is tied to VSS or Logic LO, the (x8) memory number of clock cycles (respectively low to high transi- organization is selected. For proper operation, ORG tions of CLK) must be provided. These clock cycles are must be tied to a valid logic level. required to clock in all required opcode, address and 93XX56A devices are always x8 organization and 93XX56B devices are always x16 organization.  2003 Microchip Technology Inc. DS21794B-page 11

93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C 4.0 PACKAGING INFORMATION 4.1 Package Marking Information 8-Lead MSOP (150 mil) Example: MSOP 1st Line Marking Codes Pb-free Device std mark mark XXXXXXT 3L56BI 93AA56A 3A56AT GA56AT YWWNNN 2281L7 93AA56B 3A56BT GA56BT 93AA56C 3A56CT GA56CT 93LC56A 3L56AT GL56AT 93LC56B 3L56BT GL56BT 93LC56C 3L56CT GL56CT 93C56A 3C56AT GC56AT 6-Lead SOT-23 Example: 93C56B 3C56BT GC56BT 93C56C 3C56CT GC56CT T = blank for commercial, “I” for Industrial, “E” for Extended. XXNN 2EL7 SOT23 Marking Codes Device I-temp E-temp 8-Lead PDIP Example: 93AA56A 2BNN – 93AA56B 2LNN – XXXXXXXX 93LC56B 93LC56A 2ENN 2FNN XXXXXNNN I/P 1L7 93LC56B 2PNN 2RNN YYWW 0228 93C56A 2HNN 2JNN 93C56B 2TNN 2UNN Pb-free topside mark is same; Pb-free noted only on carton label. 8-Lead SOIC Example: XXXXXXXX 93LC56B XXXXYYWW I/SN 0228 TSSOP 1st Line Marking Codes NNN 1L7 Pb-free Device std mark mark 93AA56A A56A GABA 93AA56B A56B GABB 93AA56C A56C GABC 93LC56A L56A GLBA 8-Lead TSSOP Example: 93LC56B L56B GLBB 93LC56C L56C GLBC XXXX L56B 93C56A C56A GCBA TYWW I228 93C56B C56B GCBB NNN 1L7 93C56C C56C GCBC Temperature grade is marked on line 2. Legend: XX...X Part number T Temperature Blank Commercial I Industrial E Extended YY Year code (last 2 digits of calendar year) except TSSOP and MSOP which use only the last 1 digit WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code Note: Custom marking available. DS21794B-page 12  2003 Microchip Technology Inc.

93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C 8-Lead Plastic Micro Small Outline Package (MS) (MSOP) E E1 p D 2 B n 1 α A A2 c φ A1 (F) L β Units INCHES MILLIMETERS* Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 8 8 Pitch p .026 BSC 0.65 BSC Overall Height A - - .043 - - 1.10 Molded Package Thickness A2 .030 .033 .037 0.75 0.85 0.95 Standoff A1 .000 - .006 0.00 - 0.15 Overall Width E .193 TYP. 4.90 BSC Molded Package Width E1 .118 BSC 3.00 BSC Overall Length D .118 BSC 3.00 BSC Foot Length L .016 .024 .031 0.40 0.60 0.80 Footprint (Reference) F .037 REF 0.95 REF Foot Angle φ 0° - 8° 0° - 8° Lead Thickness c .003 .006 .009 0.08 - 0.23 Lead Width B .009 .012 .016 0.22 - 0.40 Mold Draft Angle Top α 5° - 15° 5° - 15° Mold Draft Angle Bottom β 5° - 15° 5° - 15° *Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MO-187 Drawing No. C04-111  2003 Microchip Technology Inc. DS21794B-page 13

93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C 6-Lead Plastic Small Outline Transistor (OT) (SOT-23) E E1 B p1 D n 1 α c A A2 φ A1 L β Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 6 6 Pitch p .038 0.95 Outside lead pitch (basic) p1 .075 1.90 Overall Height A .035 .046 .057 0.90 1.18 1.45 Molded Package Thickness A2 .035 .043 .051 0.90 1.10 1.30 Standoff A1 .000 .003 .006 0.00 0.08 0.15 Overall Width E .102 .110 .118 2.60 2.80 3.00 Molded Package Width E1 .059 .064 .069 1.50 1.63 1.75 Overall Length D .110 .116 .122 2.80 2.95 3.10 Foot Length L .014 .018 .022 0.35 0.45 0.55 Foot Angle φ 0 5 10 0 5 10 Lead Thickness c .004 .006 .008 0.09 0.15 0.20 Lead Width B .014 .017 .020 0.35 0.43 0.50 Mold Draft Angle Top α 0 5 10 0 5 10 Mold Draft Angle Bottom β 0 5 10 0 5 10 *Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side. JEITA (formerly EIAJ) equivalent: SC-74A Drawing No. C04-120 DS21794B-page 14  2003 Microchip Technology Inc.

93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C 8-Lead Plastic Dual In-line (P) – 300 mil (PDIP) E1 D 2 n 1 α E A A2 L c A1 β B1 p eB B Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 8 8 Pitch p .100 2.54 Top to Seating Plane A .140 .155 .170 3.56 3.94 4.32 Molded Package Thickness A2 .115 .130 .145 2.92 3.30 3.68 Base to Seating Plane A1 .015 0.38 Shoulder to Shoulder Width E .300 .313 .325 7.62 7.94 8.26 Molded Package Width E1 .240 .250 .260 6.10 6.35 6.60 Overall Length D .360 .373 .385 9.14 9.46 9.78 Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43 Lead Thickness c .008 .012 .015 0.20 0.29 0.38 Upper Lead Width B1 .045 .058 .070 1.14 1.46 1.78 Lower Lead Width B .014 .018 .022 0.36 0.46 0.56 Overall Row Spacing § eB .310 .370 .430 7.87 9.40 10.92 Mold Draft Angle Top α 5 10 15 5 10 15 Mold Draft Angle Bottom β 5 10 15 5 10 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-018  2003 Microchip Technology Inc. DS21794B-page 15

93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C 8-Lead Plastic Small Outline (SN) –Narrow, 150 mil (SOIC) E E1 p D 2 B n 1 h α 45° c A A2 φ β L A1 Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 8 8 Pitch p .050 1.27 Overall Height A .053 .061 .069 1.35 1.55 1.75 Molded Package Thickness A2 .052 .056 .061 1.32 1.42 1.55 Standoff § A1 .004 .007 .010 0.10 0.18 0.25 Overall Width E .228 .237 .244 5.79 6.02 6.20 Molded Package Width E1 .146 .154 .157 3.71 3.91 3.99 Overall Length D .189 .193 .197 4.80 4.90 5.00 Chamfer Distance h .010 .015 .020 0.25 0.38 0.51 Foot Length L .019 .025 .030 0.48 0.62 0.76 Foot Angle φ 0 4 8 0 4 8 Lead Thickness c .008 .009 .010 0.20 0.23 0.25 Lead Width B .013 .017 .020 0.33 0.42 0.51 Mold Draft Angle Top α 0 12 15 0 12 15 Mold Draft Angle Bottom β 0 12 15 0 12 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-057 DS21794B-page 16  2003 Microchip Technology Inc.

93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C 8-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP) E E1 p D 2 1 n B α A c φ A1 A2 β L Units INCHES MILLIMETERS* Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 8 8 Pitch p .026 0.65 Overall Height A .043 1.10 Molded Package Thickness A2 .033 .035 .037 0.85 0.90 0.95 Standoff § A1 .002 .004 .006 0.05 0.10 0.15 Overall Width E .246 .251 .256 6.25 6.38 6.50 Molded Package Width E1 .169 .173 .177 4.30 4.40 4.50 Molded Package Length D .114 .118 .122 2.90 3.00 3.10 Foot Length L .020 .024 .028 0.50 0.60 0.70 Foot Angle φ 0 4 8 0 4 8 Lead Thickness c .004 .006 .008 0.09 0.15 0.20 Lead Width B .007 .010 .012 0.19 0.25 0.30 Mold Draft Angle Top α 0 5 10 0 5 10 Mold Draft Angle Bottom β 0 5 10 0 5 10 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005” (0.127mm) per side. JEDEC Equivalent: MO-153 Drawing No. C04-086  2003 Microchip Technology Inc. DS21794B-page 17

93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C APPENDIX A: REVISION HISTORY Revision B Corrections to Section 1.0, Electrical Characteristics. Section 4.1, 6-Lead SOT-23 package to OT. DS21794B-page 18  2003 Microchip Technology Inc.

93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C ON-LINE SUPPORT SYSTEMS INFORMATION AND UPGRADE HOT LINE Microchip provides on-line support on the Microchip World Wide Web site. The Systems Information and Upgrade Line provides The web site is used by Microchip as a means to make system users a listing of the latest versions of all of files and information easily available to customers. To Microchip's development systems software products. view the site, the user must have access to the Internet Plus, this line provides information on how customers and a web browser, such as Netscape® or Microsoft® can receive the most current upgrade kits. The Hot Line Internet Explorer. Files are also available for FTP Numbers are: download from our FTP site. 1-800-755-2345 for U.S. and most of Canada, and 1-480-792-7302 for the rest of the world. Connecting to the Microchip Internet Web Site 042003 The Microchip web site is available at the following URL: www.microchip.com The file transfer site is available by using an FTP service to connect to: ftp://ftp.microchip.com The web site and file transfer site provide a variety of services. Users may download files for the latest Development Tools, Data Sheets, Application Notes, User's Guides, Articles and Sample Programs. A vari- ety of Microchip specific business information is also available, including listings of Microchip sales offices, distributors and factory representatives. Other data available for consideration is: (cid:127) Latest Microchip Press Releases (cid:127) Technical Support Section with Frequently Asked Questions (cid:127) Design Tips (cid:127) Device Errata (cid:127) Job Postings (cid:127) Microchip Consultant Program Member Listing (cid:127) Links to other useful web sites related to Microchip Products (cid:127) Conferences for products, Development Systems, technical information and more (cid:127) Listing of seminars and events  2003 Microchip Technology Inc. DS21794B-page 19

93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod- uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: Technical Publications Manager Total Pages Sent ________ RE: Reader Response From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y N Device: 93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C Literature Number: DS21794B Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS21794B-page 20  2003 Microchip Technology Inc.

93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X X X /XX X Examples: a) 93AA56C-I/MS: 2K, 256x8 or 128x16 Serial Device Pinout Tape & Reel Temperature Package Lead Finish EEPROM, MSOP package, 1.8V Range b) 93AA56B-I/MS: 2K, 128x16 Serial EEPROM, MSOP package, 1.8V Device 93AA56A: 2K 1.8V Microwire Serial EEPROM c) 93AA56AT-I/OT: 2K, 256x8 Serial EEPROM, 93AA56B: 2K 1.8V Microwire Serial EEPROM SOT-23 package, tape and reel, 1.8V 93AA56C: 2K 1.8V Microwire Serial EEPROM w/ORG d) 93AA56CT-I/MS: 2K, 256x8 or 128x16 Serial EEPROM, MSOP package, tape and reel, 1.8V 93LC56A: 2K 2.5V Microwire Serial EEPROM 93LC56B: 2K 2.5V Microwire Serial EEPROM 93LC56C: 2K 2.5V Microwire Serial EEPROM w/ORG a) 93LC56A-I/MS: 2K, 256x8 Serial EEPROM, MSOP package, 2.5V 93C56A: 2K 5.0V Microwire Serial EEPROM b) 93LC56BT-I/OT: 2K, 128x16 Serial EEPROM, 93C56B: 2K 5.0V Microwire Serial EEPROM SOT-23 package, tape and reel, 2.5V 93C56C: 2K 5.0V Microwire Serial EEPROM w/ORG c) 93LC56B-I/MS: 2K, 128x16 Serial EEPROM, MSOP package, 2.5V Pinout: Blank = Standard pinout d) 93LC56BXT-I/SNG: 2K, 128x16 Serial X = Rotated pinout EEPROM, SOIC package, rotated pinout, Industrial temperature, Pb-free finish, 2.5V Tape & Reel: Blank = Standard packaging T = Tape & Reel a) 93C56B-I/MS: 2K, 128x16 Serial EEPROM, MSOP package, 5.0V b) 93C56C-I/MS: 2K, 256x8 or 128x16 Serial Temperature Range I = -40°C to +85°C EEPROM, MSOP package, 5.0V E = -40°C to +125°C c) 93C56AT-I/OT: 2K, 256x8 Serial EEPROM, SOT-23 package, tape and reel, 5.0V Package MS = Plastic MSOP (Micro Small outline, 8-lead) OT = SOT-23, 6-lead (Tape & Reel only) P = Plastic DIP (300 mil body), 8-lead SN = Plastic SOIC (150 mil body), 8-lead ST = TSSOP, 8-lead Lead Finish: Blank = Standard 63% / 37% SnPb G = Pure Matte Sn Sales and Support Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. Your local Microchip sales office 2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277 3. The Microchip Worldwide Site (www.microchip.com) Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products.  2003 Microchip Technology Inc. DS21794B-page 21

93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C NOTES: DS21794B-page 22  2003 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices: (cid:127) Microchip products meet the specification contained in their particular Microchip Data Sheet. (cid:127) Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. (cid:127) There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. (cid:127) Microchip is willing to work with the customer who is concerned about the integrity of their code. (cid:127) Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is intended through suggestion only The Microchip name and logo, the Microchip logo, Accuron, and may be superseded by updates. It is your responsibility to dsPIC, KEELOQ, MPLAB, PIC, PICmicro, PICSTART, ensure that your application meets with your specifications. PRO MATE and PowerSmart are registered trademarks of No representation or warranty is given and no liability is Microchip Technology Incorporated in the U.S.A. and other assumed by Microchip Technology Incorporated with respect countries. to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such AmpLab, FilterLab, microID, MXDEV, MXLAB, PICMASTER, use or otherwise. Use of Microchip’s products as critical com- SEEVAL and The Embedded Control Solutions Company are ponents in life support systems is not authorized except with registered trademarks of Microchip Technology Incorporated express written approval by Microchip. No licenses are con- in the U.S.A. veyed, implicitly or otherwise, under any intellectual property Application Maestro, dsPICDEM, dsPICDEM.net, ECAN, rights. ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, microPort, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPIC, Select Mode, SmartSensor, SmartShunt, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. Serialized Quick Turn Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2003, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999 and Mountain View, California in March 2002. The Company’s quality system processes and procedures are QS-9000 compliant for its PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, non-volatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001 certified.  2003 Microchip Technology Inc. DS21794B-page 23

WORLDWIDE SALES AND SERVICE AMERICAS ASIA/PACIFIC Korea Corporate Office Australia 168-1, Youngbo Bldg. 3 Floor Samsung-Dong, Kangnam-Ku 2355 West Chandler Blvd. Suite 22, 41 Rawson Street Seoul, Korea 135-882 Chandler, AZ 85224-6199 Epping 2121, NSW Tel: 82-2-554-7200 Fax: 82-2-558-5932 or Tel: 480-792-7200 Australia 82-2-558-5934 Fax: 480-792-7277 Tel: 61-2-9868-6733 Singapore Technical Support: 480-792-7627 Fax: 61-2-9868-6755 Web Address: http://www.microchip.com China - Beijing 200 Middle Road #07-02 Prime Centre Atlanta Unit 915 Singapore, 188980 3780 Mansell Road, Suite 130 Bei Hai Wan Tai Bldg. Tel: 65-6334-8870 Fax: 65-6334-8850 Alpharetta, GA 30022 No. 6 Chaoyangmen Beidajie Taiwan Tel: 770-640-0034 Beijing, 100027, No. China Fax: 770-640-0307 Tel: 86-10-85282100 Kaohsiung Branch Fax: 86-10-85282104 30F - 1 No. 8 Boston China - Chengdu Min Chuan 2nd Road 2 Lan Drive, Suite 120 Kaohsiung 806, Taiwan Rm. 2401-2402, 24th Floor, Westford, MA 01886 Tel: 886-7-536-4818 Tel: 978-692-3848 Ming Xing Financial Tower Fax: 886-7-536-4803 No. 88 TIDU Street Fax: 978-692-3821 Taiwan Chengdu 610016, China Chicago Tel: 86-28-86766200 Taiwan Branch 333 Pierce Road, Suite 180 Fax: 86-28-86766599 11F-3, No. 207 Itasca, IL 60143 China - Fuzhou Tung Hua North Road Tel: 630-285-0071 Taipei, 105, Taiwan Fax: 630-285-0075 Unit 28F, World Trade Plaza Tel: 886-2-2717-7175 Fax: 886-2-2545-0139 No. 71 Wusi Road Dallas Fuzhou 350001, China EUROPE 4570 Westgrove Drive, Suite 160 Tel: 86-591-7503506 Austria Addison, TX 75001 Fax: 86-591-7503521 Tel: 972-818-7423 China - Hong Kong SAR Durisolstrasse 2 Fax: 972-818-2924 Unit 901-6, Tower 2, Metroplaza AA-u4s6tr0ia0 Wels Detroit 223 Hing Fong Road Tel: 43-7242-2244-399 Tri-Atria Office Building Kwai Fong, N.T., Hong Kong Fax: 43-7242-2244-393 32255 Northwestern Highway, Suite 190 Tel: 852-2401-1200 Denmark Farmington Hills, MI 48334 Fax: 852-2401-3431 Regus Business Centre Tel: 248-538-2250 China - Shanghai Lautrup hoj 1-3 Fax: 248-538-2260 Room 701, Bldg. B Ballerup DK-2750 Denmark Kokomo Far East International Plaza Tel: 45-4420-9895 Fax: 45-4420-9910 2767 S. Albright Road No. 317 Xian Xia Road France Kokomo, IN 46902 Shanghai, 200051 Parc d’Activite du Moulin de Massy Tel: 765-864-8360 Tel: 86-21-6275-5700 43 Rue du Saule Trapu Fax: 765-864-8387 Fax: 86-21-6275-5060 Batiment A - ler Etage Los Angeles China - Shenzhen 91300 Massy, France Rm. 1812, 18/F, Building A, United Plaza Tel: 33-1-69-53-63-20 18201 Von Karman, Suite 1090 No. 5022 Binhe Road, Futian District Fax: 33-1-69-30-90-79 Irvine, CA 92612 Shenzhen 518033, China Germany Tel: 949-263-1888 Tel: 86-755-82901380 Steinheilstrasse 10 Fax: 949-263-1338 Fax: 86-755-8295-1393 D-85737 Ismaning, Germany Phoenix China - Shunde Tel: 49-89-627-144-0 2355 West Chandler Blvd. Room 401, Hongjian Building Fax: 49-89-627-144-44 Chandler, AZ 85224-6199 No. 2 Fengxiangnan Road, Ronggui Town Italy Tel: 480-792-7966 Shunde City, Guangdong 528303, China Via Quasimodo, 12 Fax: 480-792-4338 Tel: 86-765-8395507 Fax: 86-765-8395571 20025 Legnano (MI) San Jose China - Qingdao Milan, Italy 2107 North First Street, Suite 590 Rm. B505A, Fullhope Plaza, Tel: 39-0331-742611 San Jose, CA 95131 No. 12 Hong Kong Central Rd. Fax: 39-0331-466781 Tel: 408-436-7950 Qingdao 266071, China Netherlands Fax: 408-436-7955 Tel: 86-532-5027355 Fax: 86-532-5027205 P. A. De Biesbosch 14 Toronto India NL-5152 SC Drunen, Netherlands 6285 Northam Drive, Suite 108 Divyasree Chambers Tel: 31-416-690399 Mississauga, Ontario L4V 1X5, Canada 1 Floor, Wing A (A3/A4) Fax: 31-416-690340 Tel: 905-673-0699 No. 11, O’Shaugnessey Road United Kingdom Fax: 905-673-6509 Bangalore, 560 025, India 505 Eskdale Road Tel: 91-80-2290061 Fax: 91-80-2290062 Winnersh Triangle Japan Wokingham Benex S-1 6F Berkshire, England RG41 5TU 3-18-20, Shinyokohama Tel: 44-118-921-5869 Kohoku-Ku, Yokohama-shi Fax: 44-118-921-5820 Kanagawa, 222-0033, Japan Tel: 81-45-471- 6166 Fax: 81-45-471-6122 07/28/03 DS21794B-page 24  2003 Microchip Technology Inc.

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: M icrochip: 93C56A-I/MS 93C56A-I/SN 93C56A-I/ST 93LC56AX/SN 93C56A-E/P 93LC56BT/SN 93LC56BT/ST 93C56A-I/P 93AA56A-I/P 93LC56A-I/P 93LC56C-I/P 93C56C-E/MS 93C56C-E/SN 93C56C-E/ST 93C66-E/SN 93C56-E/SN 93C56C-E/P 93LC56AT-E/SN 93LC56BT-E/ST 93LC56AT-E/ST 93LC56BT-E/OT 93LC56CT-E/ST 93LC56AT- E/OT 93LC56CT-E/SN 93LC56BT-E/SN 93AA56BT-I/ST 93LC56CT-E/MS 93LC56AT-E/MS 93AA56CT-I/ST 93LC56BT-E/MS 93AA56AT-I/SN 93AA56BT-I/SN 93AA56CT-I/SN 93AA56BT-I/OT 93AA56AT-I/OT 93AA56AT- I/ST 93AA56CT-I/MS 93AA56AT-I/MS 93AA56BT-I/MS 93C56AT-I/ST 93C56CT-I/ST 93C56C-I/MS 93C56BT-I/SN 93C56C-I/SN 93C56BT-I/ST 93C56AT-I/SN 93C56CT-I/SN 93C56C-I/ST 93C56BT-I/OT 93C56AT-I/OT 93LC56C-I/MS 93LC56C-I/SN 93LC56C-I/ST 93LC56/P 93C56-E/P 93AA56B-I/SN 93LC56C-E/ST 93AA56B-I/ST 93LC56C-E/SN 93AA56B-I/MS 93LC56AT/SN 93LC56AT/ST 93LC56B-I/ST 93LC56A-I/MS 93LC56A-I/SN 93LC56A-I/ST 93C56AXT-E/SN 93C56BXT-E/SN 93C56CXT-E/SN 93LC56XT/SN 93LC56/SN 93LC56A/P 93LC56B/P 93AA56C-I/P 93LC56AXT/SN 93LC56X/SN 93LC56T/SN 93C56BT-I/MS 93C56AT-I/MS 93C56CT- I/MS 93C56C-I/P 93LC56AX-I/SN 93LC56CX-I/SN 93LC56BX/SN 93LC56BX-I/SN 93AA56C-I/MS 93AA56C-I/SN 93AA56C-I/ST 93LC56BT-I/OT 93LC56BT-I/MS 93LC56BXT-I/SN 93LC56AT-I/ST 93LC56BT-I/ST 93LC56CT-I/ST 93LC56AT-I/MS 93LC56CT-I/MS 93LC56AT-I/OT 93LC56AT-I/SN 93LC56BT-I/SN 93LC56CT-I/SN