93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C 1K Microwire Compatible Serial EEPROM Device Selection Table Part Number VCC Range ORG Pin Word Size Temp Ranges Packages 93AA46A 1.8-5.5 No 8-bit I P, SN, ST, MS, OT, MC, MN 93AA46B 1.8-5-5 No 16-bit I P, SN, ST, MS, OT, MC, MN 93LC46A 2.5-5.5 No 8-bit I, E P, SN, ST, MS, OT, MC, MN 93LC46B 2.5-5.5 No 16-bit I, E P, SN, ST, MS, OT, MC, MN 93C46A 4.5-5.5 No 8-bit I, E P, SN, ST, MS, OT, MC, MN 93C46B 4.5-5.5 No 16-bit I, E P, SN, ST, MS, OT, MC, MN 93AA46C 1.8-5.5 Yes 8- or 16-bit I P, SN, ST, MS, MC, MN 93LC46C 2.5-5.5 Yes 8- or 16-bit I, E P, SN, ST, MS, MC, MN 93C46C 4.5-5.5 Yes 8- or 16-bit I, E P, SN, ST, MS, MC, MN Features: Pin Function Table • Low-Power CMOS Technology Name Function • ORG Pin to Select Word Size for ‘46C’ Version CS Chip Select • 128 x 8-bit Organization ‘A’ Devices (no ORG) CLK Serial Data Clock • 64 x 16-bit Organization ‘B’ Devices (no ORG) DI Serial Data Input • Self-Timed Erase/Write Cycles (including DO Serial Data Output Auto-Erase) VSS Ground • Automatic Erase All (ERAL) Before Write All (WRAL) NC No internal connection • Power-On/Off Data Protection Circuitry ORG Memory Configuration • Industry Standard 3-Wire Serial I/O VCC Power Supply • Device Status Signal (Ready/Busy) Description: • Sequential Read Function • 1,000,000 Erase/Write Cycles The Microchip Technology Inc. 93XX46A/B/C devices • Data Retention > 200 Years are 1Kbit low-voltage serial Electrically Erasable • RoHS Compliant PROMs (EEPROM). Word-selectable devices such as • Temperature Ranges Supported: the 93AA46C, 93LC46C or 93C46C are dependent upon external logic levels driving the ORG pin to set - Industrial (I) -40°C to +85°C word size. For dedicated 8-bit communication, the - Automotive (E) -40°C to +125°C 93AA46A, 93LC46A or 93C46A devices are available, while the 93AA46B, 93LC46B and 93C46B devices provide dedicated 16-bit communication. Advanced CMOS technology makes these devices ideal for low- power, nonvolatile memory applications. The entire 93XX Series is available in standard packages includ- ing 8-lead PDIP and SOIC, and advanced packaging including 8-lead MSOP, 6-lead SOT-23, 8-lead 2x3DFN/TDFN and 8-lead TSSOP. All packages are Pb-free (Matte Tin) finish.  2002-2013 Microchip Technology Inc. DS20001749K-page 1

93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C Package Types (not to scale) ROTATED SOIC PDIP/SOIC (ex: 93LC46BX) (P, SN) NC 1 8 ORG* CS 1 8 VCC VCC 2 7 VSS CLK 2 7 NC CS 3 6 DO DI 3 6 ORG* CLK 4 5 DI DO 4 5 VSS TSSOP/MSOP SOT-23 (ST, MS) (OT) CCLKS 12 87 VNCCC DO 1 6 VCC DI 3 6 ORG* VSS 2 5 CS DO 4 5 VSS DI 3 4 CLK DFN/TDFN (MC, MN) CS 1 8 VCC CLK 2 7 NC DI 3 6 ORG* DO 4 5 VSS *ORG pin is NC on A/B devices DS20001749K-page 2  2002-2013 Microchip Technology Inc.

93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings(†) VCC.............................................................................................................................................................................7.0V All inputs and outputs w.r.t. VSS..........................................................................................................-0.6V to VCC +1.0V Storage temperature...............................................................................................................................-65°C to +150°C Ambient temperature with power applied................................................................................................-40°C to +125°C ESD protection on all pins 4kV † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. TABLE 1-1: DC CHARACTERISTICS All parameters apply over the specified Industrial (I): TA = -40°C to +85°C, VCC = +1.8V TO +5.5V ranges unless otherwise noted. Automotive (E): TA = -40°C to +125°C, VCC = +2.5V TO +5.5V Param. Symbol Parameter Min. Typ Max. Units Conditions No. D1 VIH1 High-level input voltage 2.0 — VCC +1 V VCC 2.7V VIH2 0.7 VCC — VCC +1 V VCC 2.7V D2 VIL1 Low-level input voltage -0.3 — 0.8 V VCC 2.7V VIL2 -0.3 — 0.2 VCC V VCC 2.7V D3 VOL1 Low-level output voltage — — 0.4 V IOL = 2.1mA, VCC = 4.5V VOL2 — — 0.2 V IOL = 100 A, VCC = 2.5V D4 VOH1 High-level output voltage 2.4 — — V IOH = -400 A, VCC = 4.5V VOH2 VCC - 0.2 — — V IOH = -100 A, VCC = 2.5V D5 ILI Input leakage current — — ±1 A VIN = VSS or VCC D6 ILO Output leakage current — — ±1 A VOUT = VSS or VCC D7 CIN, Pin capacitance — — 7 pF VIN/VOUT = 0V (Note 1) COUT (all inputs/outputs) TA = 25°C, FCLK = 1 MHz D8 ICC Write current — — 2 mA FCLK = 3MHz, VCC = 5.5V write — 500 — A FCLK = 2MHz, VCC = 2.5V D9 ICC read Read current — — 1 mA FCLK = 3MHz, VCC = 5.5V — — 500 A FCLK = 2MHz, VCC = 3.0V — 100 — A FCLK = 2MHz, VCC = 2.5V D10 ICCS Standby current — — 1 A I-Temp — — 5 A E-Temp CLK = CS = 0V ORG = DI = VSS or VCC (Note 2) (Note 3) D11 VPOR VCC voltage detect (Note 1) — 1.5 — V 93AA46A/B/C, 93LC46A/B/C — 3.8 — V 93C46A/B/C Note1: This parameter is periodically sampled and not 100% tested. 2: ORG pin not available on ‘A’ or ‘B’ versions. 3: Ready/Busy status must be cleared from DO; see Section3.4 “Data Out (DO)”.  2002-2013 Microchip Technology Inc. DS20001749K-page 3

93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C TABLE 1-2: AC CHARACTERISTICS All parameters apply over the specified Industrial (I): TA = -40°C to +85°C, VCC = +1.8V TO +5.5V ranges unless otherwise noted. Automotive (E): TA = -40°C to +125°C, VCC = +2.5V TO +5.5V Param. Symbol Parameter Min. Max. Units Conditions No. A1 FCLK Clock frequency — 3 MHz 4.5VVCC  5.5V, 93XX46C only 2 MHz 2.5V VCC  5.5V 1 MHz 1.8V VCC 2.5V A2 TCKH Clock high time 200 — ns 4.5VVCC  5.5V, 93XX46C only 250 ns 2.5V VCC  5.5V 450 ns 1.8V VCC 2.5V A3 TCKL Clock low time 100 — ns 4.5VVCC  5.5V, 93XX46C only 200 ns 2.5V VCC  5.5V 450 ns 1.8V VCC 2.5V A4 TCSS Chip Select setup time 50 — ns 4.5VVCC  5.5V 100 ns 2.5V VCC  4.5V 250 ns 1.8V VCC 2.5V A5 TCSH Chip Select hold time 0 — ns 1.8V VCC 5.5V A6 TCSL Chip Select low time 250 — ns 1.8V VCC 5.5V A7 TDIS Data input setup time 50 — ns 4.5VVCC  5.5V, 93XX46C only 100 2.5V VCC  5.5V 250 1.8V VCC 2.5V A8 TDIH Data input hold time 50 — ns 4.5VVCC  5.5V, 93XX46C only 100 2.5V VCC  5.5V 250 1.8V VCC 2.5V A9 TPD Data output delay time — 200 ns 4.5VVCC  5.5V, CL = 100 pF — 250 2.5V VCC  4.5V, CL = 100 pF — 400 1.8V VCC 2.5V, CL = 100 pF A10 TCZ Data output disable time — 100 ns 4.5VVCC 5.5V, (Note 1) — 200 1.8VVCC  4.5V, (Note 1) A11 TSV Status valid time — 200 ns 4.5VVCC  5.5V, CL = 100 pF 300 2.5V VCC  4.5V, CL = 100 pF 500 1.8V VCC 2.5V, CL = 100 pF A12 TWC Program cycle time — 6 ms Erase/Write mode (AA and LC versions) A13 TWC — 2 ms Erase/Write mode (93C versions) A14 TEC — 6 ms ERAL mode, 4.5V  VCC  5.5V A15 TWL — 15 ms WRAL mode, 4.5V  VCC  5.5V A16 — Endurance 1M — cycles 25°C, VCC = 5.0V, (Note 2) Note1: This parameter is periodically sampled and not 100% tested. 2: This application is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total Endurance™ Model, which may be obtained from Microchip’s web site at www.microchip.com. DS20001749K-page 4  2002-2013 Microchip Technology Inc.

93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C FIGURE 1-1: SYNCHRONOUS DATA TIMING VIH CS VIL TCSS TCKH TCKL TCSH VIH CLK VIL TDIS TDIH VIH DI VIL TPD TPD TCZ VOH DO (Read) VOL TCZ TSV DO VOH (Program) Status Valid VOL Note: TSV is relative to CS. TABLE 1-3: INSTRUCTION SET FOR X16 ORGANIZATION (93XX46B OR 93XX46C WITH ORG = 1) Instruction SB Opcode Address Data In Data Out Req. CLK Cycles ERASE 1 11 A5 A4 A3 A2 A1 A0 — (RDY/BSY) 9 ERAL 1 00 1 0 X X X X — (RDY/BSY) 9 EWDS 1 00 0 0 X X X X — High-Z 9 EWEN 1 00 1 1 X X X X — High-Z 9 READ 1 10 A5 A4 A3 A2 A1 A0 — D15 - D0 25 WRITE 1 01 A5 A4 A3 A2 A1 A0 D15 - D0 (RDY/BSY) 25 WRAL 1 00 0 1 X X X X D15 - D0 (RDY/BSY) 25 TABLE 1-4: INSTRUCTION SET FOR X8 ORGANIZATION (93XX46A OR 93XX46C WITH ORG = 0) Instruction SB Opcode Address Data In Data Out Req. CLK Cycles ERASE 1 11 A6 A5 A4 A3 A2 A1 A0 — (RDY/BSY) 10 ERAL 1 00 1 0 X X X X X — (RDY/BSY) 10 EWDS 1 00 0 0 X X X X X — High-Z 10 EWEN 1 00 1 1 X X X X X — High-Z 10 READ 1 10 A6 A5 A4 A3 A2 A1 A0 — D7 - D0 18 WRITE 1 01 A6 A5 A4 A3 A2 A1 A0 D7 - D0 (RDY/BSY) 18 WRAL 1 00 0 1 X X X X X D7 - D0 (RDY/BSY) 18  2002-2013 Microchip Technology Inc. DS20001749K-page 5

93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C 2.0 FUNCTIONAL DESCRIPTION 2.3 Data Protection When the ORG pin (93XX46C) is connected to VCC, All modes of operation are inhibited when VCC is below the (x16) organization is selected. When it is connected a typical voltage of 1.5V for ‘93AA’ and ‘93LC’ devices to ground, the (x8) organization is selected. Instruc- or 3.8V for ‘93C’ devices. tions, addresses and write data are clocked into the DI The EWEN and EWDS commands give additional pin on the rising edge of the clock (CLK). The DO pin is protection against accidentally programming during normally held in a High-Z state except when reading normal operation. data from the device, or when checking the Ready/ Busy status during a programming operation. The Note: For added protection, an EWDS command Ready/Busy status can be verified during an erase/ should be performed after every write write operation by polling the DO pin; DO low indicates operation and an external 10 k pull- that programming is still in progress, while DO high down protection resistor should be added indicates the device is ready. DO will enter the High-Z to the CS pin. state on the falling edge of CS. After power-up, the device is automatically in the EWDS mode. Therefore, an EWEN instruction must be 2.1 Start Condition performed before the initial ERASE or WRITE instruc- tion can be executed. The Start bit is detected by the device if CS and DI are both high with respect to the positive edge of CLK for Block Diagram the first time. Before a Start condition is detected, CS, CLK and DI VCC VSS may change in any combination (except to that of a Start condition), without resulting in any device Memory Address operation (Read, Write, Erase, EWEN, EWDS, ERAL Array Decoder or WRAL). As soon as CS is high, the device is no longer in Standby mode. Address An instruction following a Start condition will only be Counter executed if the required opcode, address and data bits for any particular instruction are clocked in. DO Output Data Register Note: When preparing to transmit an instruction, Buffer DI either the CLK or DI signal levels must be at a logic low as CS is toggled active-high. Mode ORG* Decode 2.2 Data In/Data Out (DI/DO) CS Logic It is possible to connect the Data In and Data Out pins Clock CLK together. However, with this configuration it is possible Register for a “bus conflict” to occur during the “dummy zero” that precedes the read operation if A0 is a logic high level. Under such a condition the voltage level seen at *ORG input is not available on A/B devices Data Out is undefined and will depend upon the relative impedances of Data Out and the signal source driving A0. The higher the current sourcing capability of A0, the higher the voltage at the Data Out pin. In order to limit this current, a resistor should be connected between DI and DO. DS20001749K-page 6  2002-2013 Microchip Technology Inc.

93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C 2.4 Erase The DO pin indicates the Ready/Busy status of the device if CS is brought high after a minimum of 250 ns The ERASE instruction forces all data bits of the low (TCSL). DO at logical ‘0’ indicates that programming specified address to the logical ‘1’ state. CS is brought is still in progress. DO at logical ‘1’ indicates that the low following the loading of the last address bit. This register at the specified address has been erased and falling edge of the CS pin initiates the self-timed the device is ready for another instruction. programming cycle, except on ‘93C’ devices where the rising edge of CLK before the last address bit initiates Note: After the Erase cycle is complete, issuing the write cycle. a Start bit and then taking CS low will clear the Ready/Busy status from DO. FIGURE 2-1: ERASE TIMING FOR 93AA AND 93LC DEVICES TCSL CS Check Status CLK DI 1 1 1 AN AN-1 AN-2 ••• A0 TSV TCZ High-Z DO Busy Ready High-Z TWC FIGURE 2-2: ERASE TIMING FOR 93C DEVICES TCSL CS Check Status CLK DI 1 1 1 AN AN-1 AN-2 ••• A0 TSV TCZ High-Z DO Busy Ready High-Z TWC  2002-2013 Microchip Technology Inc. DS20001749K-page 7

93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C 2.5 Erase All (ERAL) The DO pin indicates the Ready/Busy status of the device if CS is brought high after a minimum of 250 ns The Erase All (ERAL) instruction will erase the entire low (TCSL). memory array to the logical ‘1’ state. The ERAL cycle is identical to the erase cycle, except for the different Note: After the ERAL command is complete, opcode. The ERAL cycle is completely self-timed and issuing a Start bit and then taking CS low commences at the falling edge of the CS, except on will clear the Ready/Busy status from DO. ‘93C’ devices where the rising edge of CLK before the VCC must be 4.5V for proper operation of ERAL. last data bit initiates the write cycle. Clocking of the CLK pin is not necessary after the device has entered the ERAL cycle. FIGURE 2-3: ERAL TIMING FOR 93AA AND 93LC DEVICES TCSL CS Check Status CLK DI 1 0 0 1 0 x ••• x TSV TCZ High-Z DO Busy Ready High-Z TEC VCC must be 4.5V for proper operation of ERAL. FIGURE 2-4: ERAL TIMING FOR 93C DEVICES TCSL CS Check Status CLK DI 1 0 0 1 0 x ••• x TSV TCZ High-Z DO Busy Ready High-Z TEC DS20001749K-page 8  2002-2013 Microchip Technology Inc.

93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C 2.6 Erase/Write Disable and Enable enabled until an EWDS instruction is executed or Vcc is (EWDS/EWEN) removed from the device. To protect against accidental data disturbance, the EWDS The 93XX46A/B/C powers up in the Erase/Write Disable instruction can be used to disable all erase/write functions (EWDS) state. All programming modes must be preceded and should follow all programming operations. Execution by an Erase/Write Enable (EWEN) instruction. Once the of a READ instruction is independent of both the EWEN EWEN instruction is executed, programming remains and EWDS instructions. FIGURE 2-5: EWDS TIMING TCSL CS CLK DI 1 0 0 0 0 x ••• x FIGURE 2-6: EWEN TIMING TCSL CS CLK 1 0 0 1 1 x ••• x DI 2.7 Read The output data bits will toggle on the rising edge of the CLK and are stable after the specified time delay (TPD). The READ instruction outputs the serial data of the Sequential read is possible when CS is held high. The addressed memory location on the DO pin. A dummy memory data will automatically cycle to the next register zero bit precedes the 8-bit (if ORG pin is low or A-version and output sequentially. devices) or 16-bit (if ORG pin is high or B-version devices) output string. FIGURE 2-7: READ TIMING CS CLK DI 1 1 0 AN ••• A0 High-Z DO 0 Dx ••• D0 Dx ••• D0 Dx ••• D0  2002-2013 Microchip Technology Inc. DS20001749K-page 9

93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C 2.8 Write The DO pin indicates the Ready/Busy status of the device if CS is brought high after a minimum of 250 ns The WRITE instruction is followed by 8 bits (if ORG is low (TCSL). DO at logical ‘0’ indicates that programming low or A-version devices) or 16 bits (if ORG pin is high is still in progress. DO at logical ‘1’ indicates that the or B-version devices) of data, which are written into the register at the specified address has been written with specified address. For 93AA46A/B/C and 93LC46A/B/C the data specified and the device is ready for another devices, after the last data bit is clocked into DI, the instruction. falling edge of CS initiates the self-timed auto-erase and programming cycle. For 93C46A/B/C devices, the self- Note: After the Write cycle is complete, issuing a timed auto-erase and programming cycle is initiated by Start bit and then taking CS low will clear the rising edge of CLK on the last data bit. the Ready/Busy status from DO. FIGURE 2-8: WRITE TIMING FOR 93AA AND 93LC DEVICES TCSL CS CLK DI 1 0 1 AN ••• A0 Dx ••• D0 TSV TCZ High-Z DO Busy Ready High-Z TWC FIGURE 2-9: WRITE TIMING FOR 93C DEVICES TCSL CS CLK DI 1 0 1 AN ••• A0 Dx ••• D0 TSV TCZ High-Z DO Busy Ready High-Z TWC DS20001749K-page 10  2002-2013 Microchip Technology Inc.

93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C 2.9 Write All (WRAL) The DO pin indicates the Ready/Busy status of the device if CS is brought high after a minimum of 250 ns The Write All (WRAL) instruction will write the entire low (TCSL). memory array with the data specified in the command. For 93AA46A/B/C and 93LC46A/B/C devices, after the Note: After the Write All cycle is complete, last data bit is clocked into DI, the falling edge of CS issuing a Start bit and then taking CS low initiates the self-timed auto-erase and programming will clear the Ready/Busy status from DO. cycle. For 93C46A/B/C devices, the self-timed auto- VCC must be 4.5V for proper operation of WRAL. erase and programming cycle is initiated by the rising edge of CLK on the last data bit. Clocking of the CLK pin is not necessary after the device has entered the WRAL cycle. The WRAL command does include an automatic ERAL cycle for the device. Therefore, the WRAL instruction does not require an ERAL instruc- tion, but the chip must be in the EWEN status. FIGURE 2-10: WRAL TIMING FOR 93AA AND 93LC DEVICES TCSL CS CLK DI 1 0 0 0 1 x ••• x Dx ••• D0 TSV TCZ High-Z DO Busy Ready HIGH-Z TWL VCC must be 4.5V for proper operation of WRAL. FIGURE 2-11: WRAL TIMING FOR 93C DEVICES TCSL CS CLK DI 1 0 0 0 1 x ••• x Dx ••• D0 TSV TCZ High-Z DO Busy Ready HIGH-Z TWL  2002-2013 Microchip Technology Inc. DS20001749K-page 11

93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C 3.0 PIN DESCRIPTIONS TABLE 3-1: PIN DESCRIPTIONS Rotated Name PDIP SOIC TSSOP MSOP DFN(1) TDFN(1) SOT-23 Function SOIC CS 1 1 1 1 1 1 5 3 Chip Select CLK 2 2 2 2 2 2 4 4 Serial Clock DI 3 3 3 3 3 3 3 5 Data In DO 4 4 4 4 4 4 1 6 Data Out Vss 5 5 5 5 5 5 2 7 Ground ORG/NC 6 6 6 6 6 6 — 8 Organization/93XX46C No Internal Connection/ 93XX46A/B NC 7 7 7 7 7 7 — 1 No Internal Connection VCC 8 8 8 8 8 8 6 2 Power Supply Note 1: The exposed pad on the DFN/TDFN packages can be connected to VSS or left floating. 3.1 Chip Select (CS) data bits before an instruction is executed. CLK and DI then become “don't care” inputs waiting for a new Start A high level selects the device; a low level deselects condition to be detected. the device and forces it into Standby mode. However, a programming cycle that is already in progress will be 3.3 Data In (DI) completed, regardless of the Chip Select (CS) input signal. If CS is brought low during a program cycle, the Data In (DI) is used to clock in a Start bit, opcode, device will go into Standby mode as soon as the address and data synchronously with the CLK input. programming cycle is completed. CS must be low for 250 ns minimum (TCSL) between 3.4 Data Out (DO) consecutive instructions. If CS is low, the internal Data Out (DO) is used in the Read mode to output data control logic is held in a Reset status. synchronously with the CLK input (TPD after the positive edge of CLK). 3.2 Serial Clock (CLK) This pin also provides Ready/Busy status information The Serial Clock is used to synchronize the communi- during erase and write cycles. Ready/Busy status infor- cation between a master device and the 93XX series mation is available on the DO pin if CS is brought high device. Opcodes, address and data bits are clocked in after being low for minimum Chip Select low time (TCSL) on the positive edge of CLK. Data bits are also clocked and an erase or write operation has been initiated. out on the positive edge of CLK. The Status signal is not available on DO if CS is held CLK can be stopped anywhere in the transmission low during the entire erase or write cycle. In this case, sequence (at high or low level) and can be continued DO is in the High-Z mode. If status is checked after the anytime with respect to clock high time (TCKH) and erase/write cycle, the data line will be high to indicate clock low time (TCKL). This gives the controlling master the device is ready. freedom in preparing opcode, address and data. Note: After a programming cycle is complete, CLK is a “don't care” if CS is low (device deselected). If issuing a Start bit and then taking CS low CS is high, but the Start condition has not been will clear the Ready/Busy status from DO. detected (DI = 0), any number of clock cycles can be received by the device without changing its status (i.e., 3.5 Organization (ORG) waiting for a Start condition). CLK cycles are not required during the self-timed write When the ORG pin is connected to VCC or Logic HI, the (i.e., auto erase/write) cycle. (x16) memory organization is selected. When the ORG pin is tied to VSS or Logic LO, the (x8) memory After detection of a Start condition the specified number organization is selected. For proper operation, ORG of clock cycles (respectively low-to-high transitions of must be tied to a valid logic level. CLK) must be provided. These clock cycles are required to clock in all required opcode, address and 93XX46A devices are always (x8) organization and 93XX46B devices are always (x16) organization. DS20001749K-page 12  2002-2013 Microchip Technology Inc.

93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C 4.0 PACKAGING INFORMATION 4.1 Package Marking Information 8-Lead MSOP (150 mil) Example: XXXXXXT 3L46BI YWWNNN 5281L7 6-Lead SOT-23 Example: XXNN 1EL7 8-Lead PDIP Example: XXXXXXXX 93LC46B T/XXXNNN I/P e 3 1L7 YYWW 0528 8-Lead SOIC Example: XXXXXXXT 93LC46BI XXXXYYWW SN e 3 0528 NNN 1L7 8-Lead Rotated SOIC Example: XXXXXXXT 93L46BXI XXXXYYWW SN e 3 0528 NNN 1L7 8-Lead TSSOP Example: XXXX L46B TYWW I528 NNN 1L7  2002-2013 Microchip Technology Inc. DS20001749K-page 13

93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C 8-Lead 2x3 DFN Example: XXX 314 YWW 528 NN L7 8-Lead 2x3 TDFN Example: XXX E14 YWW 528 NN L7 1st Line Marking Codes Part Number SOT-23 DFN TDFN TSSOP MSOP I Temp. E Temp. I Temp. E Temp. I Temp. E Temp. 93AA46A A46A 3A46AT 1BNN — 301 — E01 — 93AA46B A46B 3A46BT 1LNN — 311 — E11 — 93AA46C A46C 3A46CT — — 321 — E21 — 93LC46A L46A 3L46AT 1ENN 1FNN 304 — E04 E05 93LC46B L46B 3L46BT 1PNN 1RNN 314 — E14 E15 93LC46C L46C 3L46CT — — 324 — E24 E25 93C46A C46A 3C46AT 1HNN 1JNN 307 — E07 E08 93C46B C46B 3C46BT 1TNN 1UNN 317 — E17 E18 93C46C C46C 3C46CT — — 327 — E27 E28 Note: T = Temperature grade (I, E) NN = Alphanumeric traceability code Legend: XX...X Part number or part number code T Temperature (I, E) Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code (2 characters for small packages) e3 Pb-free JEDEC designator for Matte Tin (Sn) Note: For very small packages with no room for the Pb-free JEDEC designator e3 , the marking will only appear on the outer carton or reel label. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. DS20001749K-page 14  2002-2013 Microchip Technology Inc.

93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C Note: For the mostcurrent package drawings,please seetheMicrochip Packaging Specification located at http://www.microchip.com/packaging  2002-2013 Microchip Technology Inc. DS20001749K-page 15

93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C Note: For the mostcurrent package drawings,please seetheMicrochip Packaging Specification located at http://www.microchip.com/packaging DS20001749K-page 16  2002-2013 Microchip Technology Inc.

93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2002-2013 Microchip Technology Inc. DS20001749K-page 17

93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)(cid:15)(cid:16)(cid:6)(cid:10)(cid:10)(cid:8)(cid:17)(cid:18)(cid:12)(cid:10)(cid:13)(cid:19)(cid:5)(cid:8)(cid:20)(cid:21)(cid:6)(cid:19)(cid:11)(cid:13)(cid:11)(cid:12)(cid:22)(cid:21)(cid:8)(cid:23)(cid:17)(cid:20)(cid:24)(cid:8)(cid:25)(cid:15)(cid:17)(cid:20)(cid:3)(cid:26)(cid:27)(cid:28) (cid:29)(cid:22)(cid:12)(cid:5)(cid:30) .(cid:10)(cid:9)(cid:2)#(cid:11)(cid:14)(cid:2)(cid:31)(cid:10) #(cid:2)(cid:8)$(cid:9)(cid:9)(cid:14)(cid:15)#(cid:2)(cid:12)(cid:28)(cid:8)/(cid:28)(cid:17)(cid:14)(cid:2)!(cid:9)(cid:28)-(cid:7)(cid:15)(cid:17) 0(cid:2)(cid:12)(cid:16)(cid:14)(cid:28) (cid:14)(cid:2) (cid:14)(cid:14)(cid:2)#(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)1(cid:28)(cid:8)/(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)#(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)#(cid:14)!(cid:2)(cid:28)#(cid:2) (cid:11)##(cid:12)+22---(cid:20)(cid:31)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)(cid:31)2(cid:12)(cid:28)(cid:8)/(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) b N 4 E E1 PIN1IDBY LASERMARK 1 2 3 e e1 D A A2 c φ L A1 L1 3(cid:15)(cid:7)# (cid:6)(cid:19)44(cid:19)(cid:6)"(cid:13)"(cid:26)(cid:22) (cid:21)(cid:7)(cid:31)(cid:14)(cid:15) (cid:7)(cid:10)(cid:15)(cid:2)4(cid:7)(cid:31)(cid:7)# (cid:6)(cid:19)5 56(cid:6) (cid:6)(cid:25)7 5$(cid:31)8(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)1(cid:7)(cid:15) 5 9 1(cid:7)#(cid:8)(cid:11) (cid:14) (cid:4)(cid:20)(cid:24)((cid:2))(cid:22)* 6$# (cid:7)!(cid:14)(cid:2)4(cid:14)(cid:28)!(cid:2)1(cid:7)#(cid:8)(cid:11) (cid:14)(cid:30) (cid:30)(cid:20)(cid:24)(cid:4)(cid:2))(cid:22)* 6,(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2):(cid:14)(cid:7)(cid:17)(cid:11)# (cid:25) (cid:4)(cid:20)(cid:24)(cid:4) ; (cid:30)(cid:20)(cid:23)( (cid:6)(cid:10)(cid:16)!(cid:14)!(cid:2)1(cid:28)(cid:8)/(cid:28)(cid:17)(cid:14)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)/(cid:15)(cid:14) (cid:25)(cid:3) (cid:4)(cid:20)<(cid:24) ; (cid:30)(cid:20)(cid:29)(cid:4) (cid:22)#(cid:28)(cid:15)!(cid:10)%% (cid:25)(cid:30) (cid:4)(cid:20)(cid:4)(cid:4) ; (cid:4)(cid:20)(cid:30)( 6,(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)=(cid:7)!#(cid:11) " (cid:3)(cid:20)(cid:3)(cid:4) ; (cid:29)(cid:20)(cid:3)(cid:4) (cid:6)(cid:10)(cid:16)!(cid:14)!(cid:2)1(cid:28)(cid:8)/(cid:28)(cid:17)(cid:14)(cid:2)=(cid:7)!#(cid:11) "(cid:30) (cid:30)(cid:20)(cid:29)(cid:4) ; (cid:30)(cid:20)<(cid:4) 6,(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)4(cid:14)(cid:15)(cid:17)#(cid:11) (cid:21) (cid:3)(cid:20)(cid:5)(cid:4) ; (cid:29)(cid:20)(cid:30)(cid:4) .(cid:10)(cid:10)#(cid:2)4(cid:14)(cid:15)(cid:17)#(cid:11) 4 (cid:4)(cid:20)(cid:30)(cid:4) ; (cid:4)(cid:20)9(cid:4) .(cid:10)(cid:10)#(cid:12)(cid:9)(cid:7)(cid:15)# 4(cid:30) (cid:4)(cid:20)(cid:29)( ; (cid:4)(cid:20)<(cid:4) .(cid:10)(cid:10)#(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14) (cid:3) (cid:4)> ; (cid:29)(cid:4)> 4(cid:14)(cid:28)!(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)/(cid:15)(cid:14) (cid:8) (cid:4)(cid:20)(cid:4)< ; (cid:4)(cid:20)(cid:3)9 4(cid:14)(cid:28)!(cid:2)=(cid:7)!#(cid:11) 8 (cid:4)(cid:20)(cid:3)(cid:4) ; (cid:4)(cid:20)((cid:30) (cid:29)(cid:22)(cid:12)(cid:5)(cid:11)(cid:30) (cid:30)(cid:20) (cid:21)(cid:7)(cid:31)(cid:14)(cid:15) (cid:7)(cid:10)(cid:15) (cid:2)(cid:21)(cid:2)(cid:28)(cid:15)!(cid:2)"(cid:30)(cid:2)!(cid:10)(cid:2)(cid:15)(cid:10)#(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)$!(cid:14)(cid:2)(cid:31)(cid:10)(cid:16)!(cid:2)%(cid:16)(cid:28) (cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)#(cid:9)$ (cid:7)(cid:10)(cid:15) (cid:20)(cid:2)(cid:6)(cid:10)(cid:16)!(cid:2)%(cid:16)(cid:28) (cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)#(cid:9)$ (cid:7)(cid:10)(cid:15) (cid:2) (cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)#(cid:2)(cid:14)&(cid:8)(cid:14)(cid:14)!(cid:2)(cid:4)(cid:20)(cid:30)(cid:3)(cid:5)(cid:2)(cid:31)(cid:31)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2) (cid:7)!(cid:14)(cid:20) (cid:3)(cid:20) (cid:21)(cid:7)(cid:31)(cid:14)(cid:15) (cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)!(cid:2)#(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6)"(cid:2)’(cid:30)(cid:23)(cid:20)((cid:6)(cid:20) )(cid:22)*+ )(cid:28) (cid:7)(cid:8)(cid:2)(cid:21)(cid:7)(cid:31)(cid:14)(cid:15) (cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)#(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)&(cid:28)(cid:8)#(cid:2),(cid:28)(cid:16)$(cid:14)(cid:2) (cid:11)(cid:10)-(cid:15)(cid:2)-(cid:7)#(cid:11)(cid:10)$#(cid:2)#(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14) (cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)-(cid:7)(cid:15)(cid:17)*(cid:4)(cid:23)(cid:27)(cid:4)(cid:3)<) DS20001749K-page 18  2002-2013 Microchip Technology Inc.

93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2002-2013 Microchip Technology Inc. DS20001749K-page 19

93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C (cid:31)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8) (cid:18)(cid:6)(cid:10)(cid:8)!(cid:19)(cid:3)(cid:4)(cid:13)(cid:19)(cid:5)(cid:8)(cid:23)(cid:9)(cid:24)(cid:8)"(cid:8)(cid:27)##(cid:8)(cid:16)(cid:13)(cid:10)(cid:8)$(cid:22)(cid:7)%(cid:8)(cid:25)(cid:9) !(cid:9)(cid:28) (cid:29)(cid:22)(cid:12)(cid:5)(cid:30) .(cid:10)(cid:9)(cid:2)#(cid:11)(cid:14)(cid:2)(cid:31)(cid:10) #(cid:2)(cid:8)$(cid:9)(cid:9)(cid:14)(cid:15)#(cid:2)(cid:12)(cid:28)(cid:8)/(cid:28)(cid:17)(cid:14)(cid:2)!(cid:9)(cid:28)-(cid:7)(cid:15)(cid:17) 0(cid:2)(cid:12)(cid:16)(cid:14)(cid:28) (cid:14)(cid:2) (cid:14)(cid:14)(cid:2)#(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)1(cid:28)(cid:8)/(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)#(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)#(cid:14)!(cid:2)(cid:28)#(cid:2) (cid:11)##(cid:12)+22---(cid:20)(cid:31)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)(cid:31)2(cid:12)(cid:28)(cid:8)/(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) N NOTE1 E1 1 2 3 D E A A2 L A1 c e eB b1 b 3(cid:15)(cid:7)# (cid:19)5*:"(cid:22) (cid:21)(cid:7)(cid:31)(cid:14)(cid:15) (cid:7)(cid:10)(cid:15)(cid:2)4(cid:7)(cid:31)(cid:7)# (cid:6)(cid:19)5 56(cid:6) (cid:6)(cid:25)7 5$(cid:31)8(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)1(cid:7)(cid:15) 5 < 1(cid:7)#(cid:8)(cid:11) (cid:14) (cid:20)(cid:30)(cid:4)(cid:4)(cid:2))(cid:22)* (cid:13)(cid:10)(cid:12)(cid:2)#(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)#(cid:7)(cid:15)(cid:17)(cid:2)1(cid:16)(cid:28)(cid:15)(cid:14) (cid:25) ; ; (cid:20)(cid:3)(cid:30)(cid:4) (cid:6)(cid:10)(cid:16)!(cid:14)!(cid:2)1(cid:28)(cid:8)/(cid:28)(cid:17)(cid:14)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)/(cid:15)(cid:14) (cid:25)(cid:3) (cid:20)(cid:30)(cid:30)( (cid:20)(cid:30)(cid:29)(cid:4) (cid:20)(cid:30)(cid:24)( )(cid:28) (cid:14)(cid:2)#(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)#(cid:7)(cid:15)(cid:17)(cid:2)1(cid:16)(cid:28)(cid:15)(cid:14) (cid:25)(cid:30) (cid:20)(cid:4)(cid:30)( ; ; (cid:22)(cid:11)(cid:10)$(cid:16)!(cid:14)(cid:9)(cid:2)#(cid:10)(cid:2)(cid:22)(cid:11)(cid:10)$(cid:16)!(cid:14)(cid:9)(cid:2)=(cid:7)!#(cid:11) " (cid:20)(cid:3)(cid:24)(cid:4) (cid:20)(cid:29)(cid:30)(cid:4) (cid:20)(cid:29)(cid:3)( (cid:6)(cid:10)(cid:16)!(cid:14)!(cid:2)1(cid:28)(cid:8)/(cid:28)(cid:17)(cid:14)(cid:2)=(cid:7)!#(cid:11) "(cid:30) (cid:20)(cid:3)(cid:23)(cid:4) (cid:20)(cid:3)((cid:4) (cid:20)(cid:3)<(cid:4) 6,(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)4(cid:14)(cid:15)(cid:17)#(cid:11) (cid:21) (cid:20)(cid:29)(cid:23)< (cid:20)(cid:29)9( (cid:20)(cid:23)(cid:4)(cid:4) (cid:13)(cid:7)(cid:12)(cid:2)#(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)#(cid:7)(cid:15)(cid:17)(cid:2)1(cid:16)(cid:28)(cid:15)(cid:14) 4 (cid:20)(cid:30)(cid:30)( (cid:20)(cid:30)(cid:29)(cid:4) (cid:20)(cid:30)((cid:4) 4(cid:14)(cid:28)!(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)/(cid:15)(cid:14) (cid:8) (cid:20)(cid:4)(cid:4)< (cid:20)(cid:4)(cid:30)(cid:4) (cid:20)(cid:4)(cid:30)( 3(cid:12)(cid:12)(cid:14)(cid:9)(cid:2)4(cid:14)(cid:28)!(cid:2)=(cid:7)!#(cid:11) 8(cid:30) (cid:20)(cid:4)(cid:23)(cid:4) (cid:20)(cid:4)9(cid:4) (cid:20)(cid:4)(cid:5)(cid:4) 4(cid:10)-(cid:14)(cid:9)(cid:2)4(cid:14)(cid:28)!(cid:2)=(cid:7)!#(cid:11) 8 (cid:20)(cid:4)(cid:30)(cid:23) (cid:20)(cid:4)(cid:30)< (cid:20)(cid:4)(cid:3)(cid:3) 6,(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)(cid:26)(cid:10)-(cid:2)(cid:22)(cid:12)(cid:28)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:2)? (cid:14)) ; ; (cid:20)(cid:23)(cid:29)(cid:4) (cid:29)(cid:22)(cid:12)(cid:5)(cid:11)(cid:30) (cid:30)(cid:20) 1(cid:7)(cid:15)(cid:2)(cid:30)(cid:2),(cid:7) $(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)!(cid:14)&(cid:2)%(cid:14)(cid:28)#$(cid:9)(cid:14)(cid:2)(cid:31)(cid:28)(cid:18)(cid:2),(cid:28)(cid:9)(cid:18)0(cid:2)8$#(cid:2)(cid:31)$ #(cid:2)8(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)#(cid:14)!(cid:2)-(cid:7)#(cid:11)(cid:2)#(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)#(cid:8)(cid:11)(cid:14)!(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) ?(cid:2)(cid:22)(cid:7)(cid:17)(cid:15)(cid:7)%(cid:7)(cid:8)(cid:28)(cid:15)#(cid:2)*(cid:11)(cid:28)(cid:9)(cid:28)(cid:8)#(cid:14)(cid:9)(cid:7) #(cid:7)(cid:8)(cid:20) (cid:29)(cid:20) (cid:21)(cid:7)(cid:31)(cid:14)(cid:15) (cid:7)(cid:10)(cid:15) (cid:2)(cid:21)(cid:2)(cid:28)(cid:15)!(cid:2)"(cid:30)(cid:2)!(cid:10)(cid:2)(cid:15)(cid:10)#(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)$!(cid:14)(cid:2)(cid:31)(cid:10)(cid:16)!(cid:2)%(cid:16)(cid:28) (cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)#(cid:9)$ (cid:7)(cid:10)(cid:15) (cid:20)(cid:2)(cid:6)(cid:10)(cid:16)!(cid:2)%(cid:16)(cid:28) (cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)#(cid:9)$ (cid:7)(cid:10)(cid:15) (cid:2) (cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)#(cid:2)(cid:14)&(cid:8)(cid:14)(cid:14)!(cid:2)(cid:20)(cid:4)(cid:30)(cid:4)@(cid:2)(cid:12)(cid:14)(cid:9)(cid:2) (cid:7)!(cid:14)(cid:20) (cid:23)(cid:20) (cid:21)(cid:7)(cid:31)(cid:14)(cid:15) (cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)!(cid:2)#(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6)"(cid:2)’(cid:30)(cid:23)(cid:20)((cid:6)(cid:20) )(cid:22)*+(cid:2))(cid:28) (cid:7)(cid:8)(cid:2)(cid:21)(cid:7)(cid:31)(cid:14)(cid:15) (cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)#(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)&(cid:28)(cid:8)#(cid:2),(cid:28)(cid:16)$(cid:14)(cid:2) (cid:11)(cid:10)-(cid:15)(cid:2)-(cid:7)#(cid:11)(cid:10)$#(cid:2)#(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14) (cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)-(cid:7)(cid:15)(cid:17)*(cid:4)(cid:23)(cid:27)(cid:4)(cid:30)<) DS20001749K-page 20  2002-2013 Microchip Technology Inc.

93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2002-2013 Microchip Technology Inc. DS20001749K-page 21

93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS20001749K-page 22  2002-2013 Microchip Technology Inc.

93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C (cid:31)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)(cid:15)(cid:16)(cid:6)(cid:10)(cid:10)(cid:8)(cid:17)(cid:18)(cid:12)(cid:10)(cid:13)(cid:19)(cid:5)(cid:8)(cid:23)(cid:15)(cid:29)(cid:24)(cid:8)"(cid:8)(cid:29)(cid:6)(cid:21)(cid:21)(cid:22)&’(cid:8)(cid:27)()#(cid:8)(cid:16)(cid:16)(cid:8)$(cid:22)(cid:7)%(cid:8)(cid:25)(cid:15)(cid:17)!*(cid:28) (cid:29)(cid:22)(cid:12)(cid:5)(cid:30) .(cid:10)(cid:9)(cid:2)#(cid:11)(cid:14)(cid:2)(cid:31)(cid:10) #(cid:2)(cid:8)$(cid:9)(cid:9)(cid:14)(cid:15)#(cid:2)(cid:12)(cid:28)(cid:8)/(cid:28)(cid:17)(cid:14)(cid:2)!(cid:9)(cid:28)-(cid:7)(cid:15)(cid:17) 0(cid:2)(cid:12)(cid:16)(cid:14)(cid:28) (cid:14)(cid:2) (cid:14)(cid:14)(cid:2)#(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)1(cid:28)(cid:8)/(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)#(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)#(cid:14)!(cid:2)(cid:28)#(cid:2) (cid:11)##(cid:12)+22---(cid:20)(cid:31)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)(cid:31)2(cid:12)(cid:28)(cid:8)/(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)  2002-2013 Microchip Technology Inc. DS20001749K-page 23

93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C (cid:31)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)(cid:20)+(cid:13)(cid:19)(cid:8)(cid:15)+(cid:21)(cid:13)(cid:19),(cid:8)(cid:15)(cid:16)(cid:6)(cid:10)(cid:10)(cid:8)(cid:17)(cid:18)(cid:12)(cid:10)(cid:13)(cid:19)(cid:5)(cid:8)(cid:23)(cid:15)(cid:20)(cid:24)(cid:8)"(cid:8)-(-(cid:8)(cid:16)(cid:16)(cid:8)$(cid:22)(cid:7)%(cid:8)(cid:25)(cid:20)(cid:15)(cid:15)(cid:17)(cid:9)(cid:28) (cid:29)(cid:22)(cid:12)(cid:5)(cid:30) .(cid:10)(cid:9)(cid:2)#(cid:11)(cid:14)(cid:2)(cid:31)(cid:10) #(cid:2)(cid:8)$(cid:9)(cid:9)(cid:14)(cid:15)#(cid:2)(cid:12)(cid:28)(cid:8)/(cid:28)(cid:17)(cid:14)(cid:2)!(cid:9)(cid:28)-(cid:7)(cid:15)(cid:17) 0(cid:2)(cid:12)(cid:16)(cid:14)(cid:28) (cid:14)(cid:2) (cid:14)(cid:14)(cid:2)#(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)1(cid:28)(cid:8)/(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)#(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)#(cid:14)!(cid:2)(cid:28)#(cid:2) (cid:11)##(cid:12)+22---(cid:20)(cid:31)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)(cid:31)2(cid:12)(cid:28)(cid:8)/(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) D N E E1 NOTE1 1 2 b e c φ A A2 A1 L1 L 3(cid:15)(cid:7)# (cid:6)(cid:19)44(cid:19)(cid:6)"(cid:13)"(cid:26)(cid:22) (cid:21)(cid:7)(cid:31)(cid:14)(cid:15) (cid:7)(cid:10)(cid:15)(cid:2)4(cid:7)(cid:31)(cid:7)# (cid:6)(cid:19)5 56(cid:6) (cid:6)(cid:25)7 5$(cid:31)8(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)1(cid:7)(cid:15) 5 < 1(cid:7)#(cid:8)(cid:11) (cid:14) (cid:4)(cid:20)9((cid:2))(cid:22)* 6,(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2):(cid:14)(cid:7)(cid:17)(cid:11)# (cid:25) ; ; (cid:30)(cid:20)(cid:3)(cid:4) (cid:6)(cid:10)(cid:16)!(cid:14)!(cid:2)1(cid:28)(cid:8)/(cid:28)(cid:17)(cid:14)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)/(cid:15)(cid:14) (cid:25)(cid:3) (cid:4)(cid:20)<(cid:4) (cid:30)(cid:20)(cid:4)(cid:4) (cid:30)(cid:20)(cid:4)( (cid:22)#(cid:28)(cid:15)!(cid:10)%%(cid:2) (cid:25)(cid:30) (cid:4)(cid:20)(cid:4)( ; (cid:4)(cid:20)(cid:30)( 6,(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)=(cid:7)!#(cid:11) " 9(cid:20)(cid:23)(cid:4)(cid:2))(cid:22)* (cid:6)(cid:10)(cid:16)!(cid:14)!(cid:2)1(cid:28)(cid:8)/(cid:28)(cid:17)(cid:14)(cid:2)=(cid:7)!#(cid:11) "(cid:30) (cid:23)(cid:20)(cid:29)(cid:4) (cid:23)(cid:20)(cid:23)(cid:4) (cid:23)(cid:20)((cid:4) (cid:6)(cid:10)(cid:16)!(cid:14)!(cid:2)1(cid:28)(cid:8)/(cid:28)(cid:17)(cid:14)(cid:2)4(cid:14)(cid:15)(cid:17)#(cid:11) (cid:21) (cid:3)(cid:20)(cid:24)(cid:4) (cid:29)(cid:20)(cid:4)(cid:4) (cid:29)(cid:20)(cid:30)(cid:4) .(cid:10)(cid:10)#(cid:2)4(cid:14)(cid:15)(cid:17)#(cid:11) 4 (cid:4)(cid:20)(cid:23)( (cid:4)(cid:20)9(cid:4) (cid:4)(cid:20)(cid:5)( .(cid:10)(cid:10)#(cid:12)(cid:9)(cid:7)(cid:15)# 4(cid:30) (cid:30)(cid:20)(cid:4)(cid:4)(cid:2)(cid:26)". .(cid:10)(cid:10)#(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14) (cid:3) (cid:4)> ; <> 4(cid:14)(cid:28)!(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)/(cid:15)(cid:14) (cid:8) (cid:4)(cid:20)(cid:4)(cid:24) ; (cid:4)(cid:20)(cid:3)(cid:4) 4(cid:14)(cid:28)!(cid:2)=(cid:7)!#(cid:11) 8 (cid:4)(cid:20)(cid:30)(cid:24) ; (cid:4)(cid:20)(cid:29)(cid:4) (cid:29)(cid:22)(cid:12)(cid:5)(cid:11)(cid:30) (cid:30)(cid:20) 1(cid:7)(cid:15)(cid:2)(cid:30)(cid:2),(cid:7) $(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)!(cid:14)&(cid:2)%(cid:14)(cid:28)#$(cid:9)(cid:14)(cid:2)(cid:31)(cid:28)(cid:18)(cid:2),(cid:28)(cid:9)(cid:18)0(cid:2)8$#(cid:2)(cid:31)$ #(cid:2)8(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)#(cid:14)!(cid:2)-(cid:7)#(cid:11)(cid:7)(cid:15)(cid:2)#(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)#(cid:8)(cid:11)(cid:14)!(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) (cid:21)(cid:7)(cid:31)(cid:14)(cid:15) (cid:7)(cid:10)(cid:15) (cid:2)(cid:21)(cid:2)(cid:28)(cid:15)!(cid:2)"(cid:30)(cid:2)!(cid:10)(cid:2)(cid:15)(cid:10)#(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)$!(cid:14)(cid:2)(cid:31)(cid:10)(cid:16)!(cid:2)%(cid:16)(cid:28) (cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)#(cid:9)$ (cid:7)(cid:10)(cid:15) (cid:20)(cid:2)(cid:6)(cid:10)(cid:16)!(cid:2)%(cid:16)(cid:28) (cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)#(cid:9)$ (cid:7)(cid:10)(cid:15) (cid:2) (cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)#(cid:2)(cid:14)&(cid:8)(cid:14)(cid:14)!(cid:2)(cid:4)(cid:20)(cid:30)((cid:2)(cid:31)(cid:31)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2) (cid:7)!(cid:14)(cid:20) (cid:29)(cid:20) (cid:21)(cid:7)(cid:31)(cid:14)(cid:15) (cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)!(cid:2)#(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6)"(cid:2)’(cid:30)(cid:23)(cid:20)((cid:6)(cid:20) )(cid:22)*+ )(cid:28) (cid:7)(cid:8)(cid:2)(cid:21)(cid:7)(cid:31)(cid:14)(cid:15) (cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)#(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)&(cid:28)(cid:8)#(cid:2),(cid:28)(cid:16)$(cid:14)(cid:2) (cid:11)(cid:10)-(cid:15)(cid:2)-(cid:7)#(cid:11)(cid:10)$#(cid:2)#(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14) (cid:20) (cid:26)".+ (cid:26)(cid:14)%(cid:14)(cid:9)(cid:14)(cid:15)(cid:8)(cid:14)(cid:2)(cid:21)(cid:7)(cid:31)(cid:14)(cid:15) (cid:7)(cid:10)(cid:15)0(cid:2)$ $(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)-(cid:7)#(cid:11)(cid:10)$#(cid:2)#(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)0(cid:2)%(cid:10)(cid:9)(cid:2)(cid:7)(cid:15)%(cid:10)(cid:9)(cid:31)(cid:28)#(cid:7)(cid:10)(cid:15)(cid:2)(cid:12)$(cid:9)(cid:12)(cid:10) (cid:14) (cid:2)(cid:10)(cid:15)(cid:16)(cid:18)(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)-(cid:7)(cid:15)(cid:17)*(cid:4)(cid:23)(cid:27)(cid:4)<9) DS20001749K-page 24  2002-2013 Microchip Technology Inc.

93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2002-2013 Microchip Technology Inc. DS20001749K-page 25

93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C (cid:31)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8) (cid:18)(cid:6)(cid:10)(cid:8).(cid:10)(cid:6)(cid:12)’(cid:8)(cid:29)(cid:22)(cid:8)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:6)(cid:14),(cid:6)/(cid:5)(cid:8)(cid:23)0*(cid:24)(cid:8)"(cid:8)(cid:26)1(cid:27)1#()(cid:8)(cid:16)(cid:16)(cid:8)$(cid:22)(cid:7)%(cid:8)(cid:25) .(cid:29)(cid:28) (cid:29)(cid:22)(cid:12)(cid:5)(cid:30) .(cid:10)(cid:9)(cid:2)#(cid:11)(cid:14)(cid:2)(cid:31)(cid:10) #(cid:2)(cid:8)$(cid:9)(cid:9)(cid:14)(cid:15)#(cid:2)(cid:12)(cid:28)(cid:8)/(cid:28)(cid:17)(cid:14)(cid:2)!(cid:9)(cid:28)-(cid:7)(cid:15)(cid:17) 0(cid:2)(cid:12)(cid:16)(cid:14)(cid:28) (cid:14)(cid:2) (cid:14)(cid:14)(cid:2)#(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)1(cid:28)(cid:8)/(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)#(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)#(cid:14)!(cid:2)(cid:28)#(cid:2) (cid:11)##(cid:12)+22---(cid:20)(cid:31)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)(cid:31)2(cid:12)(cid:28)(cid:8)/(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) D e b N N L K E E2 EXPOSEDPAD NOTE1 NOTE1 1 2 2 1 D2 TOPVIEW BOTTOMVIEW A NOTE2 A3 A1 3(cid:15)(cid:7)# (cid:6)(cid:19)44(cid:19)(cid:6)"(cid:13)"(cid:26)(cid:22) (cid:21)(cid:7)(cid:31)(cid:14)(cid:15) (cid:7)(cid:10)(cid:15)(cid:2)4(cid:7)(cid:31)(cid:7)# (cid:6)(cid:19)5 56(cid:6) (cid:6)(cid:25)7 5$(cid:31)8(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)1(cid:7)(cid:15) 5 < 1(cid:7)#(cid:8)(cid:11) (cid:14) (cid:4)(cid:20)((cid:4)(cid:2))(cid:22)* 6,(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2):(cid:14)(cid:7)(cid:17)(cid:11)# (cid:25) (cid:4)(cid:20)<(cid:4) (cid:4)(cid:20)(cid:24)(cid:4) (cid:30)(cid:20)(cid:4)(cid:4) (cid:22)#(cid:28)(cid:15)!(cid:10)%%(cid:2) (cid:25)(cid:30) (cid:4)(cid:20)(cid:4)(cid:4) (cid:4)(cid:20)(cid:4)(cid:3) (cid:4)(cid:20)(cid:4)( *(cid:10)(cid:15)#(cid:28)(cid:8)#(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)/(cid:15)(cid:14) (cid:25)(cid:29) (cid:4)(cid:20)(cid:3)(cid:4)(cid:2)(cid:26)". 6,(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)4(cid:14)(cid:15)(cid:17)#(cid:11) (cid:21) (cid:3)(cid:20)(cid:4)(cid:4)(cid:2))(cid:22)* 6,(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)=(cid:7)!#(cid:11) " (cid:29)(cid:20)(cid:4)(cid:4)(cid:2))(cid:22)* "&(cid:12)(cid:10) (cid:14)!(cid:2)1(cid:28)!(cid:2)4(cid:14)(cid:15)(cid:17)#(cid:11) (cid:21)(cid:3) (cid:30)(cid:20)(cid:29)(cid:4) ; (cid:30)(cid:20)(( "&(cid:12)(cid:10) (cid:14)!(cid:2)1(cid:28)!(cid:2)=(cid:7)!#(cid:11) "(cid:3) (cid:30)(cid:20)((cid:4) ; (cid:30)(cid:20)(cid:5)( *(cid:10)(cid:15)#(cid:28)(cid:8)#(cid:2)=(cid:7)!#(cid:11) 8 (cid:4)(cid:20)(cid:3)(cid:4) (cid:4)(cid:20)(cid:3)( (cid:4)(cid:20)(cid:29)(cid:4) *(cid:10)(cid:15)#(cid:28)(cid:8)#(cid:2)4(cid:14)(cid:15)(cid:17)#(cid:11) 4 (cid:4)(cid:20)(cid:29)(cid:4) (cid:4)(cid:20)(cid:23)(cid:4) (cid:4)(cid:20)((cid:4) *(cid:10)(cid:15)#(cid:28)(cid:8)#(cid:27)#(cid:10)(cid:27)"&(cid:12)(cid:10) (cid:14)!(cid:2)1(cid:28)! U (cid:4)(cid:20)(cid:3)(cid:4) ; ; (cid:29)(cid:22)(cid:12)(cid:5)(cid:11)(cid:30) (cid:30)(cid:20) 1(cid:7)(cid:15)(cid:2)(cid:30)(cid:2),(cid:7) $(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)!(cid:14)&(cid:2)%(cid:14)(cid:28)#$(cid:9)(cid:14)(cid:2)(cid:31)(cid:28)(cid:18)(cid:2),(cid:28)(cid:9)(cid:18)0(cid:2)8$#(cid:2)(cid:31)$ #(cid:2)8(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)#(cid:14)!(cid:2)-(cid:7)#(cid:11)(cid:7)(cid:15)(cid:2)#(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)#(cid:8)(cid:11)(cid:14)!(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) 1(cid:28)(cid:8)/(cid:28)(cid:17)(cid:14)(cid:2)(cid:31)(cid:28)(cid:18)(cid:2)(cid:11)(cid:28),(cid:14)(cid:2)(cid:10)(cid:15)(cid:14)(cid:2)(cid:10)(cid:9)(cid:2)(cid:31)(cid:10)(cid:9)(cid:14)(cid:2)(cid:14)&(cid:12)(cid:10) (cid:14)!(cid:2)#(cid:7)(cid:14)(cid:2)8(cid:28)(cid:9) (cid:2)(cid:28)#(cid:2)(cid:14)(cid:15)! (cid:20) (cid:29)(cid:20) 1(cid:28)(cid:8)/(cid:28)(cid:17)(cid:14)(cid:2)(cid:7) (cid:2) (cid:28)-(cid:2) (cid:7)(cid:15)(cid:17)$(cid:16)(cid:28)#(cid:14)!(cid:20) (cid:23)(cid:20) (cid:21)(cid:7)(cid:31)(cid:14)(cid:15) (cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)!(cid:2)#(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6)"(cid:2)’(cid:30)(cid:23)(cid:20)((cid:6)(cid:20) )(cid:22)*+ )(cid:28) (cid:7)(cid:8)(cid:2)(cid:21)(cid:7)(cid:31)(cid:14)(cid:15) (cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)#(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)&(cid:28)(cid:8)#(cid:2),(cid:28)(cid:16)$(cid:14)(cid:2) (cid:11)(cid:10)-(cid:15)(cid:2)-(cid:7)#(cid:11)(cid:10)$#(cid:2)#(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14) (cid:20) (cid:26)".+ (cid:26)(cid:14)%(cid:14)(cid:9)(cid:14)(cid:15)(cid:8)(cid:14)(cid:2)(cid:21)(cid:7)(cid:31)(cid:14)(cid:15) (cid:7)(cid:10)(cid:15)0(cid:2)$ $(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)-(cid:7)#(cid:11)(cid:10)$#(cid:2)#(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)0(cid:2)%(cid:10)(cid:9)(cid:2)(cid:7)(cid:15)%(cid:10)(cid:9)(cid:31)(cid:28)#(cid:7)(cid:10)(cid:15)(cid:2)(cid:12)$(cid:9)(cid:12)(cid:10) (cid:14) (cid:2)(cid:10)(cid:15)(cid:16)(cid:18)(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)-(cid:7)(cid:15)(cid:17)*(cid:4)(cid:23)(cid:27)(cid:30)(cid:3)(cid:29)* DS20001749K-page 26  2002-2013 Microchip Technology Inc.

93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2002-2013 Microchip Technology Inc. DS20001749K-page 27

93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS20001749K-page 28  2002-2013 Microchip Technology Inc.

93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2002-2013 Microchip Technology Inc. DS20001749K-page 29

93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C (cid:31)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8) (cid:18)(cid:6)(cid:10)(cid:8).(cid:10)(cid:6)(cid:12)’(cid:8)(cid:29)(cid:22)(cid:8)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:6)(cid:14),(cid:6)/(cid:5)(cid:8)(cid:23)0(cid:29)(cid:24)(cid:8)"(cid:8)(cid:26)1(cid:27)1#(23(cid:8)(cid:16)(cid:16)(cid:8)$(cid:22)(cid:7)%(cid:8)(cid:25)(cid:20) .(cid:29)(cid:28) (cid:29)(cid:22)(cid:12)(cid:5)(cid:30) .(cid:10)(cid:9)(cid:2)#(cid:11)(cid:14)(cid:2)(cid:31)(cid:10) #(cid:2)(cid:8)$(cid:9)(cid:9)(cid:14)(cid:15)#(cid:2)(cid:12)(cid:28)(cid:8)/(cid:28)(cid:17)(cid:14)(cid:2)!(cid:9)(cid:28)-(cid:7)(cid:15)(cid:17) 0(cid:2)(cid:12)(cid:16)(cid:14)(cid:28) (cid:14)(cid:2) (cid:14)(cid:14)(cid:2)#(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)1(cid:28)(cid:8)/(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)#(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)#(cid:14)!(cid:2)(cid:28)#(cid:2) (cid:11)##(cid:12)+22---(cid:20)(cid:31)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)(cid:31)2(cid:12)(cid:28)(cid:8)/(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) DS20001749K-page 30  2002-2013 Microchip Technology Inc.

93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C APPENDIX A: REVISION HISTORY Revision D (12/2003) Corrections to Section 1.0, Electrical Characteristics. Section 4.1, 6-Lead SOT-23 package to OT. Revision E (3/2005) Added DFN package. Revision F (4/2005) Added notes throughout. Revision G (5/2008) Revised Figures 2-1 through 2-4 and Figures 2-8 through 2-11; Revised Package Marking Information; Replaced Package Drawings; Revised Product ID section. Revision H (08/2010) Added 8-Lead Rotated SOIC marking information; Revised Package Drawings; Revised Product ID System. Revision J (12/2011) Added TDFN Package. Revision K (06/2013) Added E Temp to 93LC46C and 93C46C.  2002-2013 Microchip Technology Inc. DS20001749K-page 31

93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C NOTES: DS20001749K-page 32  2002-2013 Microchip Technology Inc.

93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at Users of Microchip products can receive assistance www.microchip.com. This web site is used as a means through several channels: to make files and information easily available to • Distributor or Representative customers. Accessible by using your favorite Internet • Local Sales Office browser, the web site contains the following • Field Application Engineer (FAE) information: • Technical Support • Product Support – Data sheets and errata, • Development Systems Information Line application notes and sample programs, design resources, user’s guides and hardware support Customers should contact their distributor, documents, latest software releases and archived representative or field application engineer (FAE) for software support. Local sales offices are also available to help • General Technical Support – Frequently Asked customers. A listing of sales offices and locations is Questions (FAQ), technical support requests, included in the back of this document. online discussion groups, Microchip consultant Technical support is available through the web site program member listing at: http://microchip.com/support • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions.  2002-2013 Microchip Technology Inc. DS20001749K-page 33

93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480)792-4150. Please list the following information, and use this outline to provide us with your comments about this document. TO: Technical Publications Manager Total Pages Sent ________ RE: Reader Response From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y N Device: 93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C Literature Number: DS20001749K Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS20001749K-page 34  2002-2013 Microchip Technology Inc.

93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X X X /XX X Examples: a) 93AA46C-I/P: 1K, 128x8 or 64x16 Serial Device Pinout Tape & Reel Temperature Package Lead Finish EEPROM, PDIP package, 1.8V Range b) 93AA46B-I/MS: 1K, 64x16 Serial EEPROM, MSOP package, 1.8V Device: 93AA46A: 1K 1.8V Microwire Serial EEPROM c) 93AA46AT-I/OT: 1K, 128x8 Serial EEPROM, 93AA46B: 1K 1.8V Microwire Serial EEPROM SOT-23 package, tape and reel, 1.8V 93AA46C: 1K 1.8V Microwire Serial EEPROM w/ORG d) 93AA46CT-I/SN: 1K, 128x8 or 16x16 Serial EEPROM, SOIC package, tape and reel, 1.8V 93LC46A: 1K 2.5V Microwire Serial EEPROM 93LC46B: 1K 2.5V Microwire Serial EEPROM 93LC46C: 1K 2.5V Microwire Serial EEPROM w/ORG a) 93LC46A-I/MS: 1K, 128x8 Serial EEPROM, MSOP package, 2.5V 93C46A: 1K 5.0V Microwire Serial EEPROM b) 93LC46BT-I/OT: 1K, 64x16 Serial EEPROM, 93C46B: 1K 5.0V Microwire Serial EEPROM SOT-23 package, tape and reel, 2.5V 93C46C: 1K 5.0V Microwire Serial EEPROM w/ORG c) 93LC46B-I/ST: 1K, 64x16 Serial EEPROM, TSSOP package, 2.5V Pinout: Blank = Standard pinout d) 93LC46CT-I/MNY: 1K, 128x8 or 64x16 Serial X = Rotated pinout (SOIC only) EEPROM, TDFN package, tape and reel, 2.5V Tape & Reel: Blank = Standard packaging a) 93C46B-I/MS: 1K, 64x16 Serial EEPROM, T = Tape & Reel MSOP package, 5.0V b) 93C46C-I/MS: 1K, 128x8 or 64x16 Serial EEPROM, MSOP package, 5.0V Temperature Range: I = -40°C to +85°C c) 93C46AT-I/OT: 1K, 128x8 Serial EEPROM, E = -40°C to +125°C SOT-23 package, tape and reel, 5.0V d) 93C46BX-I/SN: 1K, 64x16 Serial EEPROM, Rotated SOIC Package, 5.0V Package: MS = Plastic MSOP (Micro Small outline), 8-lead OT = Plastic SOT-23, 6-lead (Tape & Reel only) P = Plastic DIP (300 mil body), 8-lead SN = Plastic SOIC (3.9 mm body), 8-lead ST = Plastic TSSOP (4.4 mm body), 8-lead MC = Plastic DFN (2x3x0.90 mm body), 8-lead MNY(1) = Plastic TDFN (2x3x0.75 mm body), 8-lead (Tape & Reel only) Note 1: “Y” indicates a Nickel Palladium Gold (NiPdAu) finish.  2002-2013 Microchip Technology Inc. DS20001749K-page 35

93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C NOTES: DS20001749K-page 36  2002-2013 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC, and may be superseded by updates. It is your responsibility to FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, ensure that your application meets with your specifications. PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash MICROCHIP MAKES NO REPRESENTATIONS OR and UNI/O are registered trademarks of Microchip Technology WARRANTIES OF ANY KIND WHETHER EXPRESS OR Incorporated in the U.S.A. and other countries. IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, INCLUDING BUT NOT LIMITED TO ITS CONDITION, MTP, SEEVAL and The Embedded Control Solutions QUALITY, PERFORMANCE, MERCHANTABILITY OR Company are registered trademarks of Microchip Technology FITNESS FOR PURPOSE. Microchip disclaims all liability Incorporated in the U.S.A. arising from this information and its use. Use of Microchip Silicon Storage Technology is a registered trademark of devices in life support and/or safety applications is entirely at Microchip Technology Inc. in other countries. the buyer’s risk, and the buyer agrees to defend, indemnify and Analog-for-the-Digital Age, Application Maestro, BodyCom, hold harmless Microchip from any and all damages, claims, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, suits, or expenses resulting from such use. No licenses are dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, conveyed, implicitly or otherwise, under any Microchip ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial intellectual property rights. Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O, Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA and Z-Scale are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. GestIC and ULPP are registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2002-2013, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 9781620772799 QUALITY MANAGEMENT SYSTEM Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and CERTIFIED BY DNV Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures == ISO/TS 16949 == are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.  2002-2013 Microchip Technology Inc. DS20001749K-page 37

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