Low Skew, 1-to-2 85211I-01 Differential-to-HSTL Fanout Buffer PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES SEPTEMBER 7, 2016 DATASHEET GENERAL DESCRIPTION FEATURES The 85211I-01 is a low skew, high performance 1-to-2 • Two differential HSTL compatible outputs Differential-to-HSTL Fanout Buffer The CLK, nCLK pair can • One differential CLK, nCLK input pair accept most standarddifferential input levels.The 85211I-01 is characterized to operate from a 3.3V power supply. Guaranteed • CLK, nCLK pair can accept the following differential output and part-to-part skew characteristics make the 85211I-01 input levels: LVDS, LVPECL, HSTL, SSTL, HCSL ideal for those clock distribution applications demanding well • Maximum output frequency: 700MHz defi ned performance and repeatability. For optimal performance, terminate all outputs. • Translates any single-ended input signal to HSTL levels with resistor bias on nCLK input • Output skew: 30ps (maximum) • Part-to-part skew: 250ps (maximum) • Propagation delay: 1ns (maximum) • Output crossover Voltage: 0.68V to 0.9V • Output duty cycle: 49% - 51% up to 266.6MHz • V = 1.4V (maximum) OH • 3.3V operating supply • -40°C to 85°C ambient operating temperature • Available in lead-free RoHS-compliant package • For functional replacement use 8523 B D P A LOCK IAGRAM IN SSIGNMENT Q0 Q0 1 8 VDD nQ0 nQ0 2 7 CLK CLK Q1 3 6 nCLK nCLK Q1 nQ1 4 5 GND nQ1 85211I-01 8-Lead SOIC 3.90mm x 4.90mm x 1.37mm package body M Package Top View 85211I-01 REVISION B 6/12/15 1 ©2015 Integrated Device Technology, Inc.

85211I-01 DATA SHEET TABLE 1. PIN DESCRIPTIONS Number Name Type Description 1, 2 Q0, nQ0 Output Differential output pair. HSTL interface levels. 3, 4 Q1, nQ1 Output Differential output pair. HSTL interface levels. 5 GND Power Power supply ground. Pullup/ 6 nCLK Input Inverting differential clock input. V /2 default when left fl oating. Pulldown DD 7 CLK Input Pulldown Non-inverting differential clock input. 8 V Power Positive supply pin. DD NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4 pF IN R Input Pullup Resistor 51 kΩ PULLUP R Input Pulldown Resistor 51 kΩ PULLDOWN TABLE 3. CLOCK INPUT FUNCTION TABLE Inputs Outputs Input to Output Mode Polarity CLK nCLK Q0, Q1 nQ0, nQ1 0 0 LOW HIGH Differential to Differential Non Inverting 1 1 HIGH LOW Differential to Differential Non Inverting 0 Biased; NOTE 1 LOW HIGH Single Ended to Differential Non Inverting 1 Biased; NOTE 1 HIGH LOW Single Ended to Differential Non Inverting Biased; NOTE 1 0 HIGH LOW Single Ended to Differential Inverting Biased; NOTE 1 1 LOW HIGH Single Ended to Differential Inverting NOTE 1: Please refer to the Application Information section, “Wiring the Differential Input to Accept Single Ended Levels”. LOW SKEW, 1-TO-2 2 REVISION B 6/12/15 DIFFERENTIAL-TO-HSTL FANOUT BUFFER

85211I-01 DATA SHEET ABSOLUTE MAXIMUM RATINGS Supply Voltage, V 4.6V DD NOTE: Stresses beyond those listed under Absolute Inputs, V -0.5V to V + 0.5 V Maximum Ratings may cause permanent damage to the DD DD device. These ratings are stress specifi cations only. Functional Outputs, V -0.5V to V + 0.5V DD DD operation of product at these conditions or any conditions Package Thermal Impedance, θ 112.7°C/W (0 lfpm) beyond those listed in the DC Characteristics or AC Charac- JA teristics is not implied. Exposure to absolute maximum rating Storage Temperature, T -65°C to 150°C STG conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, V = 3.3V ± 5%, TA = -40°C TO 85°C DD Symbol Parameter Test Conditions Minimum Typical Maximum Units V Power Supply Voltage 3.135 3.3 3.465 V DD I Power Supply Current 22 mA DD TABLE 4B. DIFFERENTIAL DC CHARACTERISTICS, V = 3.3V ± 5%, TA = -40°C TO 85°C DD Symbol Parameter Test Conditions Minimum Typical Maximum Units nCLK V = V = 3.465V 150 µA I Input High Current DD IN IH CLK V = V = 3.465V 150 µA DD IN nCLK V = 3.465V, V = 0V -150 µA I Input Low Current DD IN IL CLK V = 3.465V, V = 0V -5 µA DD IN V Peak-to-Peak Input Voltage 0.15 1.3 V PP Common Mode Input Voltage; V 0.5 V - 0.85 V CMR NOTE 1, 2 DD NOTE 1: For single ended applications the maximum input voltage for CLK and nCLK is V + 0.3V. DD NOTE 2: Common mode voltage is defi ned as V . IH TABLE 4C. HSTL DC CHARACTERISTICS, V = 3.3V ± 5%, TA = -40°C TO 85°C DD Symbol Parameter Test Conditions Minimum Typical Maximum Units V Output High Voltage; NOTE 1 1.0 1.4 V OH V Output Low Voltage; NOTE 1 0 0.4 V OL V Output Crossover Voltage 0.68 0.9 V OX V Peak-to-Peak Output Voltage Swing 0.6 1.0 1.4 V SWING NOTE 1: All outputs must be terminated with 50Ω to ground. REVISION B 6/12/15 3 LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-HSTL FANOUT BUFFER

85211I-01 DATA SHEET TABLE 5. AC CHARACTERISTICS, V = 3.3V ± 5%, TA = -40°C TO 85°C DD Symbol Parameter Test Conditions Minimum Typical Maximum Units f Output Frequency 700 MHz MAX t Propagation Delay; NOTE 1 ƒ ≤ 600MHz 0.7 1.0 ns PD tsk(o) Output Skew; NOTE 2, 4 30 ps tsk(pp) Part-to-Part Skew; NOTE 3, 4 250 ps t / t Output Rise/Fall Time 20% to 80% 200 500 ps R F 48 52 % odc Output Duty Cycle ƒ ≤ 266.6MHz 49 51 % All parameters measured at 600MHz unless noted otherwise. The cycle-to-cycle jitter on the input will equal the jitter on the output. The part does not add jitter. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defi ned as skew between outputs at the same supply voltage and with equal load conditions. Measured at output differential cross points. NOTE 3: Defi ned as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defi ned in accordance with JEDEC Standard 65. LOW SKEW, 1-TO-2 4 REVISION B 6/12/15 DIFFERENTIAL-TO-HSTL FANOUT BUFFER

85211I-01 DATA SHEET P M I ARAMETER EASUREMENT NFORMATION 3.3V OUTPUT LOAD AC TEST CIRCUIT DIFFERENTIAL INPUT LEVEL OUTPUT SKEW PART-TO-PART SKEW OUTPUT RISE/FALL TIME PROPAGATION DELAY OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD REVISION B 6/12/15 5 LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-HSTL FANOUT BUFFER

85211I-01 DATA SHEET A I PPLICATION NFORMATION WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS Figure 1 shows how the differential input can be wired to accept of R1 and R2 might need to be adjusted to position the V_REF single ended levels. The reference voltage V_REF = V /2 is in the center of the input voltage swing. For example, if the input DD generated by the bias resistors R1, R2 and C1. This bias circuit clock swing is only 2.5V and V = 3.3V, V_REF should be 1.25V DD should be located as close as possible to the input pin. The ratio and R2/R1 = 0.609. FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT SCHEMATIC EXAMPLE Figure 2 shows a schematic example of 85211I-01. In this the power pin. For 85211I-01, the unused outputs example, the input is driven by an ICS HiPerClockS HSTL driver. need to be terminated. The decoupling capacitors should be physically located near Zo = 50 Ohm 1.8V U1 - Zo = 50 Ohm 5 4 Zo = 50 Ohm 6 GND nQ1 3 7 nCLK Q1 2 + 8 CLK nQ0 1 Zo = 50 Ohm VDD Q0 R1 R2 LVHSTL Input 50 50 LVHSTL VDD=3.3V ICS85211-01 R6 R5 C1 ICS 50 50 0.1u HiPerClockS LVHSTL Driver Unused R3 R4 Output 50 50 Need To Be Terminated FIGURE 2. 85211I-01 HSTL BUFFER SCHEMATIC EXAMPLE LOW SKEW, 1-TO-2 6 REVISION B 6/12/15 DIFFERENTIAL-TO-HSTL FANOUT BUFFER

85211I-01 DATA SHEET RECOMMENDATIONS FOR UNUSED OUTPUT PINS OUTPUTS: HSTL OUTPUT All unused HSTL outputs can be left fl oating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left fl oating or terminated. CLOCK INPUT INTERFACE The CLK /nCLK accepts differential input signals of both V the vendor of the driver components to confi rm the driver SWING and V to meet the V and V input requirements. Figures termination requirement. For example in Figure 3, the input OH PP CMR 3A to 3D show interface examples for the 85211I-01 clock termination applies for HSTL drivers. If you are using an input driven by most common driver types. The input interfaces HSTL driver from another vendor, use their termination suggested here are examples only. Please consult with recommendation. 3.3V 3.3V 3.3V 1.8V Zo = 50 Ohm Zo = 50 Ohm CLK CLK Zo = 50 Ohm Zo = 50 Ohm nCLK HiPerClockS LVPECL Input nCLK HiPerClockS LVHSTL Input R1 R2 50 50 ICS R1 R2 HiPerClockS 50 50 LVHSTL Driver R3 50 FIGURE 3A. 85211I-01 CLK/NCLK INPUT DRIVEN BY FIGURE 3B. 85211I-01 CLK/NCLK INPUT DRIVEN BY HSTL DRIVER 3.3V LVPECL DRIVER (INTERFACE 1) 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V R3 R4 R3 R4 125 125 125 125 Zo = 50 Ohm LVPECL Zo = 50 Ohm C1 CLK CLK Zo = 50 Ohm Zo = 50 Ohm C2 nCLK HiPerClockS nCLK HiPerClockS LVPECL Input Input R1 R2 R5 R6 R1 R2 84 84 100-200 100-200 84 84 R5,R6 locate near the driver pin. FIGURE 3C. 85211I-01 CLK/NCLK INPUT DRIVEN BY FIGURE 3D. 85211I-01 CLK/NCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER (INTERFACE 2) 3.3V LVPECL DRIVER WITH AC COUPLE REVISION B 6/12/15 7 LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-HSTL FANOUT BUFFER

85211I-01 DATA SHEET P C OWER ONSIDERATIONS This section provides information on power dissipation and junction temperature for the 85211I-01. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the 85211I-01 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for V = 3.3V + 5% = 3.465V, which gives worst case results. DD NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • Power (core) = V * I = 3.465V * 22mA = 76.2mW MAX DD_MAX DD_MAX • Power (outputs) = 82.34mW/Loaded Output pair MAX If all outputs are loaded, the total power is 2 * 82.34mW = 164.7mW Total Power (3.465V, with all outputs switching) = 76.2mW + 164.7mW = 240.9mW _MAX 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for the devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJAmust be used. Assuming a moderate air fl ow of 200 linear feet per minute and a multi-layer board, the appropriate value is 103.3°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.241W * 103.3°C/W = 110°C. This is well below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air fl ow, and the type of board (single layer or multi-layer). TABLE 6. THERMAL RESISTANCE θJA FOR 8-PIN SOIC, FORCED CONVECTION θ by Velocity (Linear Feet per Minute) JA 0 200 500 Single-Layer PCB, JEDEC Standard Test Boards 153.3°C/W 128.5°C/W 115.5°C/W Multi-Layer PCB, JEDEC Standard Test Boards 112.7°C/W 103.3°C/W 97.1°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. LOW SKEW, 1-TO-2 8 REVISION B 6/12/15 DIFFERENTIAL-TO-HSTL FANOUT BUFFER

85211I-01 DATA SHEET 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. HSTL output driver circuit and termination are shown in Figure 4. FIGURE 4. HSTL DRIVER CIRCUIT AND TERMINATION To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load. Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = (V /R) * (V - V ) OH_MAX L DD_MAX OH_MAX Pd_L = (V /R) * (V - V ) OL_MAX L DD_MAX OL_MAX Pd_H = (1.4V/50Ω) * (3.465V - 1.4V) = 57.82mW Pd_L = (0.4V/50Ω) * (3.465V - 0.4V) = 24.52mW Total Power Dissipation per output pair = Pd_H + Pd_L = 82.34mW REVISION B 6/12/15 9 LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-HSTL FANOUT BUFFER

85211I-01 DATA SHEET R I ELIABILITY NFORMATION θ TABLE 7. VS. AIR FLOW TABLE FOR 8 LEAD SOIC JA θ by Velocity (Linear Feet per Minute) JA 0 200 500 Single-Layer PCB, JEDEC Standard Test Boards 153.3°C/W 128.5°C/W 115.5°C/W Multi-Layer PCB, JEDEC Standard Test Boards 112.7°C/W 103.3°C/W 97.1°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for 85211I-01 is: 411 LOW SKEW, 1-TO-2 10 REVISION B 6/12/15 DIFFERENTIAL-TO-HSTL FANOUT BUFFER

85211I-01 DATA SHEET PACKAGE OUTLINE - M SUFFIX FOR 8 LEAD SOIC TABLE 8. PACKAGE DIMENSIONS Millimeters SYMBOL MINIMUM MAXIMUM N 8 A 1.35 1.75 A1 0.10 0.25 B 0.33 0.51 C 0.19 0.25 D 4.80 5.00 E 3.80 4.00 e 1.27 BASIC H 5.80 6.20 h 0.25 0.50 L 0.40 1.27 α 0° 8° Reference Document: JEDEC Publication 95, MS-012 REVISION B 6/12/15 11 LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-HSTL FANOUT BUFFER

85211I-01 DATA SHEET TABLE 9. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature 85211AMI-01LF 211AI01L 8 lead “Lead-Free” SOIC tube -40°C to 85°C 85211AMI-01LFT 211AI01L 8 lead “Lead-Free” SOIC tape & reel -40°C to 85°C LOW SKEW, 1-TO-2 12 REVISION B 6/12/15 DIFFERENTIAL-TO-HSTL FANOUT BUFFER

85211I-01 DATA SHEET REVISION HISTORY SHEET Rev Table Page Description of Change Date Throughout data sheet changed LVHSTL to HSTL. 1 2 Changed nCLK Type from V /2 to Pullup/Pulldown. A DD 7/16/03 2 2 Pin Characteristics Table - changed C 4pF max. to 4pF typical. IN Changed R to R /R , Pullup/Pulldown Resistors. PULLUP PULLUP PULLDOWN 1 Features section - added Lead Free/RoHS bullet. A 7 Added Recommendations for Unused Output Pins. 11/01/05 T9 12 Ordering Information Table - added Lead-Free part number and marking. Updated datasheet’s header/footer with IDT from ICS. B T9 12 Removed ICS prefi x from Part/Order Number column. 8/4/10 14 Added Contact Page. 1 Features Section - removed reference to leaded devices. B T9 12 Ordering Information - removed leaded devices. 6/12/15 Updated data sheet format. Product Discontinuation Notice - Last time buy expires September 7, 2016. B PDN N-16-02. 3/10/16 T9 12 Ordering Information - Deleted LF note below table. REVISION B 6/12/15 13 LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-HSTL FANOUT BUFFER

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