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7 4 L V T January 2008 H 1 2 5 — 74LVTH125 L o Low Voltage Quad Buffer with 3-STATE Outputs w V o Features General Description lt a g ■ Input and output interface capability to systems at The LVTH125 contains four independent non-inverting e 5V V buffers with 3-STATE outputs. Q CC u ■ Bushold data inputs eliminate the need for external These buffers are designed for low-voltage (3.3V) V a pull-up resistors to hold unused inputs applications, but with the capability to provide a TTCCL d B ■ Live insertion/extraction permitted interface to a 5V environment. The LVTH125 is fabri- u ■ Power Up/Down high impedance provides glitch-free cated with an advanced BiCMOS technology to achieve ff e bus loading high speed operation similar to 5V ABT while maintain- r ■ Outputs source/sink –32mA/+64mA ing a low power dissipation. w i ■ Functionally compatible with the 74 series 125 th ■ Latch-up performance exceeds 500mA 3 - ■ ESD performance: S T – Human-body model > 2000V A T – Machine model > 200V E – Charged-device model> 1000V O u t p u t s Ordering Information Package Order Number Number Package Description 74LVTH125M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 74LVTH125SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74LVTH125MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number. All packages are lead free per JEDEC: J-STD-020B standard. ©1998 Fairchild Semiconductor Corporation www.fairchildsemi.com 74LVTH125 Rev. 1.4.0

7 4 Connection Diagram Logic Symbol L V T IEEE/IEC H 1 2 5 — L o w V o l t a g e Q u a d Pin Description B Truth Table u Pin Names Description f f e An, Bn Inputs Inputs Output r w O 3-STATE Outputs A B O n n n n i t h L L L 3 L H H -S T H X Z A T H = HIGH Voltage Level E L = LOW Voltage Level O u X = Immaterial tp Z = HIGH Impedance u t s ©1998 Fairchild Semiconductor Corporation www.fairchildsemi.com 74LVTH125 Rev. 1.4.0 2

7 4 Absolute Maximum Ratings L V Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be T H operable above the recommended operating conditions and stressing the parts to these levels is not recommended. 1 In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. 2 5 The absolute maximum ratings are stress ratings only. — Symbol Parameter Rating L o V Supply Voltage –0.5V to +4.6V w CC V V DC Input Voltage –0.5V to +7.0V I o VO DC Output Voltage lta g Output in 3-STATE –0.5V to +7.0V e Output in HIGH or LOW State(1) –0.5V to +7.0V Q u I DC Input Diode Current, V < GND –50mA a IK I d IOK DC Output Diode Current, VO < GND –50mA B IO DC Output Current, VO > VCC uf f e Output at HIGH State 64mA r w Output at LOW State 128mA i t I DC Supply Current per Supply Pin ±64mA h CC 3 I DC Ground Current per Ground Pin ±128mA - GND S T Storage Temperature –65°C to +150°C T STG A T Note: E 1. I Absolute Maximum Rating must be observed. O O u t p u Recommended Operating Conditions t s The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol Parameter Min Max Units V Supply Voltage 2.7 3.6 V CC V Input Voltage 0 5.5 V I I HIGH-Level Output Current –32 mA OH I LOW-Level Output Current 64 mA OL T Free-Air Operating Temperature –40 85 °C A ∆t / ∆V Input Edge Rate, VIN = 0.8V–2.0V, VCC = 3.0V 0 10 ns/V ©1998 Fairchild Semiconductor Corporation www.fairchildsemi.com 74LVTH125 Rev. 1.4.0 3

7 4 DC Electrical Characteristics L V T T = –40°C to +85°C H A 1 Min. Typ.(2) Max. 2 5 Symbol Parameter V (V) Conditions Units — CC V Input Clamp Diode Voltage 2.7 I = –18mA –1.2 V L IK I o V Input HIGH Voltage 2.7–3.6 V ≤ 0.1V or 2.0 V w IH O VIL Input LOW Voltage 2.7–3.6 VO ≥ VCC – 0.1V 0.8 V Vo V Output HIGH Voltage 2.7–3.6 I = –100µA V – 0.2 V lt OH OH CC a 2.7 I = –8mA 2.4 g OH e 3.0 I = –32mA 2.0 Q OH u VOL Output LOW Voltage 2.7 IOL = 100µA 0.2 V a d IOL = 24mA 0.5 B 3.0 I = 16mA 0.4 u OL f f I = 32mA 0.5 e OL r I = 64mA 0.55 w OL i II(HOLD) Bushold Input Minimum Drive 3.0 VI = 0.8V 75 µA th V = 2.0V –75 3 I - S II(OD) Bushold Input Over-Drive 3.0 (3) 500 µA T A Current to Change State (4) –500 T E II Input Current 3.6 VI = 5.5V 10 µA O Control Pins 3.6 V = 0V or V ±1 u I CC t Data Pins 3.6 V = 0V –5 p I u VI = VCC 1 ts I Power Off Leakage Current 0 0V ≤ V or V ≤ 5.5V ±100 µA OFF I O I Power up/down 3-STATE 0–1.5 V = 0.5V to 3.0V, ±100 µA PU/PD O Output Current V = GND or V I CC I 3-STATE Output Leakage Current 3.6 V = 0.5V –5 µA OZL O I 3-STATE Output Leakage Current 3.6 V = 3.0V 5 µA OZH O I + 3-STATE Output Leakage Current 3.6 V < V ≤ 5.5V 10 µA OZH CC O I Power Supply Current 3.6 Outputs HIGH 0.19 mA CCH I Power Supply Current 3.6 Outputs LOW 5 mA CCL I Power Supply Current 3.6 Outputs Disabled 0.19 mA CCZ I + Power Supply Current 3.6 V ≤ V ≤ 5.5V, 0.19 mA CCZ CC O Outputs Disabled ∆I Increase in Power Supply 3.6 One Input at V – 0.6V, 0.2 mA CC CC Current(5) Other Inputs at V or CC GND Notes: 2. All typical values are at V = 3.3V, T = 25°C. CC A 3. An external driver must source at least the specified current to switch from LOW-to-HIGH. 4. An external driver must sink at least the specified current to switch from HIGH-to-LOW. 5. This is the increase in supply current for each input that is at the specified voltage level rather than V or GND. CC ©1998 Fairchild Semiconductor Corporation www.fairchildsemi.com 74LVTH125 Rev. 1.4.0 4

7 4 Dynamic Switching Characteristics(6) L V T Conditions T = 25°C H A 1 Symbol Parameter V (V) C = 50 pF, R = 500Ω Min. Typ. Max. Units 2 CC L L 5 V Quiet Output Maximum 3.3 (7) 0.8 V — OLP Dynamic V OL L VOLV Quiet Output Minimum 3.3 (7) –0.8 V ow Dynamic VOL V o Notes: l t a 6. Characterized in SOIC package. Guaranteed parameter, but not tested. g e 7. Max number of outputs defined as (n). n–1 data inputs are driven 0V to 3V. Output under test held LOW. Q u a d AC Electrical Characteristics B u TA = –40°C to +85°C, ff C = 50pF, R = 500Ω e L L r V = 3.3V ± 0.3V V = 2.7V w CC CC i t Symbol Parameter Min. Typ.(8) Max. Min. Max. Units h 3 tPLH Propagation Delay, Data to Output 1.0 3.5 1.0 4.5 ns -S T tPHL 1.0 3.9 1.0 4.9 A T tPZH Output Enable Time 1.0 4.0 1.0 5.5 ns E t 1.1 4.0 1.1 5.4 O PZL u t Output Disable Time 1.5 4.5 1.5 5.7 ns t PHZ p u t 1.3 4.5 1.3 4.0 PLZ t s t , t Output to Output Skew(9) 1.0 1.0 ns OSHL OSLH Notes: 8. All typical values are at V = 3.3V, T = 25°C. CC A 9. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t ) or LOW-to-HIGH (t ). OSHL OSLH Capacitance(10) Symbol Parameter Conditions Typical Units C Input Capacitance V = 0V, V = 0V or V 4 pF IN CC I CC C Output Capacitance V = 3.0V, V = 0V or V 8 pF OUT CC O CC Note: 10.Capacitance is measured at frequency f = 1MHz, per MIL-STD-883B, Method 3012. ©1998 Fairchild Semiconductor Corporation www.fairchildsemi.com 74LVTH125 Rev. 1.4.0 5

0.65 (cid:24)(cid:17)(cid:19)(cid:19)(cid:147)(cid:19)(cid:17)(cid:20)(cid:19) A 0.43TYP 14 8 B 6.4 (cid:23)(cid:17)(cid:23)(cid:19)(cid:147)(cid:19)(cid:17)(cid:20)(cid:19) 6.10 3.2 1.65 1 7 0.2 C B A PIN1IDENT TOPVIEW ALLLEADTIPS 0.45 RECOMMENDEDLANDPATTERN 1.2MAX SEEDETAILA +0.15 0.90 -0.10 0.20 (cid:19)(cid:17)(cid:20)(cid:19)(cid:147)(cid:19)(cid:17)(cid:19)(cid:24) 0.09 ALLLEADTIPS 0.30 0.19 C 0.1 C 0.65 0.13 A B C (cid:20)(cid:21)(cid:17)(cid:19)(cid:19)(cid:131)(cid:3)(cid:55)(cid:50)(cid:51)(cid:3)(cid:9)(cid:3)(cid:37)(cid:50)(cid:55)(cid:55)(cid:50)(cid:48) FRONTVIEW 0.09MIN NOTES: GAGEPLANE A.CONFORMSTOJEDECREGISTRATIONMO-153, VARIATIONAB,REFNOTE6 B.DIMENSIONSAREINMILLIMETERS. 0.25 0.09MIN C.DIMENSIONSAREEXCLUSIVEOFBURRS, (cid:19)(cid:131)(cid:16)(cid:3)(cid:27)(cid:131) (cid:19)(cid:17)(cid:25)(cid:147)(cid:19)(cid:17)(cid:20) MOLDFLASH,ANDTIEBAREXTRUSIONS SEATINGPLANE 1.00 D.DIMENSIONINGANDTOLERANCESPERANSI DETAILA Y14.5M,2009. E.LANDPATTERNSTANDARD:SOP65P640X110-14M. F.DRAWINGFILENAME:MKT-MTC14rev7.

8.75 A 8.50 7.62 14 0.65 8 14 8 B 4.00 6.00 5.60 3.80 1.70 1 7 PIN #1 1.27 0.51 1 7 IDENT. 1.27 0.35 (0.33) 0.25 M C B A LAND PATTERN RECOMMENDATION TOP VIEW 1.75 MAX A C 0.25 0.19 1.50 0.10 C 0.25 1.25 0.10 SIDE VIEW FRONT VIEW NOTES: A. CONFORMS TO JEDEC MS-012, VARIATION AB, ISSUE C B. ALL DIMENSIONS ARE IN MILLIMETERS 0.50 0.25 x 45 C. DIMENSIONS DO NOT INCLUDE MOLD FLASH OR BURRS R0.10 GAGE D. LAND PATTERN STANDARD: PLANE SOIC127P600X145-14M R0.10 E. CONFORMS TO ASME Y14.5M, 2009 0.36 D. DRAWING FILENAME: MKT-M14Arev14 8° 0° 0.90 0.50 SEATING PLANE (1.04) DETAIL A SCALE 16 : 1

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Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: O N Semiconductor: 74LVTH125MTC 74LVTH125MX 74LVTH125M 74LVTH125MTCX 74LVTH125SJ