74LVT574; 74LVTH574 3.3 V octal D-type flip-flop; 3-state Rev. 7 — 22 November 2011 Product data sheet 1. General description The 74LVT574; 74LVTH574 is a high-performance product designed for V operation at CC 3.3V. This device is an 8-bit, edge triggered register coupled to eight 3-state output buffers. The two sections of the device are controlled independently by the clock (pin CP) and output enable (pin OE) control gates. The state of each Dn input (one setup time before the LOW-to-HIGH clock transition) is transferred to the corresponding flip-flopsQn output. The 3-state output buffers are designed to drive heavily loaded 3-state buses, MOS memories, or MOS microprocessors. The active LOW output enable (pin OE) controls all eight 3-state buffers independent of the clock operation. When pin OE is LOW, the stored data appears at the outputs. When pin OE is HIGH, the outputs are in the high-impedance OFF-state, which means they will neither drive nor load the bus. 2. Features and benefits  Inputs and outputs arranged for easy interfacing to microprocessors  3-state outputs for bus interfacing  Common output enable control  TTL input and output switching levels  Input and output interface capability to systems at 5V supply  Bus hold data inputs eliminate need for external pull-up resistors to hold unused inputs  Live insertion and extraction permitted  No bus current loading when output is tied to 5V bus  Power-up reset  Power-up 3-state  Latch-up protection JESD78 class II exceeds 500 mA  ESD protection: HBM JESD22-A114E exceeds 2000V MM JESD22-A115-A exceeds 200V  Specified from 40 C to +85 C

74LVT574; 74LVTH574 NXP Semiconductors 3.3 V octal D-type flip-flop; 3-state 3. Ordering information Table 1. Ordering info rmation Type number Package Temperature range Name Description Version 74LVT574D 40C to +85C SO20 plastic small outline package; 20leads; SOT163-1 bodywidth7.5mm 74LVTH574D 74LVT574DB 40C to +85C SSOP20 plastic shrink small outline package; 20leads; SOT339-1 bodywidth5.3mm 74LVTH574DB 74LVT574PW 40C to +85C TSSOP20 plastic thin shrink small outline package; 20leads; SOT360-1 bodywidth 4.4mm 74LVTH574PW 74LVT574BQ 40Cto+85C DHVQFN20 plastic dual in-line compatible thermal enhanced very SOT764-1 thin quad flat package; no leads; 20terminals; body2.54.50.85mm 4. Functional diagram 1 EN2 11 11 C1 CP 2 19 D0 Q0 2 19 3 18 1D 2 D1 Q1 4 17 3 18 D2 Q2 5 D3 Q3 16 4 17 6 15 D4 Q4 5 16 7 14 D5 Q5 6 15 8 13 D6 Q6 9 12 7 14 D7 Q7 OE 8 13 1 mna798 9 12 001aae466 Fig 1. Logic symbol Fig 2. IEC logic symbol D0 D1 D2 D3 D4 D5 D6 D7 D D D D D D D D CP Q CP Q CP Q CP Q CP Q CP Q CP Q CP Q CP OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 001aae467 Fig 3. Logic diagram 74LVT_LVTH574 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 7 — 22 November 2011 2 of 17

74LVT574; 74LVTH574 NXP Semiconductors 3.3 V octal D-type flip-flop; 3-state 5. Pinning information 5.1 Pinning 74LVT574 74LVTH574 terminal 1 E CC index area O V 74LVT574 1 20 74LVTH574 D0 2 19 Q0 D1 3 18 Q1 OE 1 20 VCC D2 4 17 Q2 D0 2 19 Q0 D1 3 18 Q1 D3 5 16 Q3 D2 4 17 Q2 D4 6 15 Q4 D3 5 16 Q3 D5 7 14 Q5 D4 6 15 Q4 D6 8 GND(1) 13 Q6 D5 7 14 Q5 D7 9 12 Q7 D6 8 13 Q6 0 1 1 1 D7 9 12 Q7 D P GND 10 11 CP N C 001aah711 G 001aae758 Transparent top view (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input Fig 4. Pin configuration for SO20, and (T)SSOP20 Fig 5. Pin configuration for DHVQFN20 5.2 Pin description Table 2. Pin descripti on Symbol Pin Description OE 1 output enable input (active LOW) D0 to D7 2, 3, 4, 5, 6, 7, 8, 9 data input GND 10 ground (0V) CP 11 clock pulse input (active rising edge) Q0 to Q7 19, 18, 17, 16, 15, 14, 13, 12 data output V 20 supply voltage CC 74LVT_LVTH574 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 7 — 22 November 2011 3 of 17

74LVT574; 74LVTH574 NXP Semiconductors 3.3 V octal D-type flip-flop; 3-state 6. Functional description 6.1 Function table Table 3. Function tab le [1] Operating mode Control Input Internal register Output OE CP Dn Qn Load and read register L  l L L h H H Hold L NC X NC NC Disable outputs H L or H X NC Z  Dn Dn Z [1] H = HIGH voltage level; L = LOW voltage level;  = LOW-to-HIGH clock transition; h = HIGH voltage level one setup time prior to the LOW-to-HIGH clock transition; l = LOW voltage level one setup time prior to the LOW-to-HIGH clock transition; Z = high-impedance OFF-state; NC = no change; X = don’t care. 7. Limiting values Table 4. Limiting valu es In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit V supply voltage 0.5 +4.6 V CC V input voltage [1] 0.5 +7.0 V I V output voltage output in OFF-state or HIGH-state [1] 0.5 +7.0 V O I input clamping current V <0V - 50 mA IK I I output clamping current V <0V - 50 mA OK O I output current output in LOW-state - 128 mA O output in HIGH-state - 64 mA T storage temperature 65 +150 C stg T junction temperature [2] - 150 C j P total power dissipation T = 40 C to +85 C [3] - 500 mW tot amb [1] The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. [2] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. [3] For SO20 packages: above 70 C derate linearly with 8 mW/K. For SSOP20 and TSSOP20 packages: above 60 C derate linearly with 5.5 mW/K. For DHVQFN20 packages: above 60 C derate linearly with 4.5 mW/K. 74LVT_LVTH574 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 7 — 22 November 2011 4 of 17

74LVT574; 74LVTH574 NXP Semiconductors 3.3 V octal D-type flip-flop; 3-state 8. Recommended operating conditions Table 5. Recommend ed operating conditions Symbol Parameter Conditions Min Max Unit V supply voltage 2.7 3.6 V CC V input voltage 0 5.5 V I V HIGH-level input voltage 2.0 - V IH V LOW-level input voltage - 0.8 V IL I HIGH-level output current - 32 mA OH I LOW-level output current - 32 mA OL current duty cycle 50%; f 1kHz - 64 mA i T ambient temperature in free air 40 +85 C amb t/V input transition rise and fall rate outputs enabled - 10 ns/V 9. Static characteristics Table 6. Static charac teristics At recommended operating conditions; voltages are referenced to GND (ground=0V). Symbol Parameter Conditions T =40C to +85C Unit amb Min Typ[1] Max V input clamping voltage V = 2.7V; I =18mA 1.2 0.9 - V IK CC IK V HIGH-level output voltage V =2.7Vto3.6V; I =100A V  0.2 V  0.1 - V OH CC OH CC CC V = 2.7V; I =8mA 2.4 2.5 - V CC OH V = 3.0V; I =32mA 2.0 2.2 - V CC OH V LOW-level output voltage V = 2.7V OL CC I =100A - 0.1 0.2 V OL I =24mA - 0.3 0.5 V OL V = 3.0V CC I =16mA - 0.25 0.4 V OL I =32mA - 0.3 0.5 V OL I =64mA - 0.4 0.55 V OL V power-up LOW-level V = 3.6 V; I =1mA; V =GNDorV [2] - 0.13 0.55 V OL(pu) CC O I CC outputvoltage I input leakage current all input pins; V = 0V or 3.6V; V =5.5V - 1 10 A I CC I control pins; V = 3.6V; V = V or GND - 0.1 1 A CC I CC data pins; V =3.6V [3] CC V =V - 0.1 1 A I CC V =0V 5 1 - A I I power-off leakage current V = 0V; V or V =0V to 4.5V - 1 100 A OFF CC I O I output leakage current V =5.5V and V =3.0V; output HIGH [4] - 60 125 A LO O CC I bus hold LOW current V = 3.0 V; V =0.8V 75 150 - A BHL CC I I bus hold HIGH current V = 3.0 V; V =2.0V [4] - 150 75 A BHH CC I I bus hold HIGH V =3.6 V; V = 0 V to 3.6V [4] - - 500 A BHHO CC I overdrivecurrent 74LVT_LVTH574 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 7 — 22 November 2011 5 of 17

74LVT574; 74LVTH574 NXP Semiconductors 3.3 V octal D-type flip-flop; 3-state Table 6. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground=0V). Symbol Parameter Conditions T =40C to +85C Unit amb Min Typ[1] Max I bus hold LOW V =3.6 V; V = 0 V to 3.6V 500 - - A BHLO CC I overdrivecurrent I power-up/power-down V 1.2V; V =0.5Vto V ; [5] - 1 100 A O(pu/pd) CC O CC output current V =GNDorV ; OE=don’tcare I CC I OFF-state output current V =3.6V; V =V orV OZ CC I IH IL output HIGH: V =3.0V - 1 5 A O output LOW: V =0.5V 5 1 - A O I supply current V =3.6V; V =GNDorV ; I =0A CC CC I CC O outputs HIGH - 0.13 0.19 mA outputs LOW - 3 12 mA outputs disabled [6] - 0.13 0.19 mA I additional supply current per input pin; V =3V to 3.6V; one input [7] - 0.1 0.2 mA CC CC at V 0.6V and other inputs at V or CC CC GND C input capacitance V = 0V or 3.0V - 4 - pF I I C output capacitance outputs disabled; V = 0V or 3.0V - 8 - pF O O [1] Typical values are measured at VCC=3.3V and Tamb=25 C. [2] For valid test results, data must not be loaded into the flip-flops (or latches) after applying power. [3] Unused pins at V or GND. CC [4] This is the bus hold overdrive current required to force the input to the opposite logic state. [5] This parameter is valid for any VCC between 0V and 1.2V with a transition time of up to 10ms. From VCC=1.2V to VCC=3.3 V 0.3V a transition time of 100s is permitted. This parameter is valid for Tamb=25C only. [6] I is measured with outputs pulled to V or GND. CC CC [7] This is the increase in supply current for each input at the specified voltage level other than V or GND. CC 10. Dynamic characteristics Table 7. Dynamic cha racteristics Voltages are referenced to ground (GND=0V); for test circuit see Figure10. Symbol Parameter Conditions T =40C to +85C Unit amb Min Typ[1] Max t LOW to HIGH propagation delay CP to Qn; see Table6 PLH V =3.0 V to 3.6 V 1.7 3.6 5.4 ns CC V =2.7V - - 6.2 ns CC t HIGH to LOW propagation delay CP to Qn; see Table6 PHL V =3.0 V to 3.6 V 2.4 4.3 5.9 ns CC V =2.7V - - 6.6 ns CC t OFF-state to HIGH propagation delay OE to Qn; see Figure7 PZH V =3.0 V to 3.6 V 1.0 2.9 4.8 ns CC V =2.7V - - 5.9 ns CC 74LVT_LVTH574 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 7 — 22 November 2011 6 of 17

74LVT574; 74LVTH574 NXP Semiconductors 3.3 V octal D-type flip-flop; 3-state Table 7. Dynamic characteristics …continued Voltages are referenced to ground (GND=0V); for test circuit see Figure10. Symbol Parameter Conditions T =40C to +85C Unit amb Min Typ[1] Max t OFF-state to LOW propagation delay OE to Qn; see Figure8 PZL V =3.0 V to 3.6 V 1.3 3.4 5.1 ns CC V =2.7V - - 6.2 ns CC t HIGH to OFF-state propagation delay OE to Qn; see Figure7 PHZ V =3.0 V to 3.6 V 1.9 4.0 5.5 ns CC V =2.7V - - 5.9 ns CC t LOW to OFF-state propagation delay OE to Qn; see Figure8 PLZ V =3.0 V to 3.6 V 1.7 3.2 4.5 ns CC V =2.7V - - 4.5 ns CC t set-up time Dn to CP; see Figure9 [2] su V =3.0 V to 3.6 V 2.0 - - ns CC V =2.7V 2.4 - - ns CC t hold time Dn to CP; see Figure9 [3] h V =3.0 V to 3.6 V 0.3 - - ns CC V =2.7V 0 - - ns CC t pulse width CP input; see Figure6 [4] W V =3.0 V to 3.6 V 3.3 - - ns CC V =2.7V 3.3 - - ns CC f maximum frequency CP input; V =3.0 V to 3.6 V; 150 - - MHz max CC seeFigure6 [1] Typical values are at VCC=3.3V and Tamb=25 C. [2] t is the same as t and t su su(H) su(L) [3] t is the same as t and t h h(H) h(L) [4] t is the same as t and t W WH WL 74LVT_LVTH574 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 7 — 22 November 2011 7 of 17

74LVT574; 74LVTH574 NXP Semiconductors 3.3 V octal D-type flip-flop; 3-state 11. Waveforms 1 / fmax VI CP input VM GND tWH tWL tPHL tPLH VOH Qn output VM VOL 001aac445 Measurement points are given in Table8 V and V are typical voltage output levels that occur with the output load. OL OH Fig 6. Propagation delay clock input (CP) to output (Qn), pulse width clock (CP) and maximum clock frequency VI VI OE input VM VM OE input VM VM GND GND tPZH tPHZ tPZL tPLZ VOH 3.0 V Qn output VM VY Qn output VM VX GND VOL 001aae468 001aae469 Measurement points are given in Table8 Measurement points are given in Table8 V and V are typical voltage output levels that occur V and V are typical voltage output levels that occur OL OH OL OH with the output load. with the output load. Fig 7. Output enable time to HIGH-state and output Fig 8. Output enable time to LOW-state and output disable time from HIGH-state disable time from LOW-state Vl Dn input VM VM VM VM GND tsu(H) th(H) tsu(L) th(L) Vl CP input VM VM GND 001aac738 Measurement points are given in Table8 Remark: The shaded areas indicate when the input is permitted to change for predictable output performance. Fig 9. Data setup and hold times 74LVT_LVTH574 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 7 — 22 November 2011 8 of 17

74LVT574; 74LVTH574 NXP Semiconductors 3.3 V octal D-type flip-flop; 3-state Table 8. Measuremen t points Input Output V V V V M M X Y 1.5V 1.5V V + 0.3V V  0.3V OL OH tW VI 90 % negative pulse VM VM 10 % 0 V tf tr tr tf VI 90 % positive pulse VM VM 10 % 0 V tW VEXT VCC RL VI VO PULSE DUT GENERATOR RT CL RL 001aae235 Test data is given in Table9. Definitions test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. R = Termination resistance should be equal to output impedance Z of the pulse generator. T o VEXT = Test voltage for switching times. Fig 10. Load circuitry for switching times Table 9. Test data Input Load V EXT V f t t, t C R t , t t , t t , t I i W r f L L PHZ PZH PLZ PZL PLH PHL 2.7V  10 MHz 500 ns  2.5 ns 50 pF 500  GND 6V open 74LVT_LVTH574 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 7 — 22 November 2011 9 of 17

74LVT574; 74LVTH574 NXP Semiconductors 3.3 V octal D-type flip-flop; 3-state 12. Package outline SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 D E A X c y HE v M A Z 20 11 Q A2 A A1 (A 3 ) pin 1 index θ Lp L 1 10 detail X e w M bp 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mAax. A1 A2 A3 bp c D(1) E(1) e HE L Lp Q v w y Z(1) θ 0.3 2.45 0.49 0.32 13.0 7.6 10.65 1.1 1.1 0.9 mm 2.65 0.25 1.27 1.4 0.25 0.25 0.1 0.1 2.25 0.36 0.23 12.6 7.4 10.00 0.4 1.0 0.4 8o 0.012 0.096 0.019 0.013 0.51 0.30 0.419 0.043 0.043 0.035 0o inches 0.1 0.01 0.05 0.055 0.01 0.01 0.004 0.004 0.089 0.014 0.009 0.49 0.29 0.394 0.016 0.039 0.016 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE REFERENCES EUROPEAN ISSUE DATE VERSION IEC JEDEC JEITA PROJECTION 99-12-27 SOT163-1 075E04 MS-013 03-02-19 Fig 11. Package outline SOT163-1 (SO20) 74LVT_LVTH574 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 7 — 22 November 2011 10 of 17

74LVT574; 74LVTH574 NXP Semiconductors 3.3 V octal D-type flip-flop; 3-state SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm SOT339-1 D E A X c y HE v M A Z 20 11 Q A2 A A1 (A 3 ) pin 1 index θ Lp L 1 10 detail X w M e bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT mAax. A1 A2 A3 bp c D(1) E(1) e HE L Lp Q v w y Z(1) θ mm 2 00..2015 11..8605 0.25 00..3285 00..2009 77..40 55..42 0.65 77..96 1.25 10..0633 00..97 0.2 0.13 0.1 00..95 80oo Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. OUTLINE REFERENCES EUROPEAN ISSUE DATE VERSION IEC JEDEC JEITA PROJECTION 99-12-27 SOT339-1 MO-150 03-02-19 Fig 12. Package outline SOT339-1 (SSOP20) 74LVT_LVTH574 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 7 — 22 November 2011 11 of 17

74LVT574; 74LVTH574 NXP Semiconductors 3.3 V octal D-type flip-flop; 3-state TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 D E A X c y HE v M A Z 20 11 Q A2 (A 3 ) A pin 1 index A1 θ Lp L 1 10 detail X w M e bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT mAax. A1 A2 A3 bp c D(1) E(2) e HE L Lp Q v w y Z(1) θ mm 1.1 00..1055 00..9850 0.25 00..3109 00..21 66..64 44..53 0.65 66..62 1 00..7550 00..43 0.2 0.13 0.1 00..52 80oo Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE REFERENCES EUROPEAN ISSUE DATE VERSION IEC JEDEC JEITA PROJECTION 99-12-27 SOT360-1 MO-153 03-02-19 Fig 13. Package outline SOT360-1 (TSSOP20) 74LVT_LVTH574 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 7 — 22 November 2011 12 of 17

74LVT574; 74LVTH574 NXP Semiconductors 3.3 V octal D-type flip-flop; 3-state DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 20 terminals; body 2.5 x 4.5 x 0.85 mm SOT764-1 D B A A A1 E c terminal 1 detail X index area terminal 1 e1 C index area e b v M C A B y1 C y w M C 2 9 L 1 10 Eh e 20 11 19 12 Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) A(1) UNIT max. A1 b c D(1) Dh E(1) Eh e e1 L v w y y1 0.05 0.30 4.6 3.15 2.6 1.15 0.5 mm 1 0.2 0.5 3.5 0.1 0.05 0.05 0.1 0.00 0.18 4.4 2.85 2.4 0.85 0.3 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE REFERENCES EUROPEAN ISSUE DATE VERSION IEC JEDEC JEITA PROJECTION 02-10-17 SOT764-1 - - - MO-241 - - - 03-01-27 Fig 14. Package outline SOT764-1 (DHVQFN20) 74LVT_LVTH574 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 7 — 22 November 2011 13 of 17

74LVT574; 74LVTH574 NXP Semiconductors 3.3 V octal D-type flip-flop; 3-state 13. Abbreviations Table 10. Abbreviation s Acronym Description DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model MOS Metal Oxide Semiconductor TTL Transistor-Transistor Logic 14. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74LVT_LVTH574 v.7 20111122 Product data sheet - 74LVT_LVTH574 v.6 Modifications: • Legal pages updated. 74LVT_LVTH574 v.6 20110912 Product data sheet - 74LVT_LVTH574 v.5 74LVT_LVTH574 v.5 20110727 Product data sheet - 74LVT_LVTH574 v.4 74LVT_LVTH574 v.4 20080911 Product data sheet - 74LVT_LVTH574 v.3 74LVT_LVTH574 v.3 20060323 Product data sheet - 74LVT574 v.2 74LVT574 v.2 19980219 product specification - 74LVT574 v.1 74LVT574 v.1 19951114 product specification - - 74LVT_LVTH574 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 7 — 22 November 2011 14 of 17

74LVT574; 74LVTH574 NXP Semiconductors 3.3 V octal D-type flip-flop; 3-state 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. 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Constant or In no event shall NXP Semiconductors be liable for any indirect, incidental, repeated exposure to limiting values will permanently and irreversibly affect punitive, special or consequential damages (including - without limitation - lost the quality and reliability of the device. profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such Terms and conditions of commercial sale — NXP Semiconductors damages are based on tort (including negligence), warranty, breach of products are sold subject to the general terms and conditions of commercial contract or any other legal theory. sale, as published at http://www.nxp.com/profile/terms, unless otherwise Notwithstanding any damages that customer might incur for any reason agreed in a valid written individual agreement. In case an individual whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards agreement is concluded only the terms and conditions of the respective customer for the products described herein shall be limited in accordance agreement shall apply. NXP Semiconductors hereby expressly objects to with the Terms and conditions of commercial sale of NXP Semiconductors. applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without No offer to sell or license — Nothing in this document may be interpreted or limitation specifications and product descriptions, at any time and without construed as an offer to sell products that is open for acceptance or the grant, notice. This document supersedes and replaces all information supplied prior conveyance or implication of any license under any copyrights, patents or to the publication hereof. other industrial or intellectual property rights. Suitability for use — NXP Semiconductors products are not designed, Export control — This document as well as the item(s) described herein authorized or warranted to be suitable for use in life support, life-critical or may be subject to export control regulations. Export might require a prior safety-critical systems or equipment, nor in applications where failure or authorization from competent authorities. 74LVT_LVTH574 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 7 — 22 November 2011 15 of 17

74LVT574; 74LVTH574 NXP Semiconductors 3.3 V octal D-type flip-flop; 3-state Non-automotive qualified products — Unless this data sheet expressly NXP Semiconductors’ specifications such use shall be solely at customer’s states that this specific NXP Semiconductors product is automotive qualified, own risk, and (c) customer fully indemnifies NXP Semiconductors for any the product is not suitable for automotive use. It is neither qualified nor tested liability, damages or failed product claims resulting from customer design and in accordance with automotive testing or application requirements. NXP use of the product for automotive applications beyond NXP Semiconductors’ Semiconductors accepts no liability for inclusion and/or use of standard warranty and NXP Semiconductors’ product specifications. non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in 15.4 Trademarks automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the Notice: All referenced brands, product names, service names and trademarks product for such automotive applications, use and specifications, and (b) are the property of their respective owners. whenever customer uses the product for automotive applications beyond 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com 74LVT_LVTH574 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 7 — 22 November 2011 16 of 17

74LVT574; 74LVTH574 NXP Semiconductors 3.3 V octal D-type flip-flop; 3-state 17. Contents 1 General description. . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Functional description . . . . . . . . . . . . . . . . . . . 4 6.1 Function table. . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 8 Recommended operating conditions. . . . . . . . 5 9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 10 Dynamic characteristics. . . . . . . . . . . . . . . . . . 6 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 12 Package outline. . . . . . . . . . . . . . . . . . . . . . . . 10 13 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 14 14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 14 15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 15 15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15 15.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 15.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 15 15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 16 16 Contact information. . . . . . . . . . . . . . . . . . . . . 16 17 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2011. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 22 November 2011 Document identifier: 74LVT_LVTH574