Is Now Part of To learn more about ON Semiconductor, please visit our website at www.onsemi.com Please note: As part of the Fairchild Semiconductor integration, some of the Fairchild orderable part numbers will need to change in order to meet ON Semiconductor’s system requirements. Since the ON Semiconductor product management systems do not have the ability to manage part nomenclature that utilizes an underscore (_), the underscore (_) in the Fairchild part numbers will be changed to a dash (-). This document may contain device numbers with an underscore (_). Please check the ON Semiconductor website to verify the updated device numbers. The most current and up-to-date ordering information can be found at www.onsemi.com. Please email any questions regarding the system integration to Fairchild_questions@onsemi.com. ON Semiconductor and the ON Semiconductor logo are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

7 4 L V T January 2008 5 7 3 , 7 4 74LVT573, 74LVTH573 L V T Low Voltage Octal Transparent Latch with 3-STATE Outputs H 5 7 3 Features General Description — ■ Input and output interface capability to systems at The LVT573 and LVTH573 consist of eight latches L 5V V with 3-STATE outputs for bus organized system applica- o CC w ■ Bushold data inputs eliminate the need for external tions. The latches appear transparent to the data when V pull-up resistors to hold unused inputs (74LVTH573), Latch Enable (LE) is HIGH. When LE is low, the data o also available without bushold feature (74LVT573) satisfying the input timing requirements is latched. Data lt a ■ Live insertion/extraction permitted appears on the bus when the Output Enable (OE) is g LOW. When OE is HIGH, the bus output is in the high e ■ Power Up/Down high impedance provides glitch-free O impedance state. bus loading c t ■ Outputs source/sink –32mA/+64mA The LVTH573 data inputs include bushold, eliminating a l ■ Functionally compatible with the 74 series 573 the need for external pull-up resistors to hold unused Tr inputs. a ■ Latch-up performance exceeds 500mA n These octal latches are designed for low-voltage (3.3V) s ■ ESD performance: p – Human-body model > 2000V VCC applications, but with the capability to provide a TTL a interface to a 5V environment. The LVT573 and re – Machine model > 200V LVTH573 are fabricated with an advanced BiCMOS n – Charged-device model > 1000V technology to achieve high speed operation similar to 5V t L ABT while maintaining a low power dissipation. a t c h w i Ordering Information th 3 Package - S Order Number Number Package Description T A 74LVT573WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide T E 74LVT573SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide O u 74LVT573MSA MSA20 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide t p 74LVT573MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm u t Wide s 74LVTH573WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 74LVTH573SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74LVTH573MSA MSA20 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide 74LVTH573MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number. All packages are lead free per JEDEC: J-STD-020B standard. ©1999 Fairchild Semiconductor Corporation www.fairchildsemi.com 74LVT573, 74LVTH573 Rev. 1.7.0

7 4 Connection Diagram Logic Symbols L V T 5 7 3 , 7 4 L V T H 5 7 3 — IEEE/IEC L o w V o l t a g e O Pin Description c t a l Pin Names Description T r a D0–D7 Data Inputs n s LE Latch Enable Input p a OE Output Enable Input r e n O –O 3-STATE Latch Outputs 0 7 t L a t c Functional Description Truth Table h w The LVT573 and LVTH573 contain eight D-type latches Inputs Outputs i t with 3-STATE standard outputs. When the Latch Enable h LE OE D O n n 3 (LE) input is HIGH, data on the D inputs enters the n - latches. In this condition the latches are transparent, i.e., X H X Z S T a latch output will change state each time its D-type input H L L L A T changes. When LE is LOW, the latches store the infor- H L H H E mation that was present on the D-type inputs a setup O time preceding the HIGH-to-LOW transition of LE. The L L X O0 u 3-STATE standard outputs are controlled by the Output H = HIGH Voltage Level tp Enable (OE) input. When OE is LOW, the standard out- u puts are in the 2-state mode. When OE is HIGH, the L = LOW Voltage Level ts standard outputs are in the high impedance mode but Z = High Impedance this does not interfere with entering new data into the X = Immaterial latches. O = Previous O before HIGH to LOW transition 0 0 of Latch Enable ©1999 Fairchild Semiconductor Corporation www.fairchildsemi.com 74LVT573, 74LVTH573 Rev. 1.7.0 2

7 4 Logic Diagram L V T 5 7 3 , 7 4 L V T H 5 7 3 — L o w V o l t a g e O c Please note that this diagram is provided only for the understanding of logic operations and should not be used to ta estimate propagation delays. l T r a n s p a r e n t L a t c h w i t h 3 - S T A T E O u t p u t s ©1999 Fairchild Semiconductor Corporation www.fairchildsemi.com 74LVT573, 74LVTH573 Rev. 1.7.0 3

7 4 Absolute Maximum Ratings L V Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be T 5 operable above the recommended operating conditions and stressing the parts to these levels is not recommended. 7 3 In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. , The absolute maximum ratings are stress ratings only. 7 4 L Symbol Parameter Rating V T V Supply Voltage –0.5V to +4.6V H CC 5 V DC Input Voltage –0.5V to +7.0V 7 I 3 VO DC Output Voltage — Output in 3-STATE –0.5V to +7.0V L o Output in HIGH or LOW State(1) –0.5V to +7.0V w I DC Input Diode Current, V < GND –50mA V IK I o IOK DC Output Diode Current, VO < GND –50mA lta I DC Output Current, V > V g O O CC e Output at HIGH State 64mA O c Output at LOW State 128mA t a l ICC DC Supply Current per Supply Pin ±64mA T r I DC Ground Current per Ground Pin ±128mA a GND n T Storage Temperature –65°C to +150°C s STG p a Note: r e 1. I Absolute Maximum Rating must be observed. n O t L a t Recommended Operating Conditions c h The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended w operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not it h recommend exceeding them or designing to absolute maximum ratings. 3 - Symbol Parameter Min Max Units S T V Supply Voltage 2.7 3.6 V A CC T V Input Voltage 0 5.5 V E I O IOH HIGH-Level Output Current –32 mA u t I LOW-Level Output Current 64 mA p OL u TA Free-Air Operating Temperature –40 85 °C ts ∆t / ∆V Input Edge Rate, VIN = 0.8V–2.0V, VCC = 3.0V 0 10 ns/V ©1999 Fairchild Semiconductor Corporation www.fairchildsemi.com 74LVT573, 74LVTH573 Rev. 1.7.0 4

7 4 DC Electrical Characteristics L V T T = –40°C to +85°C 5 A 7 Symbol Parameter V (V) Conditions Min. Typ.(2) Max. Units 3 CC , 7 VIK Input Clamp Diode Voltage 2.7 II = –18mA –1.2 V 4 L V Input HIGH Voltage 2.7–3.6 V ≤ 0.1V or 2.0 V V IH O VIL Input LOW Voltage 2.7–3.6 VO ≥ VCC – 0.1V 0.8 V TH 5 VOH Output HIGH Voltage 2.7–3.6 IOH = –100µA VCC – 0.2 V 7 3 2.7 IOH = –8mA 2.4 — 3.0 I = –32mA 2.0 OH L V Output LOW Voltage 2.7 I = 100µA 0.2 V o OL OL w IOL = 24mA 0.5 V o 3.0 I = 16mA 0.4 l OL t a I = 32mA 0.5 g OL e IOL = 64mA 0.55 O I (3) Bushold Input Minimum 3.0 V = 0.8V 75 µA c I(HOLD) I t Drive V = 2.0V –75 al I T II(OD)(3) Bushold Input Over-Drive 3.0 (4) 500 µA ra Current to Change State (5) –500 ns p II Input Current 3.6 VI = 5.5V 10 µA a r Control Pins 3.6 V = 0V or V ±1 e I CC n Data Pins 3.6 VI = 0V –5 t L V = V 1 a I CC t c IOFF Power Off Leakage Current 0 0V ≤ VI or VO ≤ 5.5V ±100 µA h I Power up/down 3-STATE 0–1.5 V = 0.5V to 3.0V, ±100 µA w PU/PD O i Output Current VI = GND or VCC th I 3-STATE Output Leakage 3.6 V = 0.5V –5 µA 3 OZL O - Current S T I 3-STATE Output Leakage 3.6 V = 3.0V 5 µA A OZH O T Current E I + 3-STATE Output Leakage 3.6 V < V ≤ 5.5V 10 µA O OZH CC O Current u t p ICCH Power Supply Current 3.6 Outputs HIGH 0.19 mA u t I Power Supply Current 3.6 Outputs LOW 5 mA s CCL I Power Supply Current 3.6 Outputs Disabled 0.19 mA CCZ I + Power Supply Current 3.6 V ≤ V ≤ 5.5V, 0.19 mA CCZ CC O Outputs Disabled ∆I Increase in Power Supply 3.6 One Input at V – 0.6V, 0.2 mA CC CC Current(6) Other Inputs at V or CC GND Notes: 2. All typical values are at V = 3.3V, T = 25°C. CC A 3. Applies to bushold versions only (74LVTH573). 4. An external driver must source at least the specified current to switch from LOW-to-HIGH. 5. An external driver must sink at least the specified current to switch from HIGH-to-LOW. 6. This is the increase in supply current for each input that is at the specified voltage level rather than V or GND. CC ©1999 Fairchild Semiconductor Corporation www.fairchildsemi.com 74LVT573, 74LVTH573 Rev. 1.7.0 5

7 4 Dynamic Switching Characteristics(7) L V T Conditions T = 25°C 5 A 7 Symbol Parameter VCC (V) CL = 50pF, RL = 500Ω Min. Typ. Max. Units 3, 7 V Quiet Output Maximum 3.3 (8) 0.8 V 4 OLP L Dynamic VOL V T VOLV Quiet Output Minimum 3.3 (8) –0.8 V H Dynamic V 5 OL 7 3 Notes: — 7. Characterized in SOIC package. Guaranteed parameter, but not tested. L 8. Max number of outputs defined as (n). n–1 data inputs are driven 0V to 3V. Output under test held LOW. o w V o AC Electrical Characteristics l t a TA = –40°C to +85°C ge C = 50pF, R = 500Ω O L L c V = 3.3V ± 0.3V V = 2.7V t CC CC a Symbol Parameter Min. Typ.(9) Max. Min. Max. Units l T r a tPHL Propagation Delay, Dn to On 1.5 4.4 1.5 4.9 ns n s tPLH 1.5 4.1 1.5 4.7 p a tPHL Propagation Delay, LE to On 1.9 4.4 1.9 4.9 ns re t 1.9 4.4 1.9 5.0 n PLH t L t Output Enable Time 1.5 5.1 1.5 6.6 ns PZL a t t 1.5 5.1 1.5 5.9 c PZH h tPLZ Output Disable Time 2.0 4.6 2.0 4.9 ns w i t 2.0 4.9 2.0 5.5 t PHZ h t Setup Time, D to LE 0.7 0.6 ns 3 S n - S tH Hold Time, Dn to LE 1.5 1.7 ns T A tW LE Pulse Width 3.0 3.0 ns T E tOSHL, tOSLH Output to Output Skew(10) 1.0 1.0 ns O Notes: u t 9. All typical values are at V = 3.3V, T = 25°C. p CC A u 10.Skew is defined as the absolute value of the difference between the actual propagation delay for any two ts separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t ) or LOW-to-HIGH (t ). OSHL OSLH Capacitance(11) Symbol Parameter Conditions Typical Units C Input Capacitance V = Open, V = 0V or V 4 pF IN CC I CC C Output Capacitance V = 3.0V, V = 0V or V 6 pF OUT CC O CC Note: 11.Capacitance is measured at frequency f = 1MHz, per MIL-STD-883, Method 3012. ©1999 Fairchild Semiconductor Corporation www.fairchildsemi.com 74LVT573, 74LVTH573 Rev. 1.7.0 6

7 4 Physical Dimensions L V T 5 13.00 7 12.60 3 A , 7 11.43 4 L 20 11 V T B H 5 7 3 — 9.50 10.65 7.60 L 10.00 7.40 o w 2.25 V o l t a g e PINONE 1 0.51 1.27 10 1.27 0.65 O 0.35 c INDICATOR t 0.25 M C B A a l LANDPATTERNRECOMMENDATION T r a n 2.65MAX s SEEDETAILA p a r e 0.33 n C 0.20 t L 0.30 0.10 C a t 0.75 0.10 SEATINGPLANE c X45° h 0.25 NOTES:UNLESSOTHERWISESPECIFIED w i (R0.10) th A) THISPACKAGECONFORMSTOJEDEC GAGEPLANE 3 (R0.10) MS-013,VARIATIONAC,ISSUEE - S 80°° 0.25 BC)) ADLIMLEDNIMSEIONNSSIODNOSNAORTEIINNCMLUILDLIEMMETOELRDS. TA T FLASHORBURRS. E 1.27 D) CONFORMSTOASMEY14.5M-1994 O 0.40 SEATINGPLANE E) LANDPATTERNSTANDARD:SOIC127P1030X265-20L u (1.40) DETAILA F) DRAWINGFILENAME:MKT-M20BREV3 tp SCALE:2:1 u t s Figure 1. 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ ©1999 Fairchild Semiconductor Corporation www.fairchildsemi.com 74LVT573, 74LVTH573 Rev. 1.7.0 7

7 4 Physical Dimensions (Continued) LV T 5 7 3 , 7 4 L V T H 5 7 3 — L o w V o l t a g e O c t a l T r a n s p a r e n t L a t c h w i t h 3 - S T A T E O u t p u t s Figure 2. 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ ©1999 Fairchild Semiconductor Corporation www.fairchildsemi.com 74LVT573, 74LVTH573 Rev. 1.7.0 8

7 4 Physical Dimensions (Continued) LV T 5 7 3 , 7 4 L V T H 5 7 3 — L o w V o l t a g e O c t a l T r a n s p a r e n t L a t c h w i t h 3 - S T A T E O u t p u t s Figure 3. 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ ©1999 Fairchild Semiconductor Corporation www.fairchildsemi.com 74LVT573, 74LVTH573 Rev. 1.7.0 9

7 4 Physical Dimensions (Continued) LV T 5 7 3 , 7 4 L V T H 5 7 3 — L o w V o l t a g e O c t a l T r a n s p a r e n t L a t c h w i t h 3 - S T A T E O u t p u t s Figure 4. 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ ©1999 Fairchild Semiconductor Corporation www.fairchildsemi.com 74LVT573, 74LVTH573 Rev. 1.7.0 10

7 4 L V T 5 7 3 , 7 TRADEMARKS 4 L Thefollowingincludesregisteredandunregisteredtrademarksandservicemarks,ownedbyFairchildSemiconductorand/oritsglobal V subsidiaries,andisnotintendedtobeanexhaustivelistofallsuchtrademarks. T H ACEx® FPS™ PDP-SPM™ SupreMOS™ 5 BuilditNow™ FRFET® Power220® SyncFET™ 7 CorePLUS™ GlobalPowerResourceSM POWEREDGE® ® 3 — CROSSVOLT™ GreenFPS™ Power-SPM™ ThePowerFranchise® CTL™ GreenFPS™e-Series™ PowerTrench® L CurrentTransferLogic™ GTO™ ProgrammableActiveDroop™ o EcoSPARK® i-Lo™ QFET® TinyBoost™ w EZSWITCH™* IntelliMAX™ QS™ TinyBuck™ V o ™ ISOPLANAR™ QTOptoelectronics™ TinyLogic® l t MegaBuck™ QuietSeries™ TINYOPTO™ a ® MICROCOUPLER™ RapidConfigure™ TinyPower™ ge FFaaiirrcchhiilldd®Semiconductor® MMiiccrrooPFEakT™™ SSMPMAR®TSTART™ TTiinnyyWPWireM™™ Oc FACTQuietSeries™ MillerDrive™ STEALTH™ µSerDes™ t a FACT® Motion-SPM™ SuperFET™ UHC® l FFaAsStvTC®ore™ OOPPTTOOLPOLAGNICA®R® SSuuppeerrSSOOTT™™--36 UUlntriFaEFTR™FET™ Tra FlashWriter®* ® SuperSOT™-8 VCX™ ns p *EZSWITCH™andFlashWriter®aretrademarksofSystemGeneralCorporation,usedunderlicensebyFairchildSemiconductor. a r e n DISCLAIMER t L FAIRCHILDSEMICONDUCTORRESERVESTHERIGHTTOMAKECHANGESWITHOUTFURTHERNOTICETOANYPRODUCTS a HEREINTOIMPROVERELIABILITY,FUNCTION,ORDESIGN.FAIRCHILDDOESNOTASSUMEANYLIABILITYARISINGOUTOFTHE t c APPLICATIONORUSEOFANYPRODUCTORCIRCUITDESCRIBEDHEREIN;NEITHERDOESITCONVEYANYLICENSEUNDERITS h PATENTRIGHTS,NORTHERIGHTSOFOTHERS.THESESPECIFICATIONSDONOTEXPANDTHETERMSOFFAIRCHILD’S w WORLDWIDETERMSANDCONDITIONS,SPECIFICALLYTHEWARRANTYTHEREIN,WHICHCOVERSTHESEPRODUCTS. i t h 3 LIFESUPPORTPOLICY - S FAIRCHILD’SPRODUCTSARENOTAUTHORIZEDFORUSEASCRITICALCOMPONENTSINLIFESUPPORTDEVICESOR T SYSTEMSWITHOUTTHEEXPRESSWRITTENAPPROVALOFFAIRCHILDSEMICONDUCTORCORPORATION. A T Asusedherein: E 1. Life support devices or systems are devices or systems 2. A critical component in any component of a life support, O which, (a) are intended for surgical implant intothebodyor device, or system whose failure to perform can be u (b) support or sustain life, and (c) whose failure to perform reasonablyexpectedtocausethefailureofthelifesupport t p when properly used in accordance with instructions for use deviceorsystem,ortoaffectitssafetyoreffectiveness. u provided in the labeling, can be reasonably expected to t s resultinasignificantinjuryoftheuser. PRODUCTSTATUSDEFINITIONS DefinitionofTerms DatasheetIdentification ProductStatus Definition Thisdatasheetcontainsthedesignspecificationsforproduct AdvanceInformation FormativeorInDesign development.Specificationsmaychangeinanymannerwithoutnotice. Thisdatasheetcontainspreliminarydata;supplementarydatawillbe Preliminary First Production publishedatalaterdate.FairchildSemiconductorreservestherightto makechangesatanytimewithoutnoticetoimprovedesign. Thisdatasheetcontainsfinalspecifications.FairchildSemiconductor NoIdentificationNeeded FullProduction reservestherighttomakechangesatanytimewithoutnoticetoimprove thedesign. Thisdatasheetcontainsspecificationsonaproductthathasbeen Obsolete NotInProduction discontinuedbyFairchildSemiconductor.Thedatasheetisprintedfor referenceinformationonly. Rev.I33 ©1999 Fairchild Semiconductor Corporation www.fairchildsemi.com 74LVT573, 74LVTH573 Rev. 1.7.0 11

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: N. American Technical Support: 800−282−9855 Toll Free ON Semiconductor Website: www.onsemi.com Literature Distribution Center for ON Semiconductor USA/Canada 19521 E. 32nd Pkwy, Aurora, Colorado 80011 USA Europe, Middle East and Africa Technical Support: Order Literature: http://www.onsemi.com/orderlit Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Phone: 421 33 790 2910 Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Japan Customer Focus Center For additional information, please contact your local Email: orderlit@onsemi.com Phone: 81−3−5817−1050 Sales Representative © Semiconductor Components Industries, LLC www.onsemi.com www.onsemi.com 1

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: O N Semiconductor: 74LVT573MTCX 74LVT573WM 74LVT573SJX 74LVT573MTC 74LVT573MSA 74LVT573MSAX