74LVC74A Dual D-type flip-flop with set and reset; positive-edge trigger Rev. 8 — 18 June 2020 Product data sheet 1. General description The 74LVC74A is a dual edge triggered D-type flip-flop with individual data (nD) inputs, clock (nCP) inputs, set (nSD) and (nRD) inputs, and complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Information on the data input is transferred to the nQ output on the LOW-to-HIGH transition of the clock pulse. The nD inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition, for predictable operation. Schmitt trigger action at all inputs makes the circuit highly tolerant of slower input rise and fall times. 2. Features and benefits • 5 V tolerant inputs for interlacing with 5 V logic • Wide supply voltage range from 1.2 V to 3.6 V • CMOS low power consumption • Direct interface with TTL levels • Complies with JEDEC standard: • JESD8-7A (1.65 V to 1.95 V) • JESD8-5A (2.3 V to 2.7 V) • JESD8-C/JESD36 (2.7 V to 3.6 V) • ESD protection: • HBM JESD22-A114F exceeds 2000 V • MM JESD22-A115-B exceeds 200 V • CDM JESD22-C101E exceeds 1000 V • Multiple package options • Specified from -40 °C to +85 °C and -40 °C to +125 °C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC74AD -40 °C to +125 °C SO14 plastic small outline package; 14 leads; SOT108-1 body width 3.9 mm 74LVC74ADB -40 °C to +125 °C SSOP14 plastic shrink small outline package; 14 leads; SOT337-1 body width 5.3 mm 74LVC74APW -40 °C to +125 °C TSSOP14 plastic thin shrink small outline package; 14 leads; SOT402-1 body width 4.4 mm 74LVC74ABQ -40 °C to +125 °C DHVQFN14 plastic dual in-line compatible thermal enhanced SOT762-1 very thin quad flat package; no leads; 14 terminals; body 2.5 × 3 × 0.85 mm

Nexperia 74LVC74A Dual D-type flip-flop with set and reset; positive-edge trigger 4. Functional diagram 1SD 4 SD 1D 1Q 2 D Q 5 1CP 3 CP FF 1Q Q 6 4 RD 4 10 S 5 1SD 2SD 3 C1 1 1RD SD 2 1D 6 10 2SD 2 1D 1Q 5 1 R D Q 12 2D 2Q 9 SD 3 1CP CP 12 2D D Q 2Q 9 11 2CP 10 FF S 9 2CP RD Q 12QQ 68 1112 1CD1 8 11 CPFF Q 2Q 8 1RD 2RD 13 R RD 1 13 mna418 mna419 13 2RD mna420 Fig. 1. Logic symbol Fig. 2. IEC logic symbol Fig. 3. Functional diagram Q C C C C C C D Q C C RD SD mna421 CP C C Fig. 4. Logic diagram for one flip-flop 74LVC74A All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2020. All rights reserved Product data sheet Rev. 8 — 18 June 2020 2 / 17

Nexperia 74LVC74A Dual D-type flip-flop with set and reset; positive-edge trigger 5. Pinning information 5.1. Pinning 74LVC74A D C terminal 1 R C 1 V index area 74LVC74A 1 14 1D 2 13 2RD 1RD 1 14 VCC 1CP 3 12 2D 1SD 4 11 2CP 1D 2 13 2RD 1Q 5 GND(1) 10 2SD 1CP 3 12 2D 1Q 6 9 2Q 1SD 4 11 2CP 7 8 D Q 1Q 5 10 2SD GN 2 001aad107 1Q 6 9 2Q Transparent top view (1) This is not a ground pin. There is no electrical or GND 7 8 2Q mechanical requirement to solder the pad. In case 001aad106 soldered, the solder land should remain floating or connected to GND. Fig. 5. Pin configuration for SOT108-1 (SO14), SOT337-1 (SSOP14) and SOT402-1 (TSSOP14) Fig. 6. Pin configuration for SOT762-1 (DHVQFN14) 5.2. Pin description Table 2. Pin description Symbol Pin Description 1RD 1 asynchronous reset-direct input (active LOW) 1D 2 data input 1CP 3 clock input (LOW-to-HIGH, edge-triggered) 1SD 4 asynchronous set-direct input (active LOW) 1Q 5 true output 1Q 6 complement output GND 7 ground (0 V) 2Q 8 complement output 2Q 9 true output 2SD 10 asynchronous set-direct input (active LOW) 2CP 11 clock input (LOW-to-HIGH, edge-triggered) 2D 12 data input 2RD 13 asynchronous reset-direct input (active LOW) V 14 supply voltage CC 74LVC74A All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2020. All rights reserved Product data sheet Rev. 8 — 18 June 2020 3 / 17

Nexperia 74LVC74A Dual D-type flip-flop with set and reset; positive-edge trigger 6. Functional description Table 3. Function table H = HIGH voltage level; L = LOW voltage level; X = don’t care Input Output nSD nRD nCP nD nQ nQ L H X X H L H L X X L H L L X X H H Table 4. Function table H = HIGH voltage level; L = LOW voltage level; ↑ = LOW-to-HIGH transition; Q = state after the next LOW-to-HIGH CP transition n+1 Input Output nSD nRD nCP nD nQ nQ n+1 n+1 H H ↑ L L H H H ↑ H H L 7. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit V supply voltage -0.5 +6.5 V CC I input clamping current V < 0 V -50 - mA IK I V input voltage [1] -0.5 +6.5 V I I output clamping current V > V or V < 0 V - ±50 mA OK O CC O V output voltage [2] -0.5 V + 0.5 V O CC I output current V = 0 V to V - ±50 mA O O CC I supply current - 100 mA CC I ground current -100 - mA GND T storage temperature -65 +150 °C stg P total power dissipation T = -40 °C to +125 °C [3] - 500 mW tot amb [1] The minimum input voltage ratings may be exceeded if the input current ratings are observed. [2] The output voltage ratings may be exceeded if the output current ratings are observed. [3] For SOT108-1 (SO14) package: Ptot derates linearly with 10.1 mW/K above 100 °C. For SOT337-1 (SSOP14) package: Ptot derates linearly with 7.3 mW/K above 81 °C. For SOT402-1 (TSSOP14) package: Ptot derates linearly with 7.3 mW/K above 81 °C. For SOT762-1 (DHVQFN14) package: Ptot derates linearly with 9.6 mW/K above 98 °C. 74LVC74A All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2020. All rights reserved Product data sheet Rev. 8 — 18 June 2020 4 / 17

Nexperia 74LVC74A Dual D-type flip-flop with set and reset; positive-edge trigger 8. Recommended operating conditions Table 6. Recommended operating conditions Symbol Parameter Conditions Min Typ Max Unit V supply voltage for maximum speed performance 1.65 - 3.6 V CC for low-voltage applications 1.2 - 3.6 V V input voltage 0 - 5.5 V I V output voltage 0 - V V O CC T ambient temperature -40 - +125 °C amb Δt/ΔV input transition rise and V = 1.65 V to 2.7 V 0 - 20 ns/V CC fall rate V = 2.7 V to 3.6 V 0 - 10 ns/V CC 9. Static characteristics Table 7. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions -40 °C to +85 °C -40 °C to +125 °C Unit Min Typ[1] Max Min Max V HIGH-level V = 1.2 V 1.08 - - 1.08 - V IH CC input voltage V = 1.65 V to 1.95 V 0.65xV - - 0.65xV - V CC CC CC V = 2.3 V to 2.7 V 1.7 - - 1.7 - V CC V = 2.7 V to 3.6 V 2.0 - - 2.0 - V CC V LOW-level V = 1.2 V - - 0.12 - 0.12 V IL CC input voltage V = 1.65 V to 1.95 V - - 0.35xV - 0.35xV V CC CC CC V = 2.3 V to 2.7 V - - 0.7 - 0.7 V CC V = 2.7 V to 3.6 V - - 0.8 - 0.8 V CC V HIGH-level V = V or V OH I IH IL output voltage I = -100 μA; V - 0.2 - - V - 0.3 - V O CC CC V = 1.65 V to 3.6 V CC I = -4 mA; V = 1.65 V 1.2 - - 1.05 - V O CC I = -8 mA; V = 2.3 V 1.8 - - 1.65 - V O CC I = -12 mA; V = 2.7 V 2.2 - - 2.05 - V O CC I = -18 mA; V = 3.0 V 2.4 - - 2.25 - V O CC I = -24 mA; V = 3.0 V 2.2 - - 2.0 - V O CC V LOW-level V = V or V OL I IH IL output voltage I = 100 μA; - - 0.2 - 0.3 V O V = 1.65 V to 3.6 V CC I = 4 mA; V = 1.65 V - - 0.45 - 0.65 V O CC I = 8 mA; V = 2.3 V - - 0.6 - 0.8 V O CC I = 12 mA; V = 2.7 V - - 0.4 - 0.6 V O CC I = 24 mA; V = 3.0 V - - 0.55 - 0.8 V O CC I input leakage V = 3.6 V; V = 5.5 V or GND - ±0.1 ±5 - ±20 μA I CC I current I supply current V = 3.6 V; V = V or GND; - 0.1 10 - 40 μA CC CC I CC I = 0 A O 74LVC74A All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2020. All rights reserved Product data sheet Rev. 8 — 18 June 2020 5 / 17

Nexperia 74LVC74A Dual D-type flip-flop with set and reset; positive-edge trigger Symbol Parameter Conditions -40 °C to +85 °C -40 °C to +125 °C Unit Min Typ[1] Max Min Max ΔI additional per input pin; - 5 500 - 5000 μA CC supply current V = 2.7 V to 3.6 V; CC V = V - 0.6 V; I = 0 A I CC O C input V = 0 V to 3.6 V; - 4.0 - - - pF I CC capacitance V = GND to V I CC [1] All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb = 25 °C. 10. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Fig. 9. Symbol Parameter Conditions -40 °C to +85 °C -40 °C to +125 °C Unit Min Typ[1] Max Min Max t propagation nCP to nQ, nQ; see Fig. 7 [2] pd delay V = 1.2 V - 15 - - - ns CC V = 1.65 V to 1.95 V 1.0 5.0 10.3 1.0 11.9 ns CC V = 2.3 V to 2.7 V 1.8 2.9 5.8 1.8 6.7 ns CC V = 2.7 V 1.0 2.7 6.0 1.0 7.5 ns CC V = 3.0 V to 3.6 V 1.0 2.6 5.2 1.0 6.5 ns CC nSD to nQ, nQ; see Fig. 8 V = 1.2 V - 15 - - - ns CC V = 1.65 V to 1.95 V 0.5 4.0 10.6 0.5 12.2 ns CC V = 2.3 V to 2.7 V 1.0 2.4 6.1 1.0 7.1 ns CC V = 2.7 V 1.0 2.9 6.4 1.0 8.0 ns CC V = 3.0 V to 3.6 V 1.0 2.2 5.4 1.0 7.0 ns CC nRD to nQ, nQ; see Fig. 8 V = 1.2 V - 15 - - - ns CC V = 1.65 V to 1.95 V 0.5 4.1 10.7 0.5 12.4 ns CC V = 2.3 V to 2.7 V 1.0 2.4 6.1 1.0 7.1 ns CC V = 2.7 V 1.0 3.0 6.4 1.0 8.0 ns CC V = 3.0 V to 3.6 V 1.0 2.2 5.4 1.0 7.0 ns CC t pulse width clock HIGH or LOW; see Fig. 7 W V = 1.65 V to 1.95 V 5.0 - - 5.0 - ns CC V = 2.3 V to 2.7 V 4.0 - - 4.0 - ns CC V = 2.7 V 3.3 - - 4.5 - ns CC V = 3.0 V to 3.6 V 3.3 1.3 - 4.5 - ns CC set or reset LOW; see Fig. 8 V = 1.65 V to 1.95 V 5.0 - - 5.0 - ns CC V = 2.3 V to 2.7 V 4.0 - - 4.0 - ns CC V = 2.7 V 3.3 - - 4.5 - ns CC V = 3.0 V to 3.6 V 3.3 1.7 - 4.5 - ns CC 74LVC74A All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2020. All rights reserved Product data sheet Rev. 8 — 18 June 2020 6 / 17

Nexperia 74LVC74A Dual D-type flip-flop with set and reset; positive-edge trigger Symbol Parameter Conditions -40 °C to +85 °C -40 °C to +125 °C Unit Min Typ[1] Max Min Max t recovery time set or reset; see Fig. 8 rec V = 1.65 V to 1.95 V 1.5 - - 1.5 - ns CC V = 2.3 V to 2.7 V 1.5 - - 1.5 - ns CC V = 2.7 V 1.5 - - 1.0 - ns CC V = 3.0 V to 3.6 V +1.0 -3.0 - 1.0 - ns CC t set-up time nD to nCP; see Fig. 7 su V = 1.65 V to 1.95 V 3.0 - - 3.0 - ns CC V = 2.3 V to 2.7 V 2.5 - - 2.5 - ns CC V = 2.7 V 2.2 - - 2.2 - ns CC V = 3.0 V to 3.6 V 2.0 0.8 - 2.0 - ns CC t hold time nD to nCP; see Fig. 7 h V = 1.65 V to 1.95 V 2.0 - - 2.0 - ns CC V = 2.3 V to 2.7 V 1.5 - - 1.5 - ns CC V = 2.7 V 1.0 - - 1.0 - ns CC V = 3.0 V to 3.6 V +1.0 -0.2 - 1.0 - ns CC f maximum nCP; see Fig. 7 max frequency V = 1.65 V to 1.95 V 100 - - 80 - MHz CC V = 2.3 V to 2.7 V 125 - - 100 - MHz CC V = 2.7 V 150 - - 120 - MHz CC V = 3.0 V to 3.6 V 150 250 - 120 - MHz CC t output skew time V = 3.0 V to 3.6 V [3] - - 1.0 - 1.5 ns sk(o) CC C power dissipation per flip-flop; V = GND to V [4] PD I CC capacitance V = 1.65 V to 1.95 V - 12.4 - - - pF CC V = 2.3 V to 2.7 V - 16.0 - - - pF CC V = 3.0 V to 3.6 V - 19.1 - - - pF CC [1] Typical values are measured at Tamb = 25 °C and VCC = 1.2 V, 1.8 V, 2.5 V, 2.7 V and 3.3 V respectively. [2] tpd is the same as tPLH and tPHL. [3] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design. [4] CPD is used to determine the dynamic power dissipation (PD in μW). PD = CPD x VCC 2 x fi x N + Σ(CL x VCC 2 x fo) where: fi = input frequency in MHz; fo = output frequency in MHz CL = output load capacitance in pF VCC = supply voltage in Volts N = number of inputs switching Σ(CL x VCC 2 x fo) = sum of the outputs 74LVC74A All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2020. All rights reserved Product data sheet Rev. 8 — 18 June 2020 7 / 17

Nexperia 74LVC74A Dual D-type flip-flop with set and reset; positive-edge trigger 10.1. Waveforms and test circuit VI nD input VM GND th th tsu tsu 1/fmax VI nCP input VM GND tW tPHL tPLH VOH nQ output VM VOL VOH nQ output VM VOL mna422 tPLH tPHL The shaded areas indicate when the input is permitted to change for predictable output performance. Measurement points are given in Table 9. V and V are typical output voltage levels that occur with the output load. OL OH Fig. 7. The clock input (nCP) to output (nQ, nQ) propagation delays, the clock pulse width, the nD to nCP set-up, the nCP to nD hold times, and the maximum frequency 74LVC74A All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2020. All rights reserved Product data sheet Rev. 8 — 18 June 2020 8 / 17

Nexperia 74LVC74A Dual D-type flip-flop with set and reset; positive-edge trigger VI nCP input VM GND trec VI nSD input VM GND tW tW VI nRD input VM GND tPLH tPHL VOH nQ output VM VOL VOH nQ output VM VOL tPHL tPLH mna423 Measurement points are given in Table 9. V and V are typical output voltage levels that occur with the output load. OL OH Fig. 8. The set (nSD) and reset (nRD) input to output (nQ, nQ) propagation delays, the set and reset pulse widths, and the nRD to nCP recovery time Table 9. Measurement points Supply voltage Input Output V V V V CC I M M 1.2 V V 0.5 x V 0.5 x V CC CC CC 1.65 V to 1.95 V V 0.5 x V 0.5 x V CC CC CC 2.3 V to 2.7 V V 0.5 x V 0.5 x V CC CC CC 2.7 V 2.7 V 1.5 V 1.5 V 3.0 V to 3.6 V 2.7 V 1.5 V 1.5 V 74LVC74A All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2020. All rights reserved Product data sheet Rev. 8 — 18 June 2020 9 / 17

Nexperia 74LVC74A Dual D-type flip-flop with set and reset; positive-edge trigger tW VI 90 % negative pulse VM VM 10 % 0 V tf tr tr tf VI 90 % positive pulse VM VM 10 % 0 V tW VCC VI VO PULSE DUT GENERATOR RT CL RL 001aaf615 Test data is given in Table 10. Definitions for test circuit: R = Load resistance. L C = Load capacitance including jig and probe capacitance. L R = Termination resistance should be equal to output impedance Z of the pulse generator. T o Fig. 9. Test circuit for measuring switching times Table 10. Test data Supply voltage Input Load V V t, t C R CC I r f L L 1.2 V V ≤ 2 ns 30 pF 1 kΩ CC 1.65 V to 1.95 V V ≤ 2 ns 30 pF 1 kΩ CC 2.3 V to 2.7 V V ≤ 2 ns 30 pF 500 Ω CC 2.7 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω 3.0 V to 3.6 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω 74LVC74A All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2020. All rights reserved Product data sheet Rev. 8 — 18 June 2020 10 / 17

Nexperia 74LVC74A Dual D-type flip-flop with set and reset; positive-edge trigger 11. Package outline SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y H E v M A Z 14 8 Q A 2 A 1 (A 3 ) A pin 1 index θ L p 1 7 L e w M detail X b p 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mAax . A 1 A 2 A 3 b p c D (1) E (1) e H E L L p Q v w y Z (1) θ 0.25 1.45 0.49 0.25 8.75 4.0 6.2 1.0 0.7 0.7 mm 1.75 0.25 1.27 1.05 0.25 0.25 0.1 0.10 1.25 0.36 0.19 8.55 3.8 5.8 0.4 0.6 0.3 8 o 0.010 0.057 0.019 0.0100 0.35 0.16 0.244 0.039 0.028 0.028 0 o inches 0.069 0.01 0.05 0.041 0.01 0.01 0.004 0.004 0.049 0.014 0.0075 0.34 0.15 0.228 0.016 0.024 0.012 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE REFERENCES EUROPEAN ISSUE DATE VERSION IEC JEDEC JEITA PROJECTION 99-12-27 SOT108-1 076E06 MS-012 03-02-19 Fig. 10. Package outline SOT108-1 (SO14) 74LVC74A All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2020. All rights reserved Product data sheet Rev. 8 — 18 June 2020 11 / 17

Nexperia 74LVC74A Dual D-type flip-flop with set and reset; positive-edge trigger SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1 D E A X c y H E v M A Z 14 8 Q A 2 A 1 (A 3 ) A pin 1 index θ L p L 1 7 detail X w M e b p 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT mAax . A 1 A 2 A 3 b p c D (1) E (1) e H E L L p Q v w y Z (1) θ 0.21 1.80 0.38 0.20 6.4 5.4 7.9 1.03 0.9 1.4 8 o mm 2 0.05 1.65 0.25 0.25 0.09 6.0 5.2 0.65 7.6 1.25 0.63 0.7 0.2 0.13 0.1 0.9 0 o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE REFERENCES EUROPEAN ISSUE DATE VERSION IEC JEDEC JEITA PROJECTION 99-12-27 SOT337-1 MO-150 03-02-19 Fig. 11. Package outline SOT337-1 (SSOP14) 74LVC74A All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2020. All rights reserved Product data sheet Rev. 8 — 18 June 2020 12 / 17

Nexperia 74LVC74A Dual D-type flip-flop with set and reset; positive-edge trigger TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 D E A X c y H E v M A Z 14 8 Q A 2 (A 3 ) A pin 1 index A 1 θ L p L 1 7 detail X w M e b p 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT mAax . A 1 A 2 A 3 b p c D (1) E (2) e H E L L p Q v w y Z (1) θ 0.15 0.95 0.30 0.2 5.1 4.5 6.6 0.75 0.4 0.72 8 o mm 1.1 0.05 0.80 0.25 0.19 0.1 4.9 4.3 0.65 6.2 1 0.50 0.3 0.2 0.13 0.1 0.38 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE REFERENCES EUROPEAN ISSUE DATE VERSION IEC JEDEC JEITA PROJECTION 99-12-27 SOT402-1 MO-153 03-02-18 Fig. 12. Package outline SOT402-1 (TSSOP14) 74LVC74A All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2020. All rights reserved Product data sheet Rev. 8 — 18 June 2020 13 / 17

Nexperia 74LVC74A Dual D-type flip-flop with set and reset; positive-edge trigger DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.5 x 3 x 0.85 mm SOT762-1 D B A A A1 E c terminal 1 detail X index area terminal 1 C e1 index area e b v C A B y1C y w C 2 6 L 1 7 Eh e 14 8 k 13 9 Dh X k 0 2 4 mm scale Dimensions (mm are the original dimensions) Unit A(1) A1 b c D(1) Dh E(1) Eh e e1 k L v w y y1 max 1 0.05 0.30 3.1 1.65 2.6 1.15 0.5 mm nom 0.02 0.25 0.2 3.0 1.50 2.5 1.00 0.5 2 0.4 0.1 0.05 0.05 0.1 min 0.00 0.18 2.9 1.35 2.4 0.85 0.2 0.3 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. sot762-1_po Outline References European Issue date version IEC JEDEC JEITA projection 15-04-10 SOT762-1 MO-241 15-05-05 Fig. 13. Package outline SOT762-1 (DHVQFN14) 74LVC74A All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2020. All rights reserved Product data sheet Rev. 8 — 18 June 2020 14 / 17

Nexperia 74LVC74A Dual D-type flip-flop with set and reset; positive-edge trigger 12. Abbreviations Table 11. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 13. Revision history Table 12. Revision history Document ID Release date Data sheet status Change notice Supersedes 74LVC74A v.8 20200618 Product data sheet - 74LVC74A v.7 Modifications: • The format of this data sheet has been redesigned to comply with the identity guidelines of Nexperia. • Legal texts have been adapted to the new company name where appropriate. • Section 1 and Section 2 updated. • Table 5: Derating values for P total power dissipation have been updated. tot • Table 10 corrected (errata). • Package outline drawing of SOT762-1 (Fig. 13) updated. 74LVC74A v.7 20121120 Product data sheet - 74LVC74A v.6 Modifications: • Table 6, Table 7, Table 8, Table 9 and Table 10: values added for lower voltage ranges. 74LVC74A v.6 20070604 Product data sheet - 74LVC74A v.5 74LVC74A v.5 20070525 Product data sheet - 74LVC74A v.4 74LVC74A v.4 20030526 Product specification - 74LVC74A v.3 74LVC74A v.3 20020618 Product specification - 74LVC74A v.2 74LVC74A v.2 19980617 Product specification - 74LVC74A v.1 74LVC74A v.1 19980617 Product specification - - 74LVC74A All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2020. All rights reserved Product data sheet Rev. 8 — 18 June 2020 15 / 17

Nexperia 74LVC74A Dual D-type flip-flop with set and reset; positive-edge trigger injury, death or severe property or environmental damage. Nexperia and its 14. Legal information suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Quick reference data — The Quick reference data is an extract of the Data sheet status product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Document status Product Definition Applications — Applications that are described herein for any of these [1][2] status [3] products are for illustrative purposes only. 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Nexperia’s specifications such use shall be solely at customer’s own risk, Notwithstanding any damages that customer might incur for any reason and (c) customer fully indemnifies Nexperia for any liability, damages or failed whatsoever, Nexperia’s aggregate and cumulative liability towards customer product claims resulting from customer design and use of the product for for the products described herein shall be limited in accordance with the automotive applications beyond Nexperia’s standard warranty and Nexperia’s Terms and conditions of commercial sale of Nexperia. product specifications. Right to make changes — Nexperia reserves the right to make changes Translations — A non-English (translated) version of a document is for to information published in this document, including without limitation reference only. The English version shall prevail in case of any discrepancy specifications and product descriptions, at any time and without notice. This between the translated and English versions. document supersedes and replaces all information supplied prior to the publication hereof. Trademarks Suitability for use — Nexperia products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical Notice: All referenced brands, product names, service names and systems or equipment, nor in applications where failure or malfunction trademarks are the property of their respective owners. of an Nexperia product can reasonably be expected to result in personal 74LVC74A All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2020. All rights reserved Product data sheet Rev. 8 — 18 June 2020 16 / 17

Nexperia 74LVC74A Dual D-type flip-flop with set and reset; positive-edge trigger Contents 1. General description......................................................1 2. Features and benefits..................................................1 3. Ordering information....................................................1 4. Functional diagram.......................................................2 5. Pinning information......................................................3 5.1. Pinning.........................................................................3 5.2. Pin description.............................................................3 6. Functional description.................................................4 7. Limiting values.............................................................4 8. Recommended operating conditions..........................5 9. Static characteristics....................................................5 10. Dynamic characteristics............................................6 10.1. Waveforms and test circuit........................................8 11. Package outline........................................................11 12. Abbreviations............................................................15 13. Revision history........................................................15 14. Legal information......................................................16 © Nexperia B.V. 2020. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 18 June 2020 74LVC74A All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2020. All rights reserved Product data sheet Rev. 8 — 18 June 2020 17 / 17