74LVC32A Quad 2-input OR gate Rev. 6 — 12 September 2018 Product data sheet 1. General description The 74LVC32A provides four 2-input OR gates. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V applications. 2. Features and benefits • 5 V tolerant inputs for interlacing with 5 V logic • Wide supply voltage range from 1.2 V to 3.6 V • CMOS low power consumption • Direct interface with TTL levels • Complies with JEDEC standard: • JESD8-7A (1.65 V to 1.95 V) • JESD8-5A (2.3 V to 2.7 V) • JESD8-C/JESD36 (2.7 V to 3.6 V) • ESD protection: • HBM JESD22-A114F exceeds 2000 V • MM JESD22-A115-B exceeds 200 V • CDM JESD22-C101E exceeds 1000 V • Specified from -40 °C to +85 °C and -40 °C to +125 °C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC32AD -40 °C to +125 °C SO14 plastic small outline package; 14 leads; SOT108-1 body width 3.9 mm 74LVC32ADB -40 °C to +125 °C SSOP14 plastic shrink small outline package; 14 leads; SOT337-1 body width 5.3 mm 74LVC32APW -40 °C to +125 °C TSSOP14 plastic thin shrink small outline package; 14 leads; SOT402-1 body width 4.4 mm 74LVC32ABQ -40 °C to +125 °C DHVQFN14 plastic dual in-line compatible thermal enhanced SOT762-1 very thin quad flat package; no leads; 14 terminals; body 2.5 × 3 × 0.85 mm

Nexperia 74LVC32A Quad 2-input OR gate 4. Functional diagram 1 ≥1 3 2 4 1 1A ≥1 6 1Y 3 5 2 1B 4 2A 2Y 6 9 5 2B ≥1 8 9 3A 10 3Y 8 10 3B 12 4A 12 4Y 11 ≥1 11 13 4B 13 mna242 mna243 Fig. 1. Logic symbol Fig. 2. IEC logic symbol A Y B mna241 Fig. 3. Logic diagram for one gate 5. Pinning information 5.1. Pinning 74LVC32A 74LVC32A 1A 1 14 VCC 1B 2 13 4B 1A 1 14 VCC 1B 2 13 4B 1Y 3 12 4A 1Y 3 12 4A 2A 4 11 4Y 2A 4 11 4Y 2B 5 10 3B 2B 5 10 3B 2Y 6 9 3A 2Y 6 9 3A GND 7 8 3Y GND 7 8 3Y aaa-028966 aaa-028965 Fig. 5. Pin configuration SOT337-1 (SSOP14) and Fig. 4. Pin configuration SOT108-1 (SO14) SOT402-1 (TSSOP14) 74LVC32A All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved Product data sheet Rev. 6 — 12 September 2018 2 / 14

Nexperia 74LVC32A Quad 2-input OR gate 74LVC32A C terminal 1 A C 1 V index area 1 14 1B 2 13 4B 1Y 3 12 4A 2A 4 11 4Y 2B 5 GND(1) 10 3B 2Y 6 9 3A 7 8 D Y GN 3 aaa-028967 Transparent top view (1) This is not a supply pin. The substrate is attached to this pad using conductive die attach material. There is no electrical or mechanical requirement to solder this pad. However, if it is soldered, the solder land should remain floating or be connected to GND. Fig. 6. Pin configuration SOT762-1 (DHVQFN14) 5.2. Pin description Table 2. Pin description Symbol Pin Description 1A, 2A, 3A, 4A 1, 4, 9, 12 data input 1B, 2B, 3B, 4B 2, 5, 10, 13 data input 1Y, 2Y, 3Y, 4Y 3, 6, 8, 11 data output GND 7 ground (0 V) V 14 supply voltage CC 6. Functional description Table 3. Function selection H = HIGH voltage level; L = LOW voltage level; X = don’t care Input Output nA nB nY L L L X H H H X H 74LVC32A All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved Product data sheet Rev. 6 — 12 September 2018 3 / 14

Nexperia 74LVC32A Quad 2-input OR gate 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit V supply voltage -0.5 +6.5 V CC I input clamping current V < 0 -50 - mA IK I V input voltage [1] -0.5 +6.5 V I I output clamping current V > V or V < 0 - ±50 mA OK O CC O V output voltage [2] -0.5 V + 0.5 V O CC I output current V = 0 V to V - ±50 mA O O CC I supply current - 100 mA CC I ground current -100 - mA GND T storage temperature -65 +150 °C stg P total power dissipation T = -40 °C to +125 °C [3] - 500 mW tot amb [1] The minimum input voltage ratings may be exceeded if the input current ratings are observed. [2] The output voltage ratings may be exceeded if the output current ratings are observed. [3] For SO14 packages: above 70 °C derate linearly with 8 mW/K. For (T)SSOP14 packages: above 60 °C derate linearly with 5.5 mW/K. For DHVQFN14 packages: above 60 °C derate linearly with 4.5 mW/K. 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter Conditions Min Typ Max Unit V supply voltage 1.65 - 3.6 V CC functional 1.2 - - V V input voltage 0 - 5.5 V I V output voltage 0 - V V O CC T ambient temperature -40 - +125 °C amb Δt/ΔV input transition rise and fall rate V = 1.65 V to 2.7 V 0 - 20 ns/V CC V = 2.7 V to 3.6 V 0 - 10 ns/V CC 74LVC32A All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved Product data sheet Rev. 6 — 12 September 2018 4 / 14

Nexperia 74LVC32A Quad 2-input OR gate 9. Static characteristics Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions -40 °C to +85 °C -40 °C to +125 °C Unit Min Typ [1] Max Min Max V HIGH-level V = 1.2 V 1.08 - - 1.08 - V IH CC input voltage V = 1.65 V to 1.95 V 0.65V - - 0.65V - V CC CC CC V = 2.3 V to 2.7 V 1.7 - - 1.7 - V CC V = 2.7 V to 3.6 V 2.0 - - 2.0 - V CC V LOW-level V = 1.2 V - - 0.12 - 0.12 V IL CC input voltage V = 1.65 V to 1.95 V - - 0.35V - 0.35V V CC CC CC V = 2.3 V to 2.7 V - - 0.7 - 0.7 V CC V = 2.7 V to 3.6 V - - 0.8 - 0.8 V CC V HIGH-level V = V or V OH I IH IL output voltage I = -100 μA; V - 0.2 - - V - 0.3 - V O CC CC V = 1.65 V to 3.6 V CC I = -4 mA; V = 1.65 V 1.2 - - 1.05 - V O CC I = -8 mA; V = 2.3 V 1.8 - - 1.65 - V O CC I = -12 mA; V = 2.7 V 2.2 - - 2.05 - V O CC I = -18 mA; V = 3.0 V 2.4 - - 2.25 - V O CC I = -24 mA; V = 3.0 V 2.2 - - 2.0 - V O CC V LOW-level V = V or V OL I IH IL output voltage I = 100 μA; - - 0.2 - 0.3 V O V = 1.65 V to 3.6 V CC I = 4 mA; V = 1.65 V - - 0.45 - 0.65 V O CC I = 8 mA; V = 2.3 V - - 0.6 - 0.8 V O CC I = 12 mA; V = 2.7 V - - 0.4 - 0.6 V O CC I = 24 mA; V = 3.0 V - - 0.55 - 0.8 V O CC I input leakage V = 3.6 V; V = 5.5 V or GND - ±0.1 ±5 - ±20 μA I CC I current I supply current V = 3.6 V; V = V or GND; - 0.1 10 - 40 μA CC CC I CC I = 0 A O ΔI additional per input pin; - 5 500 - 5000 μA CC supply current V = 2.7 V to 3.6 V; CC V = V - 0.6 V; I = 0 A I CC O C input V = 0 V to 3.6 V; - 4.0 - - - pF I CC capacitance V = GND to V I CC [1] All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb = 25 °C. 74LVC32A All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved Product data sheet Rev. 6 — 12 September 2018 5 / 14

Nexperia 74LVC32A Quad 2-input OR gate 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Fig. 8. Symbol Parameter Conditions -40 °C to +85 °C -40 °C to +125 °C Unit Min Typ [1] Max Min Max t propagation delay nA, nB to nY; see Fig. 7 [2] pd V = 1.2 V - 10 - - - ns CC V = 1.65 V to 1.95 V 0.5 4.2 9.0 0.5 10.4 ns CC V = 2.3 V to 2.7 V 1.5 2.4 4.9 1.5 5.7 ns CC V = 2.7 V 1.5 2.5 4.4 1.5 5.5 ns CC V = 3.0 V to 3.6 V 1.0 2.2 3.8 1.0 5.0 ns CC t output skew time V = 3.0 V to 3.6 V [3] - - 1.0 - 1.5 ns sk(o) CC C power dissipation per gate; V = GND to V [4] PD I CC capacitance V = 1.65 V to 1.95 V - 4.7 - - - pF CC V = 2.3 V to 2.7 V - 8.0 - - - pF CC V = 3.0 V to 3.6 V - 11.0 - - - pF CC [1] Typical values are measured at Tamb = 25 °C and VCC = 1.2 V, 1.8 V, 2.5 V, 2.7 V, and 3.3 V respectively. [2] tpd is the same as tPLH and tPHL. [3] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design. [4] CPD is used to determine the dynamic power dissipation (PD in μW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz CL = output load capacitance in pF VCC = supply voltage in Volts N = number of inputs switching Σ(CL × VCC2 × fo) = sum of the outputs 74LVC32A All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved Product data sheet Rev. 6 — 12 September 2018 6 / 14

Nexperia 74LVC32A Quad 2-input OR gate 10.1. Waveforms and test circuit tW VI 90 % negative pulse VM VM 10 % 0 V tf tr tr tf VI 90 % positive pulse VM VM 10 % 0 V tW VCC VI nA, nB input VM PULSE VI VO DUT GENERATOR GND RT CL RL tPHL tPLH 001aaf615 nY output VM Test data is given in Table 8. mna244 Definitions for test circuit: V = 1.5 V at V ≥ 2.7 V R = Load resistance. M CC L V = 0.5 × V at V < 2.7 V. C = Load capacitance including jig and probe M CC CC L V and V are typical output voltage levels that capacitance. OL OH occur with the output load. R = Termination resistance should be equal to T output impedance Z of the pulse generator. Fig. 7. The input nA, nB to output nY propagation o delays Fig. 8. Test circuit for measuring switching times Table 8. Test data Supply voltage Input Load V t, t C R I r f L L 1.2 V V ≤ 2 ns 30 pF 1 kΩ CC 1.65 V to 1.95 V V ≤ 2 ns 30 pF 1 kΩ CC 2.3 V to 2.7 V V ≤ 2 ns 30 pF 500 Ω CC 2.7 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω 3.0 V to 3.6 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω 74LVC32A All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved Product data sheet Rev. 6 — 12 September 2018 7 / 14

Nexperia 74LVC32A Quad 2-input OR gate 11. Package outline SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y H E v M A Z 14 8 Q A 2 A 1 (A 3 ) A pin 1 index θ L p 1 7 L e w M detail X b p 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mAax . A 1 A 2 A 3 b p c D (1) E (1) e H E L L p Q v w y Z (1) θ 0.25 1.45 0.49 0.25 8.75 4.0 6.2 1.0 0.7 0.7 mm 1.75 0.25 1.27 1.05 0.25 0.25 0.1 0.10 1.25 0.36 0.19 8.55 3.8 5.8 0.4 0.6 0.3 8 o 0.010 0.057 0.019 0.0100 0.35 0.16 0.244 0.039 0.028 0.028 0 o inches 0.069 0.01 0.05 0.041 0.01 0.01 0.004 0.004 0.049 0.014 0.0075 0.34 0.15 0.228 0.016 0.024 0.012 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE REFERENCES EUROPEAN ISSUE DATE VERSION IEC JEDEC JEITA PROJECTION 99-12-27 SOT108-1 076E06 MS-012 03-02-19 Fig. 9. Package outline SOT108-1 (SO14) 74LVC32A All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved Product data sheet Rev. 6 — 12 September 2018 8 / 14

Nexperia 74LVC32A Quad 2-input OR gate SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1 D E A X c y H E v M A Z 14 8 Q A 2 A 1 (A 3 ) A pin 1 index θ L p L 1 7 detail X w M e b p 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT mAax . A 1 A 2 A 3 b p c D (1) E (1) e H E L L p Q v w y Z (1) θ 0.21 1.80 0.38 0.20 6.4 5.4 7.9 1.03 0.9 1.4 8 o mm 2 0.05 1.65 0.25 0.25 0.09 6.0 5.2 0.65 7.6 1.25 0.63 0.7 0.2 0.13 0.1 0.9 0 o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE REFERENCES EUROPEAN ISSUE DATE VERSION IEC JEDEC JEITA PROJECTION 99-12-27 SOT337-1 MO-150 03-02-19 Fig. 10. Package outline SOT337-1 (SSOP14) 74LVC32A All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved Product data sheet Rev. 6 — 12 September 2018 9 / 14

Nexperia 74LVC32A Quad 2-input OR gate TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 D E A X c y H E v M A Z 14 8 Q A 2 (A 3 ) A pin 1 index A 1 θ L p L 1 7 detail X w M e b p 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT mAax . A 1 A 2 A 3 b p c D (1) E (2) e H E L L p Q v w y Z (1) θ 0.15 0.95 0.30 0.2 5.1 4.5 6.6 0.75 0.4 0.72 8 o mm 1.1 0.05 0.80 0.25 0.19 0.1 4.9 4.3 0.65 6.2 1 0.50 0.3 0.2 0.13 0.1 0.38 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE REFERENCES EUROPEAN ISSUE DATE VERSION IEC JEDEC JEITA PROJECTION 99-12-27 SOT402-1 MO-153 03-02-18 Fig. 11. Package outline SOT402-1 (TSSOP14) 74LVC32A All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved Product data sheet Rev. 6 — 12 September 2018 10 / 14

Nexperia 74LVC32A Quad 2-input OR gate DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.5 x 3 x 0.85 mm SOT762-1 D B A A A1 E c terminal 1 detail X index area terminal 1 C e1 index area e b v C A B y1C y w C 2 6 L 1 7 Eh e 14 8 k 13 9 Dh X k 0 2 4 mm scale Dimensions (mm are the original dimensions) Unit A(1) A1 b c D(1) Dh E(1) Eh e e1 k L v w y y1 max 1 0.05 0.30 3.1 1.65 2.6 1.15 0.5 mm nom 0.02 0.25 0.2 3.0 1.50 2.5 1.00 0.5 2 0.4 0.1 0.05 0.05 0.1 min 0.00 0.18 2.9 1.35 2.4 0.85 0.2 0.3 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. sot762-1_po Outline References European Issue date version IEC JEDEC JEITA projection 15-04-10 SOT762-1 MO-241 15-05-05 Fig. 12. Package outline SOT762-1 (DHVQFN14) 74LVC32A All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved Product data sheet Rev. 6 — 12 September 2018 11 / 14

Nexperia 74LVC32A Quad 2-input OR gate 12. Abbreviations Table 9. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 13. Revision history Table 10. Revision history Document ID Release date Data sheet status Change notice Supersedes 74LVC32A v.6 20180912 Product data sheet - 74LVC32A v.5 Modifications: • The format of this data sheet has been redesigned to comply with the identity guidelines of Nexperia. • Legal texts have been adapted to the new company name where appropriate. • Package outline drawing SOT762-1 updated. • Typo corrected in t value: 1.05 ns to 1.5 ns. pd 74LVC32A v.5 20111117 Product data sheet - 74LVC32A v.4 Modifications: • Legal pages updated. • Table 6, ΔI : condition V changed. CC CC 74LVC32A v.4 20111019 Product data sheet - 74LVC32A v.3 74LVC32A v.3 20030716 Product specification - 74LVC32A v.2 74LVC32A v.2 19970630 Product specification - 74LVC32A v.1 74LVC32A v.1 19970630 Product specification - - 74LVC32A All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved Product data sheet Rev. 6 — 12 September 2018 12 / 14

Nexperia 74LVC32A Quad 2-input OR gate injury, death or severe property or environmental damage. Nexperia and its 14. Legal information suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Quick reference data — The Quick reference data is an extract of the Data sheet status product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Document status Product Definition Applications — Applications that are described herein for any of these [1][2] status [3] products are for illustrative purposes only. Nexperia makes no representation Objective [short] Development This document contains data from or warranty that such applications will be suitable for the specified use data sheet the objective specification for without further testing or modification. product development. Customers are responsible for the design and operation of their applications and products using Nexperia products, and Nexperia accepts no liability for Preliminary [short] Qualification This document contains data from any assistance with applications or customer product design. It is customer’s data sheet the preliminary specification. sole responsibility to determine whether the Nexperia product is suitable Product [short] Production This document contains the product and fit for the customer’s applications and products planned, as well as data sheet specification. for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. [1] Please consult the most recently issued document before initiating or completing a design. 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This between the translated and English versions. document supersedes and replaces all information supplied prior to the publication hereof. Trademarks Suitability for use — Nexperia products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical Notice: All referenced brands, product names, service names and systems or equipment, nor in applications where failure or malfunction trademarks are the property of their respective owners. of an Nexperia product can reasonably be expected to result in personal 74LVC32A All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved Product data sheet Rev. 6 — 12 September 2018 13 / 14

Nexperia 74LVC32A Quad 2-input OR gate Contents 1. General description......................................................1 2. Features and benefits..................................................1 3. Ordering information....................................................1 4. Functional diagram.......................................................2 5. Pinning information......................................................2 5.1. Pinning.........................................................................2 5.2. Pin description.............................................................3 6. Functional description.................................................3 7. Limiting values.............................................................4 8. Recommended operating conditions..........................4 9. Static characteristics....................................................5 10. Dynamic characteristics............................................6 10.1. Waveforms and test circuit........................................7 11. Package outline..........................................................8 12. Abbreviations............................................................12 13. Revision history........................................................12 14. Legal information......................................................13 © Nexperia B.V. 2018. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 12 September 2018 74LVC32A All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved Product data sheet Rev. 6 — 12 September 2018 14 / 14