74LVC2G00 Dual 2-input NAND gate Rev. 15 — 3 July 2017 Product data sheet 1 General description The 74LVC2G00 provides a 2-input NAND gate function. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 V and 5 V environment. This device is fully specified for partial power-down applications using I . The I OFF OFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. 2 Features and benefits • Wide supply voltage range from 1.65 V to 5.5 V • 5 V tolerant outputs for interfacing with 5 V logic • High noise immunity • ±24 mA output drive (V = 3.0 V) CC • CMOS low power consumption • Complies with JEDEC standard: –JESD8-7 (1.65 V to 1.95 V) –JESD8-5 (2.3 V to 2.7 V) –JESD8-B/JESD36 (2.7 V to 3.6 V) • Latch-up performance exceeds 250 mA • Direct interface with TTL levels • Inputs accept voltages up to 5 V • ESD protection: –HBM JESD22-A114F exceeds 2 000 V –MM JESD22-A115-A exceeds 200 V • Multiple package options • Specified from -40 °C to +85 °C and -40 °C to +125 °C 3 Ordering information Table 1. Ordering information Type number Package Temperature Name Description Version range 74LVC2G00DP -40 °C to +125 °C TSSOP8 plastic thin shrink small outline package; 8 leads; SOT505-2 body width 3 mm; lead length 0.5 mm 74LVC2G00DC -40 °C to +125 °C VSSOP8 plastic very thin shrink small outline package; 8 leads; SOT765-1 body width 2.3 mm

Nexperia 74LVC2G00 Dual 2-input NAND gate Type number Package Temperature Name Description Version range 74LVC2G00GT -40 °C to +125 °C XSON8 plastic extremely thin small outline package; no leads; SOT833-1 8 terminals; body 1 x 1.95 x 0.5 mm 74LVC2G00GF -40 °C to +125 °C XSON8 extremely thin small outline package; no leads; SOT1089 8 terminals; body 1.35 x 1 x 0.5 mm 74LVC2G00GM -40 °C to +125 °C XQFN8 plastic, extremely thin quad flat package; no leads; SOT902-2 8 terminals; body 1.6 x 1.6 x 0.5 mm 74LVC2G00GN -40 °C to +125 °C XSON8 extremely thin small outline package; no leads; SOT1116 8 terminals; body 1.2 x 1.0 x 0.35 mm 74LVC2G00GS -40 °C to +125 °C XSON8 extremely thin small outline package; no leads; SOT1203 8 terminals; body 1.35 x 1.0 x 0.35 mm 74LVC2G00GX -40 °C to +125 °C X2SON8 plastic thermal enhanced extremely thin small outline SOT1233 package; no leads; 8 terminals; body 1.35 x 0.8 x 0.35 mm 4 Marking Table 2. Marking codes [1] Type number Marking code 74LVC2G00DP V2G00 74LVC2G00DC V00 74LVC2G00GT V00 74LVC2G00GF VA 74LVC2G00GM V00 74LVC2G00GN VA 74LVC2G00GS VA 74LVC2G00GX VA [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5 Functional diagram & 1A 1Y 1B B 2A & 2Y Y 2B A 001aah748 001aah749 mna099 Figure 1.  Logic symbol Figure 2.  IEC logic symbol Figure 3.  Logic diagram (one gate) 74LVC2G00 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved. Product data sheet Rev. 15 — 3 July 2017 2 / 21

Nexperia 74LVC2G00 Dual 2-input NAND gate 6 Pinning information 6.1 Pinning 74LVC2G00 1A 1 8 VCC 1B 2 7 1Y 74LVC2G00 2Y 3 6 2B 1A 1 8 VCC 1B 2 7 1Y GND 4 5 2A 2Y 3 6 2B 001aab737 GND 4 5 2A Transparenttopview 001aab736 Figure 5.  Pin configuration SOT833-1, SOT1089, Figure 4.  Pin configuration SOT505-2 and SOT765-1 SOT1116 and SOT1203 74LVC2G00 terminal1 C C indexarea V 8 74LVC2G00 1Y 1 7 1A 1A 1 7 1Y 8 2B 2 6 1B VCC 1B 2 6 2B 2A 3 5 2Y 4 4 GND D 2Y 3 5 2A GN 001aae980 aaa-023988 Transparenttopview Transparenttopview Figure 6.  Pin configuration SOT902-2 Figure 7.  Pin configuration SOT1233 74LVC2G00 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved. Product data sheet Rev. 15 — 3 July 2017 3 / 21

Nexperia 74LVC2G00 Dual 2-input NAND gate 6.2 Pin description Table 3. Pin description Symbol Pin Description SOT505-2, SOT765-1, SOT833-1, SOT1089, SOT902-2 SOT1116, SOT1203 and SOT1233 1A, 2A 1, 5 7, 3 data input 1B, 2B 2, 6 6, 2 data input GND 4 4 ground (0 V) 1Y, 2Y 7, 3 1, 5 data output V 8 8 supply voltage CC 7 Functional description Table 4. Function table H = HIGH voltage level; L = LOW voltage level. Input Output nA nB nY L L H L H H H L H H H L 74LVC2G00 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved. Product data sheet Rev. 15 — 3 July 2017 4 / 21

Nexperia 74LVC2G00 Dual 2-input NAND gate 8 Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit V supply voltage -0.5 +6.5 V CC [1] V input voltage -0.5 +6.5 V I [1] V output voltage Active mode -0.5 V + 0.5 V O CC [1][2] Power-down mode -0.5 +6.5 V I input clamping current V < 0 V -50 - mA IK I I output clamping current V < 0 V or V > V - ±50 mA OK O O CC I output current V = 0 V to V - ±50 mA O O CC I supply current - 100 mA CC I ground current -100 - mA GND T storage temperature -65 +150 °C stg [3] P total power dissipation T = -40 °C to +125 °C - 300 mW tot amb [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation. [3] For TSSOP8 package: above 55 °C the value of Ptot derates linearly with 2.5 mW/K. For VSSOP8 package: above 110 °C the value of Ptot derates linearly with 8 mW/K. For XSON8 and XQFN8 packages: above 118 °C the value of Ptot derates linearly with 7.8 mW/K. For X2SON8 package: above 118 °C the value of Ptot derates linearly with 7.7 mW/K. 9 Recommended operating conditions Table 6. Operating conditions Symbol Parameter Conditions Min Max Unit V supply voltage 1.65 5.5 V CC V input voltage 0 5.5 V I V output voltage Active mode 0 V V O CC Power-down mode 0 5.5 V T ambient temperature -40 +125 °C amb Δt/ΔV input transition rise and fall rate V = 1.65 V to 2.7 V - 20 ns/V CC V = 2.7 V to 5.5 V - 10 ns/V CC 74LVC2G00 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved. Product data sheet Rev. 15 — 3 July 2017 5 / 21

Nexperia 74LVC2G00 Dual 2-input NAND gate 10 Static characteristics Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). [1] Symbol Parameter Conditions Min Typ Max Unit T = -40 °C to +85 °C amb V HIGH-level input voltage V = 1.65 V to 1.95 V 0.65 x V - - V IH CC CC V = 2.3 V to 2.7 V 1.7 - - V CC V = 2.7 V to 3.6 V 2.0 - - V CC V = 4.5 V to 5.5 V 0.7 x V - - V CC CC V LOW-level input voltage V = 1.65 V to 1.95 V - - 0.35 x V V IL CC CC V = 2.3 V to 2.7 V - - 0.7 V CC V = 2.7 V to 3.6 V - - 0.8 V CC V = 4.5 V to 5.5 V - - 0.3 x V V CC CC V HIGH-level output voltage V = V or V OH I IH IL I = -100 μA; V = 1.65 V to 5.5 V V - 0.1 - - V O CC CC I = -4 mA; V = 1.65 V 1.2 1.53 - V O CC I = -8 mA; V = 2.3 V 1.9 2.13 - V O CC I = -12 mA; V = 2.7 V 2.2 2.50 - V O CC I = -24 mA; V = 3.0 V 2.3 2.60 - V O CC I = -32 mA; V = 4.5 V 3.8 4.10 - V O CC V LOW-level output voltage V = V or V OL I IH IL I = 100 μA; V = 1.65 V to 5.5 V - - 0.1 V O CC I = 4 mA; V = 1.65 V - 0.08 0.45 V O CC I = 8 mA; V = 2.3 V - 0.14 0.3 V O CC I = 12 mA; V = 2.7 V - 0.19 0.4 V O CC I = 24 mA; V = 3.0 V - 0.37 0.55 V O CC I = 32 mA; V = 4.5 V - 0.43 0.55 V O CC I input leakage current V = 5.5 V or GND; V = 0 V to 5.5 V - ±0.1 ±1 μA I I CC I power-off leakage current V or V = 5.5 V; V = 0 V - ±0.1 ±2 μA OFF I O CC I supply current V = 5.5 V or GND; - 0.1 4 μA CC I V = 1.65 V to 5.5 V; I = 0 A CC O ΔI additional supply current per pin; V = V - 0.6 V; - 5 500 μA CC I CC V = 2.3 V to 5.5 V; I = 0 A CC O C input capacitance - 2.5 - pF I 74LVC2G00 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved. Product data sheet Rev. 15 — 3 July 2017 6 / 21

Nexperia 74LVC2G00 Dual 2-input NAND gate [1] Symbol Parameter Conditions Min Typ Max Unit T = -40 °C to +125 °C amb V HIGH-level input voltage V = 1.65 V to 1.95 V 0.65 x V - - V IH CC CC V = 2.3 V to 2.7 V 1.7 - - V CC V = 2.7 V to 3.6 V 2.0 - - V CC V = 4.5 V to 5.5 V 0.7 x V - - V CC CC V LOW-level input voltage V = 1.65 V to 1.95 V - - 0.35 x V V IL CC CC V = 2.3 V to 2.7 V - - 0.7 V CC V = 2.7 V to 3.6 V - - 0.8 V CC V = 4.5 V to 5.5 V - - 0.3 x V V CC CC V HIGH-level output voltage V = V or V OH I IH IL I = -100 μA; V = 1.65 V to 5.5 V V - 0.1 - - V O CC CC I = -4 mA; V = 1.65 V 0.95 - - V O CC I = -8 mA; V = 2.3 V 1.7 - - V O CC I = -12 mA; V = 2.7 V 1.9 - - V O CC I = -24 mA; V = 3.0 V 2.0 - - V O CC I = -32 mA; V = 4.5 V 3.4 - - V O CC V LOW-level output voltage V = V or V OL I IH IL I = 100 μA; V = 1.65 V to 5.5 V - - 0.1 V O CC I = 4 mA; V = 1.65 V - - 0.70 V O CC I = 8 mA; V = 2.3 V - - 0.45 V O CC I = 12 mA; V = 2.7 V - - 0.60 V O CC I = 24 mA; V = 3.0 V - - 0.80 V O CC I = 32 mA; V = 4.5 V - - 0.80 V O CC I input leakage current V = 5.5 V or GND; V = 0 V to 5.5 V - - ±1 μA I I CC I power-off leakage current V or V = 5.5 V; V = 0 V - - ±2 μA OFF I O CC I supply current V = 5.5 V or GND; - - 4 μA CC I V = 1.65 V to 5.5 V; I = 0 A CC O ΔI additional supply current per pin; V = V - 0.6 V; - - 500 μA CC I CC V = 2.3 V to 5.5 V; I = 0 A CC O [1] All typical values are measured at Tamb = 25 °C. 74LVC2G00 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved. Product data sheet Rev. 15 — 3 July 2017 7 / 21

Nexperia 74LVC2G00 Dual 2-input NAND gate 11 Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground 0 V); for test circuit see Figure 9. Symbol Parameter Conditions -40 °C to +85 °C -40 °C to +125 °C Unit [1] Min Typ Max Min Max [2] t propagation delay nA, nB to nY; see Figure 8 pd V = 1.65 V to 1.95 V 1.2 3.5 8.6 1.2 10.8 ns CC V = 2.3 V to 2.7 V 0.7 2.3 4.8 0.7 6.0 ns CC V = 2.7 V 0.7 3.0 5.6 0.7 7.0 ns CC V = 3.0 V to 3.6 V 0.7 2.2 4.3 0.7 5.4 ns CC V = 4.5 V to 5.5 V 0.5 1.8 3.3 0.5 4.2 ns CC [3] C power dissipation per gate; V = GND to V - 14 - - - pF PD I CC capacitance [1] Typical values are measured at nominal VCC and at Tamb = 25 °C. [2] tpd is the same as tPLH and tPHL [3] CPD is used to determine the dynamic power dissipation (PD in μW). PD = CPD x VCC2 x fi x N + ∑(CL x VCC2 x fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; ∑(CL x VCC2 x fo) = sum of outputs. 11.1 Waveforms and test circuit VI nA,nBinput VM GND tPHL tPLH VOH nYoutput VM VOL 001aae972 Measurement points are given in Table 9. V and V are typical output voltage levels that occur with the output load. OL OH Figure 8.  Input (nA, nB) to output (nY) propagation delays 74LVC2G00 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved. Product data sheet Rev. 15 — 3 July 2017 8 / 21

Nexperia 74LVC2G00 Dual 2-input NAND gate Table 9. Measurement points Supply voltage Input Output V V V CC M M 1.65 V to 1.95 V 0.5 x V 0.5 x V CC CC 2.3 V to 2.7 V 0.5 x V 0.5 x V CC CC 2.7 V 1.5 V 1.5 V 3.0 V to 3.6 V 1.5 V 1.5 V 4.5 V to 5.5 V 0.5 x V 0.5 x V CC CC tW VI 90% negative pulse VM VM 10% 0V tf tr tr tf VI 90% positive pulse VM VM 10% 0V tW VEXT VCC RL VI VO PULSE DUT GENERATOR RT CL RL 001aae235 Test data is given in Table 10. Definitions for test circuit: R = Load resistance. L C = Load capacitance including jig and probe capacitance. L R = Termination resistance should be equal to output impedance Z of the pulse generator. T o V = Test voltage for switching times. EXT Figure 9.  Test circuit for measuring switching times Table 10. Test data Supply voltage Input Load V EXT V V t, t C R t , t CC I r f L L PLH PHL 1.65 V to 1.95 V V ≤ 2.0 ns 30 pF 1 kΩ open CC 2.3 V to 2.7 V V ≤ 2.0 ns 30 pF 500 Ω open CC 2.7 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω open 3.0 V to 3.6 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω open 4.5 V to 5.5 V V ≤ 2.5 ns 50 pF 500 Ω open CC 74LVC2G00 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved. Product data sheet Rev. 15 — 3 July 2017 9 / 21

Nexperia 74LVC2G00 Dual 2-input NAND gate 12 Package outline TSSOP8:plasticthinshrinksmalloutlinepackage;8leads;bodywidth3mm;leadlength0.5mm SOT505-2 D E A X c y HE v M A Z 8 5 A A2 A1 (A3) pin1index θ Lp L 1 4 detailX e w M bp 0 2.5 5mm scale DIMENSIONS(mmaretheoriginaldimensions) UNIT mAax. A1 A2 A3 bp c D(1) E(1) e HE L Lp v w y Z(1) θ 0.15 0.95 0.38 0.18 3.1 3.1 4.1 0.47 0.70 8° mm 1.1 0.25 0.65 0.5 0.2 0.13 0.1 0.00 0.75 0.22 0.08 2.9 2.9 3.9 0.33 0.35 0° Note 1.Plasticormetalprotrusionsof0.15mmmaximumpersidearenotincluded. OUTLINE REFERENCES EUROPEAN ISSUEDATE VERSION IEC JEDEC JEITA PROJECTION SOT505-2 --- 02-01-16 Figure 10.  Package outline SOT505-2 (TSSOP8) 74LVC2G00 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved. Product data sheet Rev. 15 — 3 July 2017 10 / 21

Nexperia 74LVC2G00 Dual 2-input NAND gate VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm SOT765-1 D E A X c y HE v A Z 8 5 Q A2 A pin 1 index A1 (A3) θ Lp 1 4 detail X L e w bp 0 5 mm scale Dimensions (mm are the original dimensions) A Unit max. A1 A2 A3 bp c D(1) E(2) e HE L Lp Q v w y Z(1) θ max 0.15 0.85 0.27 0.23 2.1 2.4 3.2 0.40 0.21 0.4 8° mm nom 1 0.12 0.5 0.4 0.2 0.08 0.1 min 0.00 0.60 0.17 0.08 1.9 2.2 3.0 0.15 0.19 0.1 0° Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. sot765-1_po Outline References European Issue date version IEC JEDEC JEITA projection 07-06-02 SOT765-1 MO-187 16-05-31 Figure 11.  Package outline SOT765-1 (VSSOP8) 74LVC2G00 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved. Product data sheet Rev. 15 — 3 July 2017 11 / 21

Nexperia 74LVC2G00 Dual 2-input NAND gate XSON8:plasticextremelythinsmalloutlinepackage;noleads;8terminals;body1x1.95x0.5mm SOT833-1 b 1 2 3 4 4× L1 L (2) e 8 7 6 5 e1 e1 e1 8× A (2) A1 D E terminal1 indexarea 0 1 2mm scale DIMENSIONS(mmaretheoriginaldimensions) UNIT mA(a1x) mAa1x b D E e e1 L L1 0.25 2.0 1.05 0.35 0.40 mm 0.5 0.04 0.6 0.5 0.17 1.9 0.95 0.27 0.32 Notes 1.Includingplatingthickness. 2.Canbevisibleinsomemanufacturingprocesses. OUTLINE REFERENCES EUROPEAN ISSUEDATE VERSION IEC JEDEC JEITA PROJECTION 07-11-14 SOT833-1 --- MO-252 --- 07-12-07 Figure 12.  Package outline SOT833-1 (XSON8) 74LVC2G00 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved. Product data sheet Rev. 15 — 3 July 2017 12 / 21

Nexperia 74LVC2G00 Dual 2-input NAND gate XSON8:extremelythinsmalloutlinepackage;noleads; 8terminals;body1.35x1x0.5mm SOT1089 E terminal1 indexarea D A A1 detailX (4×)(2) e L (8×)(2) b 4 5 e1 1 8 terminal1 indexarea L1 X 0 0.5 1mm scale Dimensions Unit A(1) A1 b D E e e1 L L1 max 0.5 0.04 0.20 1.40 1.05 0.35 0.40 mm nom 0.15 1.35 1.00 0.55 0.35 0.30 0.35 min 0.12 1.30 0.95 0.27 0.32 Note 1.Includingplatingthickness. 2.Visibledependinguponusedmanufacturingtechnology. sot1089_po Outline References European Issuedate version IEC JEDEC JEITA projection 10-04-09 SOT1089 MO-252 10-04-12 Figure 13.  Package outline SOT1089 (XSON8) 74LVC2G00 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved. Product data sheet Rev. 15 — 3 July 2017 13 / 21

Nexperia 74LVC2G00 Dual 2-input NAND gate XQFN8: plastic, extremely thin quad flat package; no leads; 8 terminals; body 1.6 x 1.6 x 0.5 mm SOT902-2 X D B A terminal 1 index area E A A1 detail X e C v C A B b w C y1C y 4 3 5 e1 terminal 1 index area 2 6 k L 1 7 8 metal area L2 not for soldering L k L3 L1 0 1 2 mm scale Dimensions Unit(1) A A1 b D E e e1 k L L1 L2 L3 v w y y1 max 0.5 0.05 0.25 1.65 1.65 0.35 0.15 0.25 0.35 mm nom 0.20 1.60 1.60 0.55 0.5 0.30 0.10 0.20 0.30 0.1 0.05 0.05 0.05 min 0.00 0.15 1.55 1.55 0.2 0.25 0.05 0.15 0.25 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. sot902-2_po Outline References European Issue date version IEC JEDEC JEITA projection 16-07-14 SOT902-2 - - - MO-255 - - - 16-11-08 Figure 14.  Package outline SOT902-2 (XQFN8) 74LVC2G00 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved. Product data sheet Rev. 15 — 3 July 2017 14 / 21

Nexperia 74LVC2G00 Dual 2-input NAND gate XSON8:extremelythinsmalloutlinepackage;noleads; 8terminals;body1.2x1.0x0.35mm SOT1116 b 1 2 3 4 (4×)(2) L1 L e 8 7 6 5 e1 e1 e1 (8×)(2) A1 A D E terminal1 indexarea 0 0.5 1mm scale Dimensions Unit A(1) A1 b D E e e1 L L1 max 0.35 0.04 0.20 1.25 1.05 0.35 0.40 mm nom 0.15 1.20 1.00 0.55 0.3 0.30 0.35 min 0.12 1.15 0.95 0.27 0.32 Note 1.Includingplatingthickness. 2.Visibledependinguponusedmanufacturingtechnology. sot1116_po Outline References European Issuedate version IEC JEDEC JEITA projection 10-04-02 SOT1116 10-04-07 Figure 15.  Package outline SOT1116 (XSON8) 74LVC2G00 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved. Product data sheet Rev. 15 — 3 July 2017 15 / 21

Nexperia 74LVC2G00 Dual 2-input NAND gate XSON8:extremelythinsmalloutlinepackage;noleads; 8terminals;body1.35x1.0x0.35mm SOT1203 b 1 2 3 4 (4×)(2) L1 L e 8 7 6 5 e1 e1 e1 (8×)(2) A1 A D E terminal1 indexarea 0 0.5 1mm scale Dimensions Unit A(1) A1 b D E e e1 L L1 max 0.35 0.04 0.20 1.40 1.05 0.35 0.40 mm nom 0.15 1.35 1.00 0.55 0.35 0.30 0.35 min 0.12 1.30 0.95 0.27 0.32 Note 1.Includingplatingthickness. 2.Visibledependinguponusedmanufacturingtechnology. sot1203_po Outline References European Issuedate version IEC JEDEC JEITA projection 10-04-02 SOT1203 10-04-06 Figure 16.  Package outline SOT1203 (XSON8) 74LVC2G00 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved. Product data sheet Rev. 15 — 3 July 2017 16 / 21

Nexperia 74LVC2G00 Dual 2-input NAND gate X2SON8: plastic thermal enhanced extremely thin small outline package; no leads; 8 terminals; body 1.35 x 0.8 x 0.35 mm SOT1233 X A D B A E A1 detail X pin 1 index area e e C v C A B b y 1 2 (6x) 3 w C pin 1 index area 8 4 Dh L (6x) 7 6 5 (2bx1) y1C e1 0 1 mm scale Dimensions (mm are the original dimensions) Unit A A1 b b1 D Dh E e e1 L v w y y1 max 0.35 0.04 0.25 1.40 0.27 0.85 0.27 mm nom 0.32 0.20 0.15 1.35 0.22 0.80 0.5 0.54 0.22 0.1 0.05 0.05 0.05 min 0.30 0.00 0.15 (ref) 1.30 0.17 0.75 0.17 sot1233_po Outline References European Issue date version IEC JEDEC JEITA projection 16-04-21 SOT1233 --- 17-01-05 Figure 17.  Package outline SOT1233 (X2SON8) 74LVC2G00 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved. Product data sheet Rev. 15 — 3 July 2017 17 / 21

Nexperia 74LVC2G00 Dual 2-input NAND gate 13 Abbreviations Table 11. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 14 Revision history Table 12. Revision history Document ID Release date Data sheet status Change notice Supersedes 74LVC2G00 v.15 20170703 Product data sheet - 74LVC2G00 v.14 Modifications: • The format of this data sheet has been redesigned to comply with the identity guidelines of Nexperia. • Legal texts have been adapted to the new company name where appropriate. • Figure 17: Package outline drawing for SOT1233 has changed. • Type number 74LVC2G00GD removed. 74LVC2G00 v.14 20161212 Product data sheet - 74LVC2G00 v.13 Modifications: • Table 7: The maximum limits for leakage current and supply current have changed. 74LVC2G00 v.13 20161028 Product data sheet - 74LVC2G00 v.12 Modifications: • Added type number 74LVC2G00GX (SOT1233/X2SON8) 74LVC2G00 v.12 20130408 Product data sheet - 74LVC2G00 v.11 Modifications: • For type number 74LVC2G00GD XSON8U has changed to XSON8. 74LVC2G00 v.11 20120622 Product data sheet - 74LVC2G00 v.10 Modifications: • For type number 74LVC2G00GM the SOT code has changed to SOT902-2. 74LVC2G00 v.10 20111130 Product data sheet - 74LVC2G00 v.9 Modifications: • Legal pages updated. 74LVC2G00 v.9 20100608 Product data sheet - 74LVC2G00 v.8 74LVC2G00 v.8 20091026 Product data sheet - 74LVC2G00 v.7 74LVC2G00 v.7 20080610 Product data sheet - 74LVC2G00 v.6 74LVC2G00 v.6 20080220 Product data sheet - 74LVC2G00 v.5 74LVC2G00 v.5 20070904 Product data sheet - 74LVC2G00 v.4 74LVC2G00 v.4 20060515 Product data sheet - 74LVC2G00 v.3 74LVC2G00 v.3 20050201 Product specification - 74LVC2G00 v.2 74LVC2G00 v.2 20040923 Product specification - 74LVC2G00 v.1 74LVC2G00 v.1 20031117 Product specification - - 74LVC2G00 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved. Product data sheet Rev. 15 — 3 July 2017 18 / 21

Nexperia 74LVC2G00 Dual 2-input NAND gate 15 Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term 'short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nexperia.com. systems or equipment, nor in applications where failure or malfunction of an Nexperia product can reasonably be expected to result in personal 15.2 Definitions injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in Draft — The document is a draft version only. The content is still under such equipment or applications and therefore such inclusion and/or use is at internal review and subject to formal approval, which may result in the customer’s own risk. modifications or additions. Nexperia does not give any representations or warranties as to the accuracy or completeness of information included herein Applications — Applications that are described herein for any of these and shall have no liability for the consequences of use of such information. products are for illustrative purposes only. Nexperia makes no representation or warranty that such applications will be suitable for the specified use Short data sheet — A short data sheet is an extract from a full data sheet without further testing or modification. Customers are responsible for the with the same product type number(s) and title. A short data sheet is design and operation of their applications and products using Nexperia intended for quick reference only and should not be relied upon to contain products, and Nexperia accepts no liability for any assistance with detailed and full information. For detailed and full information see the applications or customer product design. It is customer’s sole responsibility relevant full data sheet, which is available on request via the local Nexperia to determine whether the Nexperia product is suitable and fit for the sales office. In case of any inconsistency or conflict with the short data sheet, customer’s applications and products planned, as well as for the planned the full data sheet shall prevail. application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks Product specification — The information and data provided in a Product associated with their applications and products. Nexperia does not accept data sheet shall define the specification of the product as agreed between any liability related to any default, damage, costs or problem which is based Nexperia and its customer, unless Nexperia and customer have explicitly on any weakness or default in the customer’s applications or products, or agreed otherwise in writing. In no event however, shall an agreement be the application or use by customer’s third party customer(s). Customer is valid in which the Nexperia product is deemed to offer functions and qualities responsible for doing all necessary testing for the customer’s applications beyond those described in the Product data sheet. and products using Nexperia products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). Nexperia does not accept any liability in this respect. 15.3 Disclaimers Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent Limited warranty and liability — Information in this document is believed damage to the device. Limiting values are stress ratings only and (proper) to be accurate and reliable. However, Nexperia does not give any operation of the device at these or any other conditions above those representations or warranties, expressed or implied, as to the accuracy given in the Recommended operating conditions section (if present) or the or completeness of such information and shall have no liability for the Characteristics sections of this document is not warranted. Constant or consequences of use of such information. Nexperia takes no responsibility repeated exposure to limiting values will permanently and irreversibly affect for the content in this document if provided by an information source outside the quality and reliability of the device. of Nexperia. In no event shall Nexperia be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal Terms and conditions of commercial sale — Nexperia products are or replacement of any products or rework charges) whether or not such sold subject to the general terms and conditions of commercial sale, as damages are based on tort (including negligence), warranty, breach of published at http://www.nexperia.com/profile/terms, unless otherwise agreed contract or any other legal theory. Notwithstanding any damages that in a valid written individual agreement. In case an individual agreement is customer might incur for any reason whatsoever, Nexperia's aggregate and concluded only the terms and conditions of the respective agreement shall cumulative liability towards customer for the products described herein shall apply. Nexperia hereby expressly objects to applying the customer’s general be limited in accordance with the Terms and conditions of commercial sale of terms and conditions with regard to the purchase of Nexperia products by Nexperia. customer. Right to make changes — Nexperia reserves the right to make changes No offer to sell or license — Nothing in this document may be interpreted to information published in this document, including without limitation or construed as an offer to sell products that is open for acceptance or specifications and product descriptions, at any time and without notice. This the grant, conveyance or implication of any license under any copyrights, document supersedes and replaces all information supplied prior to the patents or other industrial or intellectual property rights. publication hereof. Export control — This document as well as the item(s) described herein Suitability for use — Nexperia products are not designed, authorized or may be subject to export control regulations. Export might require a prior warranted to be suitable for use in life support, life-critical or safety-critical authorization from competent authorities. 74LVC2G00 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved. Product data sheet Rev. 15 — 3 July 2017 19 / 21

Nexperia 74LVC2G00 Dual 2-input NAND gate Non-automotive qualified products — Unless this data sheet expressly design and use of the product for automotive applications beyond Nexperia's states that this specific Nexperia product is automotive qualified, the standard warranty and Nexperia's product specifications. product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. Nexperia Translations — A non-English (translated) version of a document is for accepts no liability for inclusion and/or use of non-automotive qualified reference only. The English version shall prevail in case of any discrepancy products in automotive equipment or applications. In the event that customer between the translated and English versions. uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without Nexperia's warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for 15.4 Trademarks automotive applications beyond Nexperia's specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies Nexperia Notice: All referenced brands, product names, service names and for any liability, damages or failed product claims resulting from customer trademarks are the property of their respective owners. 74LVC2G00 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved. Product data sheet Rev. 15 — 3 July 2017 20 / 21

Nexperia 74LVC2G00 Dual 2-input NAND gate Contents 1 General description ............................................1 2 Features and benefits .........................................1 3 Ordering information ..........................................1 4 Marking .................................................................2 5 Functional diagram .............................................2 6 Pinning information ............................................3 6.1 Pinning ...............................................................3 6.2 Pin description ...................................................4 7 Functional description ........................................4 8 Limiting values ....................................................5 9 Recommended operating conditions ................5 10 Static characteristics ..........................................6 11 Dynamic characteristics .....................................8 11.1 Waveforms and test circuit ................................8 12 Package outline .................................................10 13 Abbreviations ....................................................18 14 Revision history ................................................18 15 Legal information ..............................................19 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section 'Legal information'. © Nexperia B.V. 2017. All rights reserved. For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 3 July 2017 Document identifier: 74LVC2G00