74LVC00A Quad 2-input NAND gate Rev. 7 — 25 April 2012 Product data sheet 1. General description The 74LVC00A provides four 2-input NAND gates. Schmitt trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V applications. 2. Features and benefits  5 V tolerant inputs for interfacing with 5 V logic  Wide supply voltage range from 1.2Vto3.6V  CMOS low-power consumption  Direct interface with TTL levels  Complies with JEDEC standard: JESD8-7A (1.65Vto1.95V) JESD8-5A (2.3Vto2.7V) JESD8-C/JESD36 (2.7Vto3.6V)  ESD protection: HBM JESD22-A114F exceeds 2000V MM JESD22-A115-B exceeds 200V CDM JESD22-C101E exceeds 1000V  Specified from −40 °C to +85 °C and −40 °C to +125 °C 3. Ordering information Table 1. Ordering info rmation Type number Package Temperature range Name Description Version 74LVC00AD −40°Cto+125°C SO14 plastic small outline package; 14leads; SOT108-1 bodywidth3.9mm 74LVC00ADB −40°Cto+125°C SSOP14 plastic shrink small outline package; 14leads; SOT337-1 bodywidth5.3mm 74LVC00APW −40°Cto+125°C TSSOP14 plastic thin shrink small outline package; 14leads; SOT402-1 bodywidth4.4mm 74LVC00ABQ −40°Cto+125°C DHVQFN14 plastic dual in-line compatible thermal enhanced very SOT762-1 thin quad flat package; no leads; 14terminals; body2.5×3×0.85mm

74LVC00A Nexperia Quad 2-input NAND gate 4. Functional diagram 1 1 1A 1Y 3 2 & 3 2 1B 4 4 2A & 6 2Y 6 5 5 2B 9 3A 9 3Y 8 & 8 10 3B 10 A 12 4A 4Y 11 12 Y 13 4B & 11 13 B mna212 mna246 mna211 Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram for one gate 5. Pinning information 5.1 Pinning C terminal 1 A C index area 1 V 1 14 1B 2 13 4B 1A 1 14 VCC 1Y 3 12 4A 1B 2 13 4B 1Y 3 12 4A 2A 4 00 11 4Y 2A 4 00 11 4Y 2B 5 GND(1) 10 3B 2B 5 10 3B 2Y 6 9 3A 2Y 6 9 3A 7 8 GND 7 8 3Y D Y N 3 001aac939 G 001aac938 Transparent top view (1) This is not a supply pin. The substrate is attached to this pad using conductive die attach material. There is no electrical or mechanical requirement to solder this pad. However, if it is soldered, the solder land should remain floating or be connected to GND. Fig 4. Pin configuration SO14 and (T)SSOP14 Fig 5. Pin configuration DHVQFN14 5.2 Pin description Table 2. Pin descripti on Symbol Pin Description 1A to 4A 1, 4, 9, 12 data input 1B to 4B 2, 5, 10, 13 data input 1Y to 4Y 3, 6, 8,11 data output GND 7 ground (0 V) V 14 supply voltage CC 74LVC00A All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved Product data sheet Rev. 7 — 25 April 2012 2 of 14

74LVC00A Nexperia Quad 2-input NAND gate 6. Functional description Table 3. Function sel ection[1] Input Output nA nB nY L X H X L H H H L [1] H=HIGH voltage level; L=LOW voltage level; X=don’t care 7. Limiting values Table 4. Limiting valu es In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit V supply voltage −0.5 +6.5 V CC I input clamping current V < 0 V −50 - mA IK I V input voltage [1] −0.5 +6.5 V I I output clamping current V > V or V < 0 V - ±50 mA OK O CC O V output voltage output in HIGH or LOW-state [2] −0.5 V + 0.5 V O CC I output current V = 0 V to V - ±50 mA O O CC I supply current - 100 mA CC I ground current −100 - mA GND P total power dissipation T = −40°C to+125°C [3] - 500 mW tot amb T storage temperature −65 +150 °C stg [1] The minimum input voltage ratings may be exceeded if the input current ratings are observed. [2] The output voltage ratings may be exceeded if the output current ratings are observed. [3] For SO14 packages: above 70°C derate linearly with 8mW/K. For (T)SSOP14 packages: above 60°C derate linearly with 5.5mW/K. For DHVQFN14 packages: above 60°C derate linearly with 4.5mW/K. 8. Recommended operating conditions Table 5. Recommend ed operating conditions Symbol Parameter Conditions Min Typ Max Unit V supply voltage 1.65 - 3.6 V CC functional 1.2 - - V V input voltage 0 - 5.5 V I V output voltage output HIGH or LOW state 0 - V V O CC T ambient temperature −40 - +125 °C amb Δt/ΔV input transition rise and V = 1.65 V to 2.7 V 0 - 20 ns/V CC fall rate V = 2.7 V to 3.6 V 0 - 10 ns/V CC 74LVC00A All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved Product data sheet Rev. 7 — 25 April 2012 3 of 14

74LVC00A Nexperia Quad 2-input NAND gate 9. Static characteristics Table 6. Static charac teristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions −40 °C to +85 °C −40 °C to +125 °C Unit Min Typ[1] Max Min Max V HIGH-level V = 1.2 V 1.08 - - 1.08 - V IH CC input voltage V = 1.65 V to 1.95 V 0.65 × V - - 0.65 × V - V CC CC CC V = 2.3 V to 2.7 V 1.7 - - 1.7 - V CC V = 2.7 V to 3.6 V 2.0 - - 2.0 - V CC V LOW-level V = 1.2 V - - 0.12 - 0.12 V IL CC input voltage V = 1.65 V to 1.95 V - - 0.35 × V - 0.35 × V V CC CC CC V = 2.3 V to 2.7 V - - 0.7 - 0.7 V CC V = 2.7 V to 3.6 V - - 0.8 - 0.8 V CC V HIGH-level V =V orV OH I IH IL output I =−100μA; V −0.2 - - V −0.3 - V O CC CC voltage V =1.65Vto3.6V CC I =−4mA; V = 1.65 V 1.2 - - 1.05 - V O CC I =−8mA; V = 2.3V 1.8 - - 1.65 - V O CC I =−12mA; V = 2.7 V 2.2 - - 2.05 - V O CC I =−18mA; V = 3.0 V 2.4 - - 2.25 - V O CC I =−24mA; V = 3.0 V 2.2 - - 2.0 - V O CC V LOW-level V =V orV OL I IH IL output I =100μA; - - 0.2 - 0.3 V O voltage V =1.65Vto3.6 V CC I =4mA; V = 1.65 V - - 0.45 - 0.65 V O CC I =8mA; V = 2.3V - - 0.6 - 0.8 V O CC I =12mA; V = 2.7 V - - 0.4 - 0.6 V O CC I =24mA; V = 3.0 V - - 0.55 - 0.8 V O CC I input leakage V = 3.6 V; V =5.5VorGND - ±0.1 ±5 - ±20 μA I CC I current I supply V = 3.6 V; V =V orGND; - 0.1 10 - 40 μA CC CC I CC current I =0A O ΔI additional per input pin; - 5 500 - 5000 μA CC supply V =2.7Vto3.6V; CC current V =V −0.6V; I =0A I CC O C input V =0 V to 3.6V; - 4.0 - - - pF I CC capacitance V =GNDtoV I CC [1] All typical values are measured at V =3.3V (unless stated otherwise) and T =25°C. CC amb 74LVC00A All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved Product data sheet Rev. 7 — 25 April 2012 4 of 14

74LVC00A Nexperia Quad 2-input NAND gate 10. Dynamic characteristics Table 7. Dynamic cha racteristics Voltages are referenced to GND (ground=0V). For test circuit see Figure7. Symbol Parameter Conditions −40 °C to +85 °C −40 °C to +125 °C Unit Min Typ[1] Max Min Max t propagation delay nA,nBtonY; see Figure6 [2] pd V =1.2V - 12 - - - ns CC V =1.65Vto1.95V 0.3 3.8 8.4 0.3 9.7 ns CC V =2.3Vto2.7V 1.0 2.2 4.8 1.0 5.7 ns CC V =2.7V 1.0 2.3 5.1 1.0 5.9 ns CC V =3.0V to3.6V 0.5 2.0 4.3 0.5 5.1 ns CC t output skew time V =3.0V to 3.6V [3] - - 1.0 - 1.5 ns sk(o) CC C power dissipation per gate; V =GNDtoV [4] PD I CC capacitance V = 1.65 V to 1.95 V - 5.6 - - - pF CC V = 2.3 V to 2.7 V - 8.9 - - - pF CC V = 3.0 V to 3.6 V - 11.8 - - - pF CC [1] Typical values are measured at T =25°C and V = 1.2 V, 1.8 V, 2.5 V, 2.7 V, and 3.3 V respectively. amb CC [2] t is the same as t and t . pd PLH PHL [3] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design. [4] C is used to determine the dynamic power dissipation (P inμW). PD D P =C ×V 2×f ×N+Σ(C ×V 2×f )where: D PD CC i L CC o f = input frequency in MHz; f =output frequency in MHz i o C =output load capacitance inpF L V =supply voltage in Volts CC N= number of inputs switching Σ(CL×VCC2×fo)=sum of the outputs 11. Waveforms VI nA, nB input VM GND tPHL tPLH VOH nY output VM VOL mna213 V =1.5V at V ≥2.7V. M CC VM=0.5 ×VCC at VCC<2.7V. V and V are typical output voltage levels that occur with the output load. OL OH Fig 6. The input (nA, nB) to output (nY) propagation delays 74LVC00A All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved Product data sheet Rev. 7 — 25 April 2012 5 of 14

74LVC00A Nexperia Quad 2-input NAND gate tW VI 90 % negative pulse VM VM 10 % 0 V tf tr tr tf VI 90 % positive pulse VM VM 10 % 0 V tW VCC VI VO PULSE DUT GENERATOR RT CL RL 001aaf615 Test data is given in Table8. Definitions for test circuit: RL = Load resistance CL = Load capacitance including jig and probe capacitance R = Termination resistance should be equal to output impedance Z of the pulse generator T o Fig 7. Load circuitry for measuring switching times Table 8. Test data Supply voltage Input Load V t, t C R I r f L L 1.2V V ≤ 2 ns 30pF 1 kΩ CC 1.65Vto1.95V V ≤ 2 ns 30pF 1 kΩ CC 2.3Vto2.7V V ≤ 2 ns 30pF 500Ω CC 2.7V 2.7V ≤ 2.5ns 50pF 500Ω 3.0Vto3.6V 2.7V ≤ 2.5ns 50pF 500Ω 74LVC00A All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved Product data sheet Rev. 7 — 25 April 2012 6 of 14

74LVC00A Nexperia Quad 2-input NAND gate 12. Package outline SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y HE v M A Z 14 8 Q A2 A1 (A 3 ) A pin 1 index θ Lp 1 7 L e w M detail X bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mAax. A1 A2 A3 bp c D(1) E(1) e HE L Lp Q v w y Z(1) θ 0.25 1.45 0.49 0.25 8.75 4.0 6.2 1.0 0.7 0.7 mm 1.75 0.25 1.27 1.05 0.25 0.25 0.1 0.10 1.25 0.36 0.19 8.55 3.8 5.8 0.4 0.6 0.3 8o 0.010 0.057 0.019 0.0100 0.35 0.16 0.244 0.039 0.028 0.028 0o inches 0.069 0.01 0.05 0.041 0.01 0.01 0.004 0.004 0.049 0.014 0.0075 0.34 0.15 0.228 0.016 0.024 0.012 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE REFERENCES EUROPEAN ISSUE DATE VERSION IEC JEDEC JEITA PROJECTION 99-12-27 SOT108-1 076E06 MS-012 03-02-19 Fig 8. Package outline SOT108-1 (SO14) 74LVC00A All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved Product data sheet Rev. 7 — 25 April 2012 7 of 14

74LVC00A Nexperia Quad 2-input NAND gate SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1 D E A X c y HE v M A Z 14 8 Q A2 A1 (A 3 ) A pin 1 index θ Lp L 1 7 detail X w M e bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT mAax. A1 A2 A3 bp c D(1) E(1) e HE L Lp Q v w y Z(1) θ mm 2 00..2015 11..8605 0.25 00..3285 00..2009 66..40 55..42 0.65 77..96 1.25 10..0633 00..97 0.2 0.13 0.1 10..49 80oo Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE REFERENCES EUROPEAN ISSUE DATE VERSION IEC JEDEC JEITA PROJECTION 99-12-27 SOT337-1 MO-150 03-02-19 Fig 9. Package outline SOT337-1 (SSOP14) 74LVC00A All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved Product data sheet Rev. 7 — 25 April 2012 8 of 14

74LVC00A Nexperia Quad 2-input NAND gate TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 D E A X c y HE v M A Z 14 8 Q A2 (A 3 ) A pin 1 index A1 θ Lp L 1 7 detail X w M e bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT mAax. A1 A2 A3 bp c D(1) E(2) e HE L Lp Q v w y Z(1) θ mm 1.1 00..1055 00..9850 0.25 00..3109 00..21 54..19 44..53 0.65 66..62 1 00..7550 00..43 0.2 0.13 0.1 00..7328 80oo Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE REFERENCES EUROPEAN ISSUE DATE VERSION IEC JEDEC JEITA PROJECTION 99-12-27 SOT402-1 MO-153 03-02-18 Fig 10. Package outline SOT402-1 (TSSOP14) 74LVC00A All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved Product data sheet Rev. 7 — 25 April 2012 9 of 14

74LVC00A Nexperia Quad 2-input NAND gate DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.5 x 3 x 0.85 mm SOT762-1 D B A A A1 E c terminal 1 detail X index area terminal 1 e1 C index area e b v M C A B y1 C y w M C 2 6 L 1 7 Eh e 14 8 13 9 Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) A(1) UNIT max. A1 b c D(1) Dh E(1) Eh e e1 L v w y y1 0.05 0.30 3.1 1.65 2.6 1.15 0.5 mm 1 0.2 0.5 2 0.1 0.05 0.05 0.1 0.00 0.18 2.9 1.35 2.4 0.85 0.3 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE REFERENCES EUROPEAN ISSUE DATE VERSION IEC JEDEC JEITA PROJECTION 02-10-17 SOT762-1 - - - MO-241 - - - 03-01-27 Fig 11. Package outline SOT762-1 (DHVQFN14) 74LVC00A All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved Product data sheet Rev. 7 — 25 April 2012 10 of 14

74LVC00A Nexperia Quad 2-input NAND gate 13. Abbreviations Table 9. Abbreviation s Acronym Description CDM Charged Device Model DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 14. Revision history T able 10. Revision history Document ID Release date Data sheet status Change notice Supersedes 74LVC00A v.7 20120425 Product data sheet - 74LVC00A v.6 Modifications: • Table2: Errata in pin description corrected. 74LVC00A v.6 20120106 Product data sheet - 74LVC00A v.5 Modifications: • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Table4, Table5, Table6, Table7 and Table8: values added for lower voltage ranges. 74LVC00A v.5 20030904 Product specification - 74LVC00A v.4 74LVC00A v.4 20030507 Product specification - 74LVC00A v.3 74LVC00A v.3 20020305 Product specification - 74LVC00A v.2 74LVC00A v.2 19980428 Product specification - 74LVC00A v.1 74LVC00A v.1 19970811 Product specification - - 74LVC00A All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved Product data sheet Rev. 7 — 25 April 2012 11 of 14

74LVC00A Nexperia Quad 2-input NAND gate 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nexperia.com. 15.2 Definitions Suitability for use — Nexperia products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or Draft — The document is a draft version only. The content is still under malfunction of a Nexperia product can reasonably be expected internal review and subject to formal approval, which may result in to result in personal injury, death or severe property or environmental modifications or additions. Nexperia does not give any damage. Nexperia and its suppliers accept no liability for representations or warranties as to the accuracy or completeness of inclusion and/or use of Nexperia products in such equipment or information included herein and shall have no liability for the consequences of applications and therefore such inclusion and/or use is at the customer’s own use of such information. risk. Short data sheet — A short data sheet is an extract from a full data sheet Applications — Applications that are described herein for any of these with the same product type number(s) and title. A short data sheet is intended products are for illustrative purposes only. Nexperia makes no for quick reference only and should not be relied upon to contain detailed and representation or warranty that such applications will be suitable for the full information. For detailed and full information see the relevant full data specified use without further testing or modification. sheet, which is available on request via the local Nexperia sales office. In case of any inconsistency or conflict with the short data sheet, the Customers are responsible for the design and operation of their applications full data sheet shall prevail. and products using Nexperia products, and Nexperia accepts no liability for any assistance with applications or customer product Product specification — The information and data provided in a Product design. It is customer’s sole responsibility to determine whether the Nexperia data sheet shall define the specification of the product as agreed between product is suitable and fit for the customer’s applications and Nexperia and its customer, unless Nexperia and products planned, as well as for the planned application and use of customer have explicitly agreed otherwise in writing. In no event however, customer’s third party customer(s). Customers should provide appropriate shall an agreement be valid in which the Nexperia product is design and operating safeguards to minimize the risks associated with their deemed to offer functions and qualities beyond those described in the applications and products. Product data sheet. Nexperia does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the 15.3 Disclaimers customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using Nexperia Limited warranty and liability — Information in this document is believed to products in order to avoid a default of the applications and be accurate and reliable. However, Nexperia does not give any the products or of the application or use by customer’s third party representations or warranties, expressed or implied, as to the accuracy or customer(s). Nexperia does not accept any liability in this respect. completeness of such information and shall have no liability for the consequences of use of such information. Nexperia takes no Limiting values — Stress above one or more limiting values (as defined in responsibility for the content in this document if provided by an information the Absolute Maximum Ratings System of IEC60134) will cause permanent source outside of Nexperia. damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in In no event shall Nexperia be liable for any indirect, incidental, the Recommended operating conditions section (if present) or the punitive, special or consequential damages (including - without limitation - lost Characteristics sections of this document is not warranted. Constant or profits, lost savings, business interruption, costs related to the removal or repeated exposure to limiting values will permanently and irreversibly affect replacement of any products or rework charges) whether or not such the quality and reliability of the device. damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Terms and conditions of commercial sale — Nexperia products are sold subject to the general terms and conditions of commercial Notwithstanding any damages that customer might incur for any reason whatsoever, Nexperia’s aggregate and cumulative liability towards sale, as published at http://www.nexperia.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual customer for the products described herein shall be limited in accordance agreement is concluded only the terms and conditions of the respective with the Terms and conditions of commercial sale of Nexperia. agreement shall apply. Nexperia hereby expressly objects to Right to make changes — Nexperia reserves the right to make applying the customer’s general terms and conditions with regard to the changes to information published in this document, including without purchase of Nexperia products by customer. limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior No offer to sell or license — Nothing in this document may be interpreted or to the publication hereof. construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 74LVC00A All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved Product data sheet Rev. 7 — 25 April 2012 12 of 14

74LVC00A Nexperia Quad 2-input NAND gate Export control — This document as well as the item(s) described herein Nexperia’s specifications such use shall be solely at customer’s may be subject to export control regulations. Export might require a prior own risk, and (c) customer fully indemnifies Nexperia for any authorization from competent authorities. liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond Nexperia’s Non-automotive qualified products — Unless this data sheet expressly standard warranty and Nexperia’s product specifications. states that this specific Nexperia product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested Translations — A non-English (translated) version of a document is for in accordance with automotive testing or application requirements. Nexperia reference only. The English version shall prevail in case of any discrepancy accepts no liability for inclusion and/or use of between the translated and English versions. non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in 15.4 Trademarks automotive applications to automotive specifications and standards, customer (a) shall use the product without Nexperia’s warranty of the Notice: All referenced brands, product names, service names and trademarks product for such automotive applications, use and specifications, and (b) are the property of their respective owners. whenever customer uses the product for automotive applications beyond 16. Contact information For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com 74LVC00A All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved Product data sheet Rev. 7 — 25 April 2012 13 of 14

74LVC00A Nexperia Quad 2-input NAND gate 17. Contents 1 General description. . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information. . . . . . . . . . . . . . . . . . . . . 1 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 2 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 Functional description . . . . . . . . . . . . . . . . . . . 3 7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3 8 Recommended operating conditions. . . . . . . . 3 9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4 10 Dynamic characteristics. . . . . . . . . . . . . . . . . . 5 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 12 Package outline. . . . . . . . . . . . . . . . . . . . . . . . . 7 13 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 11 14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 11 15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 12 15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 12 15.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 15.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 12 15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 13 16 Contact information. . . . . . . . . . . . . . . . . . . . . 13 17 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 © Nexperia B.V. 2017. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 25 April 2012