74LV4094 8-stage shift-and-store bus register Rev. 6 — 14 November 2018 Product data sheet 1. General description The 74LV4094 is a low voltage Si-gate CMOS device and is pin and functional compatible with 74HC4094; 74HCT4094. The 74LV4094 is an 8-stage serial shift register. It has a storage latch associated with each stage for strobing data from the serial input to parallel buffered 3-state outputs QP0 to QP7. The parallel outputs may be connected directly to common bus lines. Data is shifted on positive-going clock transitions. The data in each shift register stage is transferred to the storage register when the strobe (STR) input is HIGH. Data in the storage register appears at the outputs whenever the output enable (OE) signal is HIGH. Two serial outputs (QS1 and QS2) are available for cascading a number of 74LV4094 devices. Serial data is available at QS1 on positive-going clock edges to allow high-speed operation in cascaded systems with a fast clock rise time. The same serial data is available at QS2 on the next negative going clock edge. This is used for cascading 74LV4094 devices when the clock has a slow rise time. 2. Features and benefits • Optimized for low voltage applications: 1.0 V to 3.6 V • Accepts TTL input levels between V = 2.7 V and V = 3.6 V CC CC • Typical output ground bounce < 0.8 V at V = 3.3 V and T = 25 °C CC amb • Typical HIGH-level output voltage (V ) undershoot: > 2 V at V = 3.3 V and T = 25 °C OH CC amb • ESD protection: • HBM JESD22-A114E exceeds 2000 V • MM JESD22-A115-A exceeds 200 V • Multiple package options • Specified from -40 °C to +85 °C and from -40 °C to +125 °C 3. Applications • Serial-to-parallel data conversion • Remote control holding register 4. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LV4094D -40 °C to +125 °C SO16 plastic small outline package; 16 leads; SOT109-1 body width 3.9 mm 74LV4094DB -40 °C to +125 °C SSOP16 plastic shrink small outline package; 16 leads; SOT338-1 body width 5.3 mm 74LV4094PW -40 °C to +125 °C TSSOP16 plastic thin shrink small outline package; 16 leads; SOT403-1 body width 4.4 mm

Nexperia 74LV4094 8-stage shift-and-store bus register 5. Functional diagram 3 1 1 C2 15 CP STR EN3 QS1 9 SRG8 QS2 10 3 C1/ QP0 4 2 4 1D 2D 3 QP1 5 5 QP2 6 6 2 D 7 QP3 7 14 QP4 14 13 QP5 13 12 QP6 12 11 QP7 11 9 OE 10 15 001aaf111 001aaf112 Fig. 1. Functional diagram Fig. 2. Logic symbol D 2 8-STAGE SHIFT QS2 10 CP REGISTER 3 QS1 9 STR 8-BIT STORAGE 1 REGISTER OE 15 3-STATE OUTPUTS QP0 QP1 QP2 QP3 QP4 QP5 QP6 QP7 4 5 6 7 14 13 12 11 001aaf119 Fig. 3. Logic diagram 74LV4094 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved Product data sheet Rev. 6 — 14 November 2018 2 / 17

Nexperia 74LV4094 8-stage shift-and-store bus register STAGE 0 STAGES 1 TO 6 STAGE 7 D D Q D Q D Q QS1 CP CP FF 0 FF 7 D Q QS2 CP CP LE LATCH D Q D Q LE LE LATCH 0 LATCH 7 STR OE QP0 QP2 QP4 QP6 001aag799 QP1 QP3 QP5 QP7 Fig. 4. Logic diagram 6. Pinning information 6.1. Pinning 74LV4094 STR 1 16 VCC D 2 15 OE CP 3 14 QP4 QP0 4 13 QP5 QP1 5 12 QP6 QP2 6 11 QP7 QP3 7 10 QS2 GND 8 9 QS1 001aan680 Fig. 5. Pin configuration SOT109-1 (SO16), SOT338-1 (SSOP16) and SOT403-1 (TSSOP16) 6.2. Pin description Table 2. Pin description Symbol Pin Description STR 1 strobe input D 2 data input CP 3 clock input QP0 to QP7 4, 5, 6, 7, 14, 13, 12, 11 parallel output GND 8 ground supply voltage QS1, QS2 9,10 serial output OE 15 output enable input V 16 supply voltage CC 74LV4094 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved Product data sheet Rev. 6 — 14 November 2018 3 / 17

Nexperia 74LV4094 8-stage shift-and-store bus register 7. Functional description Table 3. Function table H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = HIGH-impedance OFF-state; NC = no change; ↑ = positive-going transition; ↓ = negative-going transition; Q6S = the data in register stage 6 before the LOW to HIGH clock transition; Q7S = the data in register stage 7 before the HIGH to LOW clock transition. Inputs Parallel outputs Serial outputs CP OE STR D QP0 QPn QS1 QS2 ↑ L X X Z Z Q6S NC ↓ L X X Z Z NC Q7S ↑ H L X NC NC Q6S NC ↑ H H L L QPn -1 Q6S NC ↑ H H H H QPn -1 Q6S NC ↓ H H H NC NC NC Q7S CLOCK INPUT DATA INPUT STROBE INPUT OUTPUT ENABLE INPUT INTERNAL Q0S (FF 0) Z-state OUTPUT QP0 INTERNAL Q6S (FF 6) Z-state OUTPUT QP6 SERIAL OUTPUT QS1 SERIAL OUTPUT QS2 001aaf117 At the positive clock edge, the information in the 7th register stage is transferred to the 8th register stage and the QSn outputs. Fig. 6. Timing diagram 74LV4094 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved Product data sheet Rev. 6 — 14 November 2018 4 / 17

Nexperia 74LV4094 8-stage shift-and-store bus register 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit V supply voltage -0.5 +7 V CC I input clamping current V < -0.5 V or V > V + 0.5 V - ±20 mA IK I I CC I output clamping current V < -0.5 V or V > V + 0.5 V - ±50 mA OK O O CC I output current V = -0.5 V to (V + 0.5 V) - ±25 mA O O CC I supply current - +50 mA CC I ground current -50 - mA GND T storage temperature -65 +150 °C stg P total power dissipation T = -40 °C to +125 °C tot amb SO16 package [1] - 500 mW (T)SSOP16 package [2] - 500 mW [1] For SO16 package: Ptot derates linearly with 8 mW/K above 70 °C. [2] For SSOP16 and TSSOP16 packages: Ptot derates linearly with 5.5 mW/K above 60 °C. 9. Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit V supply voltage [1] 1.0 3.3 3.6 V CC V input voltage 0 - V V I CC V output voltage 0 - V V O CC T ambient temperature -40 +25 +125 °C amb Δt/ΔV input transition rise and fall rate V = 1.0 V to 2.0 V - - 500 ns/V CC V = 2.0 V to 2.7 V - - 200 ns/V CC V = 2.7 V to 3.6 V - - 100 ns/V CC [1] The static characteristics are guaranteed from VCC = 1.2 V to VCC = 5.5 V, but LV devices are guaranteed to function down to VCC = 1.0 V (with input levels GND or VCC). 74LV4094 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved Product data sheet Rev. 6 — 14 November 2018 5 / 17

Nexperia 74LV4094 8-stage shift-and-store bus register 10. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions -40 °C to 85 °C -40 °C to +125 °C Unit Min Typ[1] Max Min Max V HIGH-level input V = 1.2 V V 0.6 - V - V IH CC CC CC voltage V = 2.0 V 1.4 - - 1.4 - V CC V = 2.7 V to 3.6 V 2.0 - - 2.0 - V CC V LOW-level input V = 1.2 V - 0.4 GND - GND V IL CC voltage V = 2.0 V - - 0.6 - 0.6 V CC V = 2.7 V to 3.6 V - - 0.8 - 0.8 V CC V HIGH-level output V = V or V ; all pins OH I IH IL voltage I = -100 μA; V = 1.2 V - 1.2 - - - V O CC I = -100 μA; V = 2.0 V 1.8 2.0 - 1.8 - V O CC I = -100 μA; V = 2.7 V 2.5 2.7 - 2.5 - V O CC I = -100 μA; V = 3.0 V 2.8 3.0 - 2.8 - V O CC V = V or V ; pins QPn I IH IL I = -6 mA; V = 3.0 V 2.40 2.82 - 2.20 - V O CC V LOW-level output V = V or V ; all pins OL I IH IL voltage I = 100 μA; V = 1.2 V - 0 - - - V O CC I = 100 μA; V = 2.0 V - 0 0.2 - 0.2 V O CC I = 100 μA; V = 2.7 V - 0 0.2 - 0.2 V O CC I = 100 μA; V = 3.0 V - 0 0.2 - 0.2 V O CC V = V or V ; pins QPn I IH IL I = 6 mA; V = 3.0 V - 0.25 0.40 - 0.50 V O CC I input leakage V = V or GND; V = 3.6 V - - ±1.0 - ±1.0 μA I I CC CC current I OFF-state output V = V or V ; V = V or GND; - - ±5.0 - ±10.0 μA OZ I IH IL O CC current V = 3.6 V CC I supply current V = V or GND; I = 0 A; - - 20.0 - 160 μA CC I CC O V = 3.6 V CC ΔI additional supply per input; V = V - 0.6 V; - - 500.0 - 850 μA CC I CC current V = 2.7 V to 3.6 V CC C input capacitance - 3.5 - - - pF I [1] All typical values are measured at Tamb = 25 °C. 74LV4094 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved Product data sheet Rev. 6 — 14 November 2018 6 / 17

Nexperia 74LV4094 8-stage shift-and-store bus register 11. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); C = 50 pF unless otherwise specified; for test circuit see Fig. 11. L Symbol Parameter Conditions -40 °C to 85 °C -40 °C to +125 °C Unit Min Typ[1] Max Min Max t propagation CP to QS1; see Fig. 7 [2] pd delay V = 1.2 V - 90 - - - ns CC V = 2.0 V - 31 58 - 70 ns CC V = 2.7 V - 23 43 - 51 ns CC V = 3.0 V to 3.6 V [3] - 17 34 - 41 ns CC V = 3.3 V; C = 15 pF - 14 - - - ns CC L CP to QS2; see Fig. 7 [2] V = 1.2 V - 80 - - - ns CC V = 2.0 V - 27 51 - 61 ns CC V = 2.7 V - 20 38 - 45 ns CC V = 3.0 V to 3.6 V - 14 30 - 36 ns CC V = 3.3 V; C = 15 pF [3] - 13 - - - ns CC L CP to QPn; see Fig. 7 [2] V = 1.2 V - 115 - - - ns CC V = 2.0 V - 39 75 - 90 ns CC V = 2.7 V - 29 55 - 66 ns CC V = 3.0 V to 3.6 V [3] - 22 44 - 53 ns CC V = 3.3 V; C = 15 pF - 18 - - - ns CC L STR to QPn; see Fig. 8 [2] V = 1.2 V - 105 - - - ns CC V = 2.0 V - 36 68 - 82 ns CC V = 2.7 V - 26 50 - 60 ns CC V = 3.0 V to 3.6 V [3] - 20 40 - 48 ns CC V = 3.3 V; C = 15 pF - 17 - - - ns CC L t enable time OE to QPn; see Fig. 9 [2] en V = 1.2 V - 100 - - - ns CC V = 2.0 V - 34 65 - 77 ns CC V = 2.7 V - 25 48 - 56 ns CC V = 3.0 V to 3.6 V [3] - 19 38 - 45 ns CC t disable time OE to QPn; see Fig. 9 [2] dis V = 1.2 V - 65 - - - ns CC V = 2.0 V - 24 40 - 49 ns CC V = 2.7 V - 18 32 - 37 ns CC V = 3.0 V to 3.6 V [3] - 14 26 - 30 ns CC 74LV4094 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved Product data sheet Rev. 6 — 14 November 2018 7 / 17

Nexperia 74LV4094 8-stage shift-and-store bus register Symbol Parameter Conditions -40 °C to 85 °C -40 °C to +125 °C Unit Min Typ[1] Max Min Max t pulse width CP HIGH or LOW; see Fig. 7 W V = 2.0 V 34 9 - 41 - ns CC V = 2.7 V 25 6 - 30 - ns CC V = 3.0 V to 3.6 V [3] 20 5 - 24 - ns CC STR HIGH; see Fig. 8 V = 2.0 V 34 9 - 41 - ns CC V = 2.7 V 25 6 - 30 - ns CC V = 3.0 V to 3.6 V [3] 20 5 - 24 - ns CC t set-up time D to CP; see Fig. 10 su V = 1.2 V - 25 - - - ns CC V = 2.0 V 22 9 - 26 - ns CC V = 2.7 V 16 6 - 19 - ns CC V = 3.0 V to 3.6 V [3] 13 5 - 15 - ns CC CP to STR; see Fig. 8 V = 1.2 V - 50 - - - ns CC V = 2.0 V 43 17 - 51 - ns CC V = 2.7 V 31 13 - 38 - ns CC V = 3.0 V to 3.6 V [3] 25 10 - 30 - ns CC t hold time D to CP; see Fig. 10 h V = 1.2 V - -10 - - - ns CC V = 2.0 V 5 -4 - +5 - ns CC V = 2.7 V 5 -3 - +5 - ns CC V = 3.0 V to 3.6 V [3] 5 -2 - +5 - ns CC CP to STR; see Fig. 8 V = 1.2 V - -25 - - - ns CC V = 2.0 V 5 -9 - +5 - ns CC V = 2.7 V 5 -6 - +5 - ns CC V = 3.0 V to 3.6 V [3] 5 -5 - +5 - ns CC f maximum CP; see Fig. 7 max frequency V = 2.0 V 14 52 - 12 - MHz CC V = 2.7 V 19 70 - 16 - MHz CC V = 3.0 V to 3.6 V [3] 24 87 - 20 - MHz CC V = 3.3 V; C = 15 pF - 95 - - - MHz CC L C power C = 50 pF; f = 1 MHz; [4] - 83 - - - pF PD L dissipation V = GND to V I CC capacitance [1] All typical values are measured at Tamb = 25 °C. [2] tpd is the same as tPLH and tPHL; ten is the same as tPZH and tPZL; tdis is the same as tPLZ and tPHZ. [3] All typical values are measured at VCC = 3.3 V. [4] CPD is used to determine the dynamic power dissipation (PD in μW). PD = CPD x VCC2 x fi x N + ∑(CL x VCC2 x fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; ∑(CL x VCC2 x fo) = sum of outputs. 74LV4094 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved Product data sheet Rev. 6 — 14 November 2018 8 / 17

Nexperia 74LV4094 8-stage shift-and-store bus register 11.1. Waveforms and test circuit 1/fmax VI CP input VM GND tW tPLH tPHL VOH QPn, QS1 output VM VOL tPLH tPHL VOH QS2 output VM VOL 001aaf113 Measurement points are given in Table 8. V and V are typical voltage output levels that occur with the output load. OL OH Fig. 7. Propagation delay input (CP) to output (QPn, QS1, QS2), output transition time, clock input (CP) pulse width and the maximum frequency (CP) VI CP input VM GND tsu th VI STR input VM GND tW tPLH tPHL VOH QPn output VM VOL 001aaf114 Measurement points are given in Table 8. V and V are typical voltage output levels that occur with the output load. OL OH Fig. 8. Propagation delay strobe input (STR) to output (QPn), strobe input (STR) pulse width and the clock set-up and hold times for strobe input 74LV4094 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved Product data sheet Rev. 6 — 14 November 2018 9 / 17

Nexperia 74LV4094 8-stage shift-and-store bus register VI OE input VM GND tPZL tPLZ VCC output LOW-to-OFF VM OFF-to-LOW VOL VX tPHZ tPZH outputV OH VY HIGH-to-OFF VM OFF-to-HIGH GND outputs outputs outputs enabled disabled enabled 001aaf116 Measurement points are given in Table 8. V and V are typical voltage output levels that occur with the output load. OL OH Fig. 9. Enable and disable times VI CP input VM GND tsu tsu th th VI D input VM GND VOH QPn, QS1, QS2 output VM VOL 001aaf115 Measurement points are given in Table 8. V and V are typical voltage output levels that occur with the output load. OL OH Fig. 10. The data input (D) to clock input (CP) set-up times and clock input (CP) to data input (D) hold times Table 8. Measurement points Supply voltage Input Output V V V V V CC M M X Y < 2.7 V 0.5V 0.5V V + 0.1V V - 0.1V CC CC OL CC OH CC 2.7 V to 3.6 V 1.5 V 1.5 V V + 0.3 V V - 0.3 V OL OH 74LV4094 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved Product data sheet Rev. 6 — 14 November 2018 10 / 17

Nexperia 74LV4094 8-stage shift-and-store bus register tW VI 90 % negative pulse VM VM 10 % 0 V tf tr tr tf VI 90 % positive pulse VM VM 10 % 0 V tW VEXT VCC RL VI VO G DUT RT CL RL 001aae331 Test data is given in Table 9. Definitions for test circuit: R = Load resistance. L C = Load capacitance including jig and probe capacitance. L R = Termination resistance should be equal to output impedance Z of the pulse generator. T o V = External voltage for measuring switching times. EXT Fig. 11. Test circuit for measuring switching times Table 9. Test data Supply voltage Input Load V EXT V V t, t C R t , t t , t t , t CC I r f L L PHL PLH PZH PHZ PZL PLZ < 2.7 V V ≤ 2.5 ns 50 pF 1 kΩ open GND 2V CC CC 2.7 V to 3.6 V 2.7 V ≤ 2.5 ns 15 pF, 50 pF 1 kΩ open GND 2V CC 74LV4094 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved Product data sheet Rev. 6 — 14 November 2018 11 / 17

Nexperia 74LV4094 8-stage shift-and-store bus register 12. Package outline SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y H E v M A Z 16 9 Q A 2 A 1 (A 3 ) A pin 1 index θ L p 1 8 L e w M detail X b p 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mAax . A 1 A 2 A 3 b p c D (1) E (1) e H E L L p Q v w y Z (1) θ 0.25 1.45 0.49 0.25 10.0 4.0 6.2 1.0 0.7 0.7 mm 1.75 0.25 1.27 1.05 0.2 5 0.25 0.1 0.10 1.25 0.36 0.19 9.8 3.8 5.8 0.4 0.6 0.3 8 o 0.010 0.057 0.019 0.0100 0.39 0.16 0.244 0.039 0.028 0.028 0 o inches 0.069 0.01 0.05 0.041 0.01 0.01 0.004 0.004 0.049 0.014 0.0075 0.38 0.15 0.228 0.016 0.020 0.012 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE REFERENCES EUROPEAN ISSUE DATE VERSION IEC JEDEC JEITA PROJECTION 99-12-27 SOT109-1 076E07 MS-012 03-02-19 Fig. 12. Package outline SOT109-1 (SO16) 74LV4094 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved Product data sheet Rev. 6 — 14 November 2018 12 / 17

Nexperia 74LV4094 8-stage shift-and-store bus register SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1 D E A X c y H E v M A Z 16 9 Q A 2 A 1 (A 3 ) A pin 1 index θ L p L 1 8 detail X w M e b p 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT mAax . A 1 A 2 A 3 b p c D (1) E (1) e H E L L p Q v w y Z (1) θ 0.21 1.80 0.38 0.20 6.4 5.4 7.9 1.03 0.9 1.00 8 o mm 2 0.05 1.65 0.25 0.25 0.09 6.0 5.2 0.65 7.6 1.25 0.63 0.7 0.2 0.13 0.1 0.55 0 o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE REFERENCES EUROPEAN ISSUE DATE VERSION IEC JEDEC JEITA PROJECTION 99-12-27 SOT338-1 MO-150 03-02-19 Fig. 13. Package outline SOT338-1 (SSOP16) 74LV4094 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved Product data sheet Rev. 6 — 14 November 2018 13 / 17

Nexperia 74LV4094 8-stage shift-and-store bus register TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 D E A X c y H E v M A Z 16 9 Q A 2 (A 3 ) A pin 1 index A 1 θ L p L 1 8 detail X w M e b p 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT mAax . A 1 A 2 A 3 b p c D (1) E (2) e H E L L p Q v w y Z (1) θ 0.15 0.95 0.30 0.2 5.1 4.5 6.6 0.75 0.4 0.40 8 o mm 1.1 0.05 0.80 0.25 0.19 0.1 4.9 4.3 0.65 6.2 1 0.50 0.3 0.2 0.13 0.1 0.06 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE REFERENCES EUROPEAN ISSUE DATE VERSION IEC JEDEC JEITA PROJECTION 99-12-27 SOT403-1 MO-153 03-02-18 Fig. 14. Package outline SOT403-1 (TSSOP16) 74LV4094 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved Product data sheet Rev. 6 — 14 November 2018 14 / 17

Nexperia 74LV4094 8-stage shift-and-store bus register 13. Abbreviations Table 10. Abbreviations Acronym Description CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 14. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74LV4094 v.6 20181114 Product data sheet - 74LV4094 v.5 Modifications: • The format of this data sheet has been redesigned to comply with the identity guidelines of Nexperia. • Legal texts have been adapted to the new company name where appropriate. • Fig. 6 corrected. 74LV4094 v.5 20160318 Product data sheet - 74LV4094 v.4 Modifications: • Type number 74LV4094N (SOT38-4) removed. 74LV4094 v.4 20111219 Product data sheet - 74LV4094 v.3 Modifications: • Legal pages updated. 74LV4094 v.3 20110307 Product data sheet - 74LV4094 v.2 74LV4094 v.2 20060629 Product data sheet - 74LV4094 v.1 74LV4094 v.1 19980623 Product specification - - 74LV4094 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved Product data sheet Rev. 6 — 14 November 2018 15 / 17

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Nexperia’s specifications such use shall be solely at customer’s own risk, Notwithstanding any damages that customer might incur for any reason and (c) customer fully indemnifies Nexperia for any liability, damages or failed whatsoever, Nexperia’s aggregate and cumulative liability towards customer product claims resulting from customer design and use of the product for for the products described herein shall be limited in accordance with the automotive applications beyond Nexperia’s standard warranty and Nexperia’s Terms and conditions of commercial sale of Nexperia. product specifications. Right to make changes — Nexperia reserves the right to make changes Translations — A non-English (translated) version of a document is for to information published in this document, including without limitation reference only. The English version shall prevail in case of any discrepancy specifications and product descriptions, at any time and without notice. This between the translated and English versions. document supersedes and replaces all information supplied prior to the publication hereof. Trademarks Suitability for use — Nexperia products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical Notice: All referenced brands, product names, service names and systems or equipment, nor in applications where failure or malfunction trademarks are the property of their respective owners. of an Nexperia product can reasonably be expected to result in personal 74LV4094 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved Product data sheet Rev. 6 — 14 November 2018 16 / 17

Nexperia 74LV4094 8-stage shift-and-store bus register Contents 1. General description......................................................1 2. Features and benefits..................................................1 3. Applications..................................................................1 4. Ordering information....................................................1 5. Functional diagram.......................................................2 6. Pinning information......................................................3 6.1. Pinning.........................................................................3 6.2. Pin description.............................................................3 7. Functional description.................................................4 8. Limiting values.............................................................5 9. Recommended operating conditions..........................5 10. Static characteristics..................................................6 11. Dynamic characteristics.............................................7 11.1. Waveforms and test circuit........................................9 12. Package outline........................................................12 13. Abbreviations............................................................15 14. Revision history........................................................15 15. Legal information......................................................16 © Nexperia B.V. 2018. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 14 November 2018 74LV4094 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved Product data sheet Rev. 6 — 14 November 2018 17 / 17