Is Now Part of To learn more about ON Semiconductor, please visit our website at www.onsemi.com Please note: As part of the Fairchild Semiconductor integration, some of the Fairchild orderable part numbers will need to change in order to meet ON Semiconductor’s system requirements. Since the ON Semiconductor product management systems do not have the ability to manage part nomenclature that utilizes an underscore (_), the underscore (_) in the Fairchild part numbers will be changed to a dash (-). This document may contain device numbers with an underscore (_). Please check the ON Semiconductor website to verify the updated device numbers. The most current and up-to-date ordering information can be found at www.onsemi.com. Please email any questions regarding the system integration to Fairchild_questions@onsemi.com. ON Semiconductor and the ON Semiconductor logo are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

7 4 L C X December 2013 7 4 — L 74LCX74 o w Low Voltage Dual D-Type Positive Edge-Triggered V o l Flip-Flop with 5V Tolerant Inputs t a g e D Features General Description u a ■ 5V tolerant inputs The LCX74 is a dual D-type flip-flop with Asynchronous l D ■■ 27..30Vns– 3t.6V m VaCxC. (sVpeci=fi c3a.3tiVon),s 1 p0rµoAvi dIed max. CInlfeoarmr aantido nS eatt itnhpeu tisn pauntd i sc otrmapnlsefmererendta troy (tQhe, Qou) topuuttpsu otsn. -Ty PD CC CC the positive edge of the clock pulse. After the Clock p ■ Power down high impedance inputs and outputs e Pulse input threshold voltage has been passed, the Data ■ ±24mA output drive (VCC = 3.0V) input is locked out and information present will not be Po ■ Implements proprietary noise/EMI reduction circuitry transferred to the outputs until the next rising edge of the s i ■ Latch-up performance exceeds JEDEC 78 conditions Clock Pulse input. ti v ■ ESD performance: Asynchronous Inputs: e E – Human body model > 2000V ■ LOW input to S (Set) sets Q to HIGH level d – Machine model > 200V D g ■ LOW input to C (Clear) sets Q to LOW level e ■ Leadless Pb-Free DQFN package ■ Clear and Set aDre independent of clock -T r i ■ Simultaneous LOW on C and S makes both Q g D D g and Q HIGH e r e d F Ordering Information li p - Package F l Order Number Number Package Description o p 74LCX74M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" w Narrow it h 74LCX74SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 5 V 74LCX74BQX(1) MLP14A 14-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), T JEDEC MO-241, 2.5 x 3.0mm o l e 74LCX74MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, r a 4.4mm Wide n t Note: I n 1. DQFN package available in Tape and Reel only. p u Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number. t s All packages are lead free per JEDEC: J-STD-020B standard. ©1995 Fairchild Semiconductor Corporation www.fairchildsemi.com 74LCX74 Rev. 1.7.1

7 4 Connection Diagrams Logic Symbols L C X Pin Assignments for SOIC, SOP, and TSSOP 7 4 — L o w V o l t a g e D u a l D IEEE/IEC -T y p Pad Assignment for DQFN e P o s i t i v e E d g e - T r i g g e r e Truth Table d F (Each Half) li p (Top View) (Bottom View) Inputs Outputs -F l o S C CP D Q Q p D D w L H X X H L Pin Description it h H L X X L H 5 Pin Names Description L L X X H H V T D1, D2 Data Inputs H H H H L o l CP1, CP2 Clock Pulse Inputs H H L L H er a CD1, CD2 Direct Clear Inputs H H L X Q0 Q0 nt SD1, SD2 Direct Set Inputs H = HIGH Voltage Level In p Q1, Q1, Q2, Q2 Outputs L = LOW Voltage Level u t DAP No Connect X = Immaterial s Note: DAP (Die Attach Pad) = LOW-to-HIGH Clock Transition Q (Q ) = Previous Q(Q) before LOW-to-HIGH Transition 0 0 of Clock ©1995 Fairchild Semiconductor Corporation www.fairchildsemi.com 74LCX74 Rev. 1.7.1 2

7 4 Absolute Maximum Ratings L C Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be X 7 operable above the recommended operating conditions and stressing the parts to these levels is not recommended. 4 In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. — The absolute maximum ratings are stress ratings only. L o Symbol Parameter Rating w V Supply Voltage –0.5V to +7.0V V CC o VI DC Input Voltage –0.5V to +7.0V lta V DC Output Voltage, Output in HIGH or LOW State(2) –0.5V to V + 0.5V g O CC e I DC Input Diode Current, V < GND –50mA D IK I u I DC Output Diode Current a OK l V < GND –50mA D O - V > V +50mA T O CC y p IO DC Output Source/Sink Current ±50mA e I DC Supply Current per Supply Pin ±100mA P CC o I DC Ground Current per Ground Pin ±100mA s GND i t i T Storage Temperature –65°C to +150°C v STG e Note: E d 2. IO Absolute Maximum Rating must be observed. g e - T r Recommended Operating Conditions(3) ig g The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended e r operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not e recommend exceeding them or designing to absolute maximum ratings. d F Symbol Parameter Min. Max. Units li p - V Supply Voltage F CC l o Operating 2.0 3.6 V p Data Retention 1.5 3.6 w i t V Input Voltage 0 5.5 V h I 5 VO Output Voltage, HIGH or LOW State 0 VCC V V IOH / IOL Output Current To VCC = 3.0V–3.6V ±24 mA le r V = 2.7V–3.0V ±12 a CC n V = 2.3V–2.7V ±8 t CC I n T Free-Air Operating Temperature –40 85 °C p A u ∆t / ∆V Input Edge Rate, VIN = 0.8V–2.0V, VCC = 3.0V 0 10 ns / V ts Note: 3. Unused inputs must be held HIGH or LOW. They may not float. ©1995 Fairchild Semiconductor Corporation www.fairchildsemi.com 74LCX74 Rev. 1.7.1 3

7 4 DC Electrical Characteristics L C X TA = –40°C to +85°C 7 4 Symbol Parameter VCC (V) Conditions Min. Max. Units — VIH HIGH Level Input Voltage 2.3–2.7 1.7 V L o 2.7–3.6 2.0 w V LOW Level Input Voltage 2.3–2.7 0.7 V V IL o l 2.7–3.6 0.8 t a V HIGH Level Output Voltage 2.3–3.6 I = –100µA V – 0.2 V g OH OH CC e 2.3 I = –8mA 1.8 D OH u 2.7 I = –12mA 2.2 a OH l 3.0 I = –18mA 2.4 D OH - IOH = –24mA 2.2 Ty p VOL LOW Level Output Voltage 2.3–3.6 IOL = 100µA 0.2 V e 2.3 I = 8mA 0.6 P OL o 2.7 IOL = 12mA 0.4 sit i 3.0 I = 16mA 0.4 v OL e I = 24mA 0.55 E OL d I Input Leakage Current 2.3–3.6 0 ≤ V ≤ 5.5V ±5.0 µA g I I e I Power-Off Leakage Current 0 V or V = 5.5V 10 µA - OFF I O T r ICC Quiescent Supply Current 2.3–3.6 VI = VCC or GND 10 µA ig g 3.6V ≤ VI ≤ 5.5V ±10 e r ∆I Increase in I per Input 2.3–3.6 V = V – 0.6V 500 µA e CC CC IH CC d F l i p AC Electrical Characteristics - F l T = –40°C to +85°C, R = 500Ω o A L p V = 3.3V ± 0.3V, V = 2.7V, V = 2.5V ± 0.2V, w CC CC CC CL = 50pF CL = 50pF CL = 30pF ith Symbol Parameter Min. Max. Min. Max. Min. Max. Units 5 V f Maximum Clock Frequency 150 150 150 MHz T MAX o l t , t Propagation Delay, 1.5 7.0 1.5 8.0 1.5 8.4 ns e PHL PLH r CP to Q or Q a n n n n t , t Propagation Delay, 1.5 7.0 1.5 8.0 1.5 8.4 ns t PHL PLH I C or S to Q or Q n Dn Dn n n p t Setup Time 2.5 2.5 4.0 ns u S t s t Hold Time 1.5 1.5 2.0 ns H t Pulse Width CP 3.3 3.3 4.0 ns W t Pulse Width and C , S 3.3 3.6 4.0 ns W D D t Recovery Time 2.5 3.0 4.5 ns REC t , t Output to Output Skew(4) 1.0 ns OSHL OSLH Note: 4. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t ) or LOW-to-HIGH (t ). OSHL OSLH ©1995 Fairchild Semiconductor Corporation www.fairchildsemi.com 74LCX74 Rev. 1.7.1 4

7 4 Dynamic Switching Characteristics L C X TA = 25°C 7 4 Symbol Parameter VCC (V) Conditions Typical Unit — VOLP Quiet Output Dynamic Peak VOL 3.3 CL = 50pF, VIH = 3.3V, VIL = 0V 0.8 V L o 2.5 CL = 30pF, VIH = 2.5V, VIL = 0V 0.6 w V Quiet Output Dynamic Valley V 3.3 C = 50pF, V = 3.3V, V = 0V –0.8 V V OLV OL L IH IL o 2.5 C = 30pF, V = 2.5V, V = 0V –0.6 lt L IH IL a g e D u Capacitance a l D Symbol Parameter Conditions Typical Units - T CIN Input Capacitance VCC = Open, VI = 0V or VCC 7 pF yp e COUT Output Capacitance VCC = 3.3V, VI = 0V or VCC 8 pF P C Power Dissipation Capacitance V = 3.3V, V = 0V or V , f = 10MHz 25 pF o PD CC I CC s i t i v e E d g e - T r i g g e r e d F l i p - F l o p w i t h 5 V T o l e r a n t I n p u t s ©1995 Fairchild Semiconductor Corporation www.fairchildsemi.com 74LCX74 Rev. 1.7.1 5

7 4 AC Loading and Waveforms (Generic for LCX Family) LC X 7 Test Switch 4 — t , t Open PLH PHL L tPZL, tPLZ 6V at VCC = 3.3 ± 0.3V o V x 2 at V = 2.5 ± 0.2V w CC CC V t , t GND PZH PHZ o l t a g e Figure 1. AC Test Circuit (CL includes probe and jig capacitance) D u a l D - T y p e P o s i t i v Waveform for Inverting and Non-Inverting Functions 3-STATE Output Low Enable and e Disable Times for Logic E d g e - T r i g g e r e d F l i p - F l o Propagation Delay. Pulse Width and t Waveforms Setup Time, Hold Time and Recovery Time for Logic p rec w i t h 5 V T o l e r a n t 3-STATE Output High Enable and I t and t n rise fall Disable Times for Logic p u t s V CC Symbol 3.3V ± 0.3V 2.7V 2.5V ± 0.2V Vmi 1.5V 1.5V VCC / 2 Vmo 1.5V 1.5V VCC / 2 V V + 0.3V V + 0.3V V + 0.15V x OL OL OL V V – 0.3V V – 0.3V V – 0.15V y OH OH OH Figure 2. Waveforms (Input Characteristics; f = 1MHz, t = t = 3ns) r f ©1995 Fairchild Semiconductor Corporation www.fairchildsemi.com 74LCX74 Rev. 1.7.1 6

7 4 Schematic Diagram (Generic for LCX Family) LC X 7 4 — L o w V o l t a g e D u a l D - T y p e P o s i t i v e E d g e - T r i g g e r e d F l i p - F l o p w i t h 5 V T o l e r a n t I n p u t s ©1995 Fairchild Semiconductor Corporation www.fairchildsemi.com 74LCX74 Rev. 1.7.1 7

7 4 Tape and Reel Specification L C X Tape Format for DQFN 7 4 Package Designator Tape Section Number of Cavities Cavity Status Cover Tape Status — BQX Leader (Start End) 125 (Typ.) Empty Sealed L o Carrier 3000 Filled Sealed w Trailer (Hub End) 75 (Typ.) Empty Sealed V o l t Tape Dimensions inches (millimeters) a g e D u a l D - T y p e P o s i t i v e E d g e - T r i g g e r e d F l i p - F l o p w i t h 5 V Reel Dimensions inches (millimeters) T o l e r a n t I n p u t s Tape Size A B C D N W1 W2 12mm 13.0 (330.0) 0.059 (1.50) 0.512 (13.00) 0.795 (20.20) 2.165 (55.00) 0.488 (12.4) 0.724 (18.4) ©1995 Fairchild Semiconductor Corporation www.fairchildsemi.com 74LCX74 Rev. 1.7.1 8

0.65 (cid:24)(cid:17)(cid:19)(cid:19)(cid:147)(cid:19)(cid:17)(cid:20)(cid:19) A 0.43TYP 14 8 B 6.4 (cid:23)(cid:17)(cid:23)(cid:19)(cid:147)(cid:19)(cid:17)(cid:20)(cid:19) 6.10 3.2 1.65 1 7 0.2 C B A PIN1IDENT TOPVIEW ALLLEADTIPS 0.45 RECOMMENDEDLANDPATTERN 1.2MAX SEEDETAILA +0.15 0.90 -0.10 0.20 (cid:19)(cid:17)(cid:20)(cid:19)(cid:147)(cid:19)(cid:17)(cid:19)(cid:24) 0.09 ALLLEADTIPS 0.30 0.19 C 0.1 C 0.65 0.13 A B C (cid:20)(cid:21)(cid:17)(cid:19)(cid:19)(cid:131)(cid:3)(cid:55)(cid:50)(cid:51)(cid:3)(cid:9)(cid:3)(cid:37)(cid:50)(cid:55)(cid:55)(cid:50)(cid:48) FRONTVIEW 0.09MIN NOTES: GAGEPLANE A.CONFORMSTOJEDECREGISTRATIONMO-153, VARIATIONAB,REFNOTE6 B.DIMENSIONSAREINMILLIMETERS. 0.25 0.09MIN C.DIMENSIONSAREEXCLUSIVEOFBURRS, (cid:19)(cid:131)(cid:16)(cid:3)(cid:27)(cid:131) (cid:19)(cid:17)(cid:25)(cid:147)(cid:19)(cid:17)(cid:20) MOLDFLASH,ANDTIEBAREXTRUSIONS SEATINGPLANE 1.00 D.DIMENSIONINGANDTOLERANCESPERANSI DETAILA Y14.5M,2009. E.LANDPATTERNSTANDARD:SOP65P640X110-14M. F.DRAWINGFILENAME:MKT-MTC14rev7.

8.75 A 8.50 7.62 14 0.65 8 14 8 B 4.00 6.00 5.60 3.80 1.70 1 7 PIN #1 1.27 0.51 1 7 IDENT. 1.27 0.35 (0.33) 0.25 M C B A LAND PATTERN RECOMMENDATION TOP VIEW 1.75 MAX A C 0.25 0.19 1.50 0.10 C 0.25 1.25 0.10 SIDE VIEW FRONT VIEW NOTES: A. CONFORMS TO JEDEC MS-012, VARIATION AB, ISSUE C B. ALL DIMENSIONS ARE IN MILLIMETERS 0.50 0.25 x 45 C. DIMENSIONS DO NOT INCLUDE MOLD FLASH OR BURRS R0.10 GAGE D. LAND PATTERN STANDARD: PLANE SOIC127P600X145-14M R0.10 E. CONFORMS TO ASME Y14.5M, 2009 0.36 D. DRAWING FILENAME: MKT-M14Arev14 8° 0° 0.90 0.50 SEATING PLANE (1.04) DETAIL A SCALE 16 : 1

4.00MAX 2.20MAX B 3.00 1.40MAX 0.05 C A 2X 1.00 MAX 1.70 2.50 0.50TYP MAX 3.50 MAX (0.90) 0.05 C PIN1QUADRANT TOPVIEW 2X 0.50TYP 0.24TYP (cid:19)(cid:17)(cid:27)(cid:19)(cid:147)(cid:19)(cid:17)(cid:19)(cid:24) 0.10 C RECOMMENDEDLANDPATTERN (cid:19)(cid:17)(cid:21)(cid:19)(cid:147)(cid:19)(cid:17)(cid:19)(cid:24) 0.08 C (cid:19)(cid:17)(cid:19)(cid:21)(cid:24)(cid:147)(cid:19)(cid:17)(cid:19)(cid:21)(cid:24) SIDEVIEW C SEATING PLANE (cid:22)(cid:17)(cid:19)(cid:19)(cid:147)(cid:19)(cid:17)(cid:19)(cid:24) (cid:20)(cid:17)(cid:25)(cid:24)(cid:147)(cid:19)(cid:17)(cid:19)(cid:24) (cid:19)(cid:17)(cid:22)(cid:26)(cid:19)(cid:147)(cid:19)(cid:17)(cid:19)(cid:24) (14X) A.CONFORMSTOJEDECREGISTRATION PIN1IDENT MO-241,VARIATIONAA B.DIMENSIONSAREINMILLIMETERS. C.DIMENSIONSANDTOLERANCESPER ASMEY14.5M,2009. 0.50 (cid:20)(cid:17)(cid:20)(cid:24)(cid:147)(cid:19)(cid:17)(cid:19)(cid:24) D.LANDPATTERNRECOMMENDATIONIS (cid:21)(cid:17)(cid:24)(cid:19)(cid:147)(cid:19)(cid:17)(cid:19)(cid:24) EXISTINGINDUSTRYLANDPATTERN. E.DRAWINGFILENAME:MKT-MLP14Arev2. 0.50 (cid:19)(cid:17)(cid:21)(cid:24)(cid:147)(cid:19)(cid:17)(cid:19)(cid:24) (14X) 2.00 0.10 C A B 0.05 C BOTTOMVIEW

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Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: O N Semiconductor: 74LCX74MTC 74LCX74MTCX 74LCX74MX 74LCX74SJ 74LCX74M 74LCX74BQX