7 4 L C February 2008 X 5 7 4 — 74LCX574 L o Low Voltage Octal D-Type Flip-Flop w V o with 5V Tolerant Inputs and Outputs l t a g e Features General Description O c ■ 5V tolerant inputs and outputs The LCX574 is a high-speed, low power octal flip-flop t a ■ 2.3V–3.6V VCC specifications provided with a buffered common Clock (CP) and a buffered l D ■ 7.5ns t max. (V = 3.3V), 10µA I max. common Output Enable (OE). The information presented - PD CC CC T to the D inputs is stored in the flip-flops on the LOW-to- ■ Power down high impedance inputs and outputs y HIGH Clock (CP) transition. p ■ Supports live insertion/withdrawal(1) e ■ ±24mA output drive (VCC = 3.0V) Texhcee pLtC foXr5 t7h4e pisin ofuutnsc.tionally identical to the LCX374 Fli ■ Implements patented noise/EMI reduction circuitry p - The LCX574 is designed for low voltage applications F ■ Latch-up performance exceeds JEDEC 78 conditions l with capability of interfacing to a 5V signal environment. o ■ ESD performance p The LCX574 is fabricated with an advanced CMOS – Human body model > 2000V technology to achieve high speed operation while main- w i – Machine model > 200V taining CMOS low power dissipation. th Note: 5 V 1. To ensure the high impedance state during power up T or down, OE should be tied to V through a pull-up o CC l resistor: the minimum value of the resistor is e r determined by the current-sourcing capability of the a n driver. t I n p u Ordering Information ts a Order Package n d Number Number Package Description O u 74LCX574WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide t p 74LCX574SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide u t 74LCX574BQX(2) MLP20B 20-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC s MO-241, 2.5 x 4.5mm 74LCX574MSA MSA20 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide 74LCX574MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Note: 2. DQFN package available in Tape and Reel only. Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number. All packages are lead free per JEDEC: J-STD-020B standard. ©2006 Fairchild Semiconductor Corporation www.fairchildsemi.com 74LCX574 Rev. 1.6.0

7 4 Connection Diagrams Logic Symbol L C X Pin Assignments for 5 SOIC, SOP, SSOP, TSSOP 7 D0D1D2D3D4D5D6D7 4 CP — OE 1 20 VCC OE L DD10 23 1198 OO10 O0O1O2O3O4O5O6O7 ow D2 4 17 O2 V D3 5 16 O3 ol D4 6 15 O4 Truth Table ta D5 7 14 O5 ge D6 8 13 O6 Inputs Internal Outputs O D7 9 12 O7 OE CP D Q O Function c GND 10 11 CP n ta H H L NC Z Hold l D H H H NC Z Hold - Pad Assignments for DQFN T y H L H Z Load OE VCC pe H H L Z Load 1 20 F D0 2 19 O0 L L H L Data Available lip D1 3 18 O1 L H L H Data Available -F l L H L NC NC No Change in Data o D2 4 17 O2 p D3 5 16 O3 L H H NC NC No Change in Data w D4 6 15 O4 HL == LHOIGWH V Vooltlataggee L Leevveell ith 5 D5 7 14 O5 X = Immaterial V D6 8 13 O6 Z = High Impedance To = LOW-to-HIGH Transition l e D7 9 12 O7 NC = No Change r a n 10 11 GND CP Functional Description t I n The LCX574 consists of eight edge-triggered flip-flops p (Top View) u with individual D-type inputs and 3-STATE true outputs. t s Pin Descriptions The buffered clock and buffered Output Enable are com- a mon to all flip-flops. The eight flip-flops will store the n d Pin Names Description state of their individual D inputs that meet the setup and O hold time requirements on the LOW-to-HIGH Clock (CP) D –D Data Inputs u 0 7 transition. With the Output Enable (OE) LOW, the con- t p CP Clock Pulse Input tents of the eight flip-flops are available at the outputs. u OE 3-STATE Output Enable Input When OE is HIGH, the outputs go to the high impedance ts state. Operation of the OE input does not affect the load- O –O 3-STATE Outputs 0 7 ing of the flip-flops. Logic Diagram D0 D1 D2 D3 D4 D5 D6 D7 CP C D C D C D C D C D C D C D C D Q Q Q Q Q Q Q Q OE O0 O1 O2 O3 O4 O5 O6 O7 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. ©2006 Fairchild Semiconductor Corporation www.fairchildsemi.com 74LCX574 Rev. 1.6.0 2

7 4 Absolute Maximum Ratings L C Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be X 5 operable above the recommended operating conditions and stressing the parts to these levels is not recommended. 7 In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. 4 The absolute maximum ratings are stress ratings only. — L Symbol Parameter Conditions Value Units o w VCC Supply Voltage –0.5 to +7.0 V V V DC Input Voltage –0.5 to +7.0 V o I l t a V DC Output Voltage Output in 3-STATE –0.5 to +7.0 V O g Output in HIGH or LOW State(3) –0.5 to VCC + 0.5 e O I DC Input Diode Current V < GND –50 mA c IK I t IOK DC Output Diode Current VO < GND –50 mA al D VO > VCC +50 - T I DC Output Source/Sink Current ±50 mA y O p I DC Supply Current per Supply Pin ±100 mA e CC F I DC Ground Current per Ground Pin ±100 mA l GND ip TSTG Storage Temperature –65 to +150 °C -F l o p Recommended Operating Conditions(4) w i t The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended h operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not 5 V recommend exceeding them or designing to absolute maximum ratings. T o Symbol Parameter Conditions Min. Max. Units le r V Supply Voltage Operating 2.0 3.6 V a CC n Data Retention 1.5 3.6 t I n V Input Voltage 0 5.5 V p I u V Output Voltage HIGH or LOW State 0 V V t O CC s 3-STATE 0 5.5 a n I /I Output Current V = 3.0V–3.6V ±24 mA d OH OL CC O VCC = 2.7V–3.0V ±12 u t V = 2.3V–2.7V ±8 p CC u TA Free-Air Operating Temperature –40 85 °C ts ∆t/∆V Input Edge Rate V = 0.8V–2.0V, V = 3.0V 0 10 ns/V IN CC Notes: 3. I Absolute Maximum Rating must be observed. O 4. Unused inputs must be held HIGH or LOW. They may not float. ©2006 Fairchild Semiconductor Corporation www.fairchildsemi.com 74LCX574 Rev. 1.6.0 3

7 4 DC Electrical Characteristics L C X TA = –40°C to +85°C 5 7 Symbol Parameter V (V) Conditions Min. Max. Units 4 CC — V HIGH Level Input Voltage 2.3–2.7 1.7 V IH L 2.7–3.6 2.0 o w VIL LOW Level Input Voltage 2.3–2.7 0.7 V V o 2.7–3.6 0.8 l t VOH HIGH Level Output Voltage 2.3–3.6 IOH = –100µA VCC – 0.2 V ag e 2.3 IOH = –8mA 1.8 O 2.7 I = –12mA 2.2 c OH t a 3.0 IOH = –18mA 2.4 l D IOH = –24mA 2.2 -T V LOW Level Output Voltage 2.3–3.6 I = 100µA 0.2 V y OL OL p 2.3 I = 8mA 0.6 e OL F 2.7 IOL = 12mA 0.4 lip 3.0 IOL = 16mA 0.4 -F l I = 24mA 0.55 o OL p I Input Leakage Current 2.3–3.6 0 ≤ V ≤ 5.5V ±5.0 µA w I I i IOZ 3-STATE Output Leakage 2.3–3.6 0 ≤ VO ≤ 5.5V, ±5.0 µA th VI = VIH or VIL 5 V IOFF Power-Off Leakage Current 0 VI or VO = 5.5V 10 µA T o ICC Quiescent Supply Current 2.3–3.6 VI = VCC or GND 10 µA le 2.3–3.6 3.6V ≤ VI, VO ≤ 5.5V(5) ±10 ra n ∆ICC Increase in ICC per Input 2.3–3.6 VIH = VCC –0.6V 500 µA t I n p u t AC Electrical Characteristics s a TA = –40°C to +85°C, RL = 500Ω nd V = 3.3V ± 0.3V, V = 2.7V, V = 2.5 ± 0.2V, O CC CC CC u CL = 50pF CL = 50pF CL = 30pF tp Symbol Parameter Min. Max. Min. Max. Min. Max. Units u t s f Maximum Clock Frequency 150 MHz MAX t , t Propagation Delay, 1.5 8.5 1.5 9.5 1.5 10.5 ns PHL PLH CP to O n t , t Output Enable Time 1.5 8.5 1.5 9.5 1.5 10.5 ns PZL PZH t , t Output Disable Time 1.5 6.5 1.5 7.0 1.5 7.8 ns PLZ PHZ t Setup Time 2.5 2.5 4.0 ns S t Hold Time 1.5 1.5 2.0 ns H t Pulse Width 3.3 3.3 4.0 ns W t , t Output to Output Skew(6) 1.0 ns OSHL OSLH Notes: 5. Outputs disabled or 3-STATE only. 6. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t ) or LOW-to-HIGH (t ). OSHL OSLH ©2006 Fairchild Semiconductor Corporation www.fairchildsemi.com 74LCX574 Rev. 1.6.0 4

7 4 Dynamic Switching Characteristics L C X TA = 25°C 5 7 Symbol Parameter V (V) Conditions Typical Units 4 CC — V Quiet Output Dynamic Peak V 3.3 C = 50pF, V = 3.3V, V = 0V 0.8 V OLP OL L IH IL L 2.5 C = 30pF, V = 2.5V, V = 0V 0.6 o L IH IL w VOLV Quiet Output Dynamic Valley VOL 3.3 CL = 50pF, VIH = 3.3V, VIL = 0V –0.8 V V 2.5 C = 30pF, V = 2.5V, V = 0V –0.6 o L IH IL l t a g e Capacitance O c t Symbol Parameter Conditions Typical Units a l C Input Capacitance V = Open, V = 0V or V 7 pF D IN CC I CC - T C Output Capacitance V = 3.3V, V = 0V or V 8 pF y OUT CC I CC p C Power Dissipation Capacitance V = 3.3V, V = 0V or V , f = 10MHz 25 pF e PD CC I CC F l i p - F l o p w i t h 5 V T o l e r a n t I n p u t s a n d O u t p u t s ©2006 Fairchild Semiconductor Corporation www.fairchildsemi.com 74LCX574 Rev. 1.6.0 5

7 4 AC Loading and Waveforms (Generic for LCX Family) LC X 5 VCC 7 500Ω OPEN tPLH, tPHL 4 TEST DUT GND tPZH, tPHZ — SIGNAL VI tPZL, tPLZ L CL 500Ω o w V o l Figure 1. AC Test Circuit (C includes probe and jig capacitance) t L a g Test Switch e O t , t Open c PLH PHL t tPZL, tPLZ 6V at VCC = 3.3 ± 0.3V al V x 2 at V = 2.5 ± 0.2V D CC CC - T tPZH, tPHZ GND y p e DATINA Vmi VGCNCD COONUTTRPOUTL Vmi VGCNCD Flip tpxx tpxx tPZH tPHZ - F DOAUTAT Vmo DOAUTAT Vmo VVOYH lo p w Waveform for Inverting and 3-STATE Output High Enable and i t Non-Inverting Functions Disable Times for Logic h 5 V COCNLTORCOINKL tW treVcmiVmi VGCNCD CONINTDRPAOUTITLNA tS VtHmi Vmi VGVGCCNNCCDD Tolerant tPHL tPLH MR tS trec In OR Vmi p OUTPUT Vmo Vmo CLEAR u t s Propagation Delay, Pulse Width and Setup Time, Hold Time and a n t Waveforms Recovery Time for Logic d rec O COONUTTRPOUTL Vmi VGCNCD tr tf utp u tPZL tPLZ ANY 90% 90% VOH ts DOAUTAT Vmo VX OUTPUT 10% 10% VOL VOL 3-STATE Output Low Enable and t and t rise fall Disable Times for Logic Figure 2. Waveforms (Input Characteristics; f =1MHz, t = t = 3ns) r f V CC Symbol 3.3V ± 0.3V 2.7V 2.5V ± 0.2V V 1.5V 1.5V V / 2 mi CC V 1.5V 1.5V V / 2 mo CC V V + 0.3V V + 0.3V V + 0.15V x OL OL OL V V – 0.3V V – 0.3V V – 0.15V y OH OH OH ©2006 Fairchild Semiconductor Corporation www.fairchildsemi.com 74LCX574 Rev. 1.6.0 6

7 4 Schematic Diagram (Generic for LCX Family) LC X 5 Input Stage 7 4 — L o w P2 V o P1 l t VCC ag e O Data c t a ESD P5 X1 l D D2 N+/P– VDD -T N1 N2 y p e F GTO™ Output l i Input Stage p - F P4 D6 l N+/P– o p w i t h 5 P3 V T N5 o l e r a Enable n N4 t ESD I n D4 N+/P– p u N3 t s a n d O u t p u t s ©2006 Fairchild Semiconductor Corporation www.fairchildsemi.com 74LCX574 Rev. 1.6.0 7

7 4 Tape and Reel Specification L C X Tape Format for DQFN 5 7 Package Tape Number Cavity Cover Tape 4 — Designator Section Cavities Status Status L BQX Leader (Start End) 125 (typ) Empty Sealed o w Carrier 3000 Filled Sealed V Trailer (Hub End) 75 (typ) Empty Sealed o l t a Tape Dimensions inches (millimeters) g e O c t a l D - T y p e F l i p - F l o p w i t h 5 V T o l e r a n t I n p u t s a n d O u t Reel Dimensions inches (millimeters) p u t s Tape Size A B C D N W1 W2 12mm 13.0 (330.0) 0.059 (1.50) 0.512 (13.00) 0.795 (20.20) 2.165 (55.00) 0.488 (12.4) 0.724 (18.4) ©2006 Fairchild Semiconductor Corporation www.fairchildsemi.com 74LCX574 Rev. 1.6.0 8

7 4 Physical Dimensions L C X 5 13.00 7 12.60 4 A — 11.43 L 20 11 o B w V o l t a 9.50 g e 10.65 7.60 10.00 7.40 O c t 2.25 a l D - T y p PINONE 1 0.51 1.27 10 1.27 0.65 e 0.35 F INDICATOR l 0.25 M C B A ip - LANDPATTERNRECOMMENDATION F l o p 2.65MAX SEEDETAILA w i t h 0.33 5 C 0.20 V T 0.30 0.10 C o 0.75 0.10 SEATINGPLANE le 0.25X45° r NOTES:UNLESSOTHERWISESPECIFIED a n t (R0.10) A) THISPACKAGECONFORMSTOJEDEC In (R0.10) GAGEPLANE MS-013,VARIATIONAC,ISSUEE p u B) ALLDIMENSIONSAREINMILLIMETERS. t 8° 0.25 s 0° C) DIMENSIONSDONOTINCLUDEMOLD a FLASHORBURRS. n 1.27 D) CONFORMSTOASMEY14.5M-1994 d 0.40 SEATINGPLANE E) LANDPATTERNSTANDARD:SOIC127P1030X265-20L O u (1.40) DETAILA F) DRAWINGFILENAME:MKT-M20BREV3 tp SCALE:2:1 u t s Figure 3. 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ ©2006 Fairchild Semiconductor Corporation www.fairchildsemi.com 74LCX574 Rev. 1.6.0 9

7 4 Physical Dimensions (Continued) LC X 5 7 4 — L o w V o l t a g e O c t a l D - T y p e F l i p - F l o p w i t h 5 V T o l e r a n t I n p u t s a n d O u t p u t s Figure 4. 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ ©2006 Fairchild Semiconductor Corporation www.fairchildsemi.com 74LCX574 Rev. 1.6.0 10

7 4 Physical Dimensions (Continued) LC X 5 7 4 — L o w V o l t a g e O c t a l D - T y p e F l i p - F l o p w i t h 5 V T o l e r a n t I n p u t s a n d O u t p u t s Figure 5. 20-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC MO-241, 2.5 x 4.5mm Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ ©2006 Fairchild Semiconductor Corporation www.fairchildsemi.com 74LCX574 Rev. 1.6.0 11

7 4 Physical Dimensions (Continued) LC X 5 7 4 — L o w V o l t a g e O c t a l D - T y p e F l i p - F l o p w i t h 5 V T o l e r a n t I n p u t s a n d O u t p u t s Figure 6. 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ ©2006 Fairchild Semiconductor Corporation www.fairchildsemi.com 74LCX574 Rev. 1.6.0 12

7 4 Physical Dimensions (Continued) LC X 5 7 4 — L o w V o l t a g e O c t a l D - T y p e F l i p - F l o p w i t h 5 V T o l e r a n t I n p u t s a n d O u t p u t s Figure 7. 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ ©2006 Fairchild Semiconductor Corporation www.fairchildsemi.com 74LCX574 Rev. 1.6.0 13

7 4 L C X 5 7 4 — TRADEMARKS L Thefollowingincludesregisteredandunregisteredtrademarksandservicemarks,ownedbyFairchildSemiconductorand/oritsglobal o subsidiaries,andisnotintendedtobeanexhaustivelistofallsuchtrademarks. w ACEx® FPS™ PDP-SPM™ SupreMOS™ V BuilditNow™ FRFET® Power220® SyncFET™ ol CorePLUS™ GlobalPowerResourceSM POWEREDGE® ® ta CROSSVOLT™ GreenFPS™ Power-SPM™ ThePowerFranchise® g CTL™ GreenFPS™e-Series™ PowerTrench® e O CurrentTransferLogic™ GTO™ ProgrammableActiveDroop™ EcoSPARK® i-Lo™ QFET® TinyBoost™ ct EZSWITCH™* IntelliMAX™ QS™ TinyBuck™ al ™ ISOPLANAR™ QTOptoelectronics™ TinyLogic® D ® MegaBuck™ QuietSeries™ TINYOPTO™ -T MICROCOUPLER™ RapidConfigure™ TinyPower™ y FFaaiirrcchhiilldd®Semiconductor® MMiiccrrooPFEakT™™ SSMPMAR®TSTART™ TTiinnyyWPWireM™™ pe F FACTQuietSeries™ MillerDrive™ STEALTH™ µSerDes™ l FACT® Motion-SPM™ SuperFET™ UHC® ip FAST® OPTOLOGIC® SuperSOT™-3 UltraFRFET™ -F FastvCore™ OPTOPLANAR® SuperSOT™-6 UniFET™ lo FlashWriter®* ® SuperSOT™-8 VCX™ p w *EZSWITCH™andFlashWriter®aretrademarksofSystemGeneralCorporation,usedunderlicensebyFairchildSemiconductor. i t h 5 DISCLAIMER V FAIRCHILDSEMICONDUCTORRESERVESTHERIGHTTOMAKECHANGESWITHOUTFURTHERNOTICETOANYPRODUCTS T HEREINTOIMPROVERELIABILITY,FUNCTION,ORDESIGN.FAIRCHILDDOESNOTASSUMEANYLIABILITYARISINGOUTOFTHE o l APPLICATIONORUSEOFANYPRODUCTORCIRCUITDESCRIBEDHEREIN;NEITHERDOESITCONVEYANYLICENSEUNDERITS e r PATENTRIGHTS,NORTHERIGHTSOFOTHERS.THESESPECIFICATIONSDONOTEXPANDTHETERMSOFFAIRCHILD’S a WORLDWIDETERMSANDCONDITIONS,SPECIFICALLYTHEWARRANTYTHEREIN,WHICHCOVERSTHESEPRODUCTS. n t I n LIFESUPPORTPOLICY p u FAIRCHILD’SPRODUCTSARENOTAUTHORIZEDFORUSEASCRITICALCOMPONENTSINLIFESUPPORTDEVICESOR t s SYSTEMSWITHOUTTHEEXPRESSWRITTENAPPROVALOFFAIRCHILDSEMICONDUCTORCORPORATION. a Asusedherein: n d 1. Life support devices or systems are devices or systems 2. A critical component in any component of a life support, O which, (a) are intended for surgical implant intothebodyor device, or system whose failure to perform can be u (b) support or sustain life, and (c) whose failure to perform reasonablyexpectedtocausethefailureofthelifesupport t when properly used in accordance with instructions for use deviceorsystem,ortoaffectitssafetyoreffectiveness. p provided in the labeling, can be reasonably expected to u t resultinasignificantinjuryoftheuser. s PRODUCTSTATUSDEFINITIONS DefinitionofTerms DatasheetIdentification ProductStatus Definition Thisdatasheetcontainsthedesignspecificationsforproduct AdvanceInformation FormativeorInDesign development.Specificationsmaychangeinanymannerwithoutnotice. Thisdatasheetcontainspreliminarydata;supplementarydatawillbe Preliminary First Production publishedatalaterdate.FairchildSemiconductorreservestherightto makechangesatanytimewithoutnoticetoimprovedesign. Thisdatasheetcontainsfinalspecifications.FairchildSemiconductor NoIdentificationNeeded FullProduction reservestherighttomakechangesatanytimewithoutnoticetoimprove thedesign. Thisdatasheetcontainsspecificationsonaproductthathasbeen Obsolete NotInProduction discontinuedbyFairchildSemiconductor.Thedatasheetisprintedfor referenceinformationonly. Rev.I33 ©2006 Fairchild Semiconductor Corporation www.fairchildsemi.com 74LCX574 Rev. 1.6.0 14