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7 4 L C X December 2013 5 4 1 — 74LCX541 L o Low Voltage Octal Buffer/Line Driver w V o with 5V Tolerant Inputs and Outputs l t a g e Features General Description O c ■ 5V tolerant input and outputs The LCX541 is an octal buffer/line driver designed to be t a ■ 2.3V–3.6V VCC specifications provided employed as memory and address drivers, clock drivers l B ■ 6.5ns t max (V = 3.3V), 10µA I max and bus oriented transmitter/receivers. The LCX541 is a u PD CC CC non inverting option of the LCX540. f ■ Power-down high impedance inputs and outputs fe ■ Supports live insertion/withdrawal(1) This device is similar in function to the LCX244 while r/ L providing flow-through architecture (inputs on opposite ■■ ±Im2p4l emmAe onutstp purto dprriiveeta (rVy CnCo i=s e3/. 0EVM)I reduction circuitry sdiedvei cfero ems poeuctipaulltys )u. sTehfuisl paisn oaunt oaurrtapnugt epmoret nfto rm makicerso pthrois- ine D ■ Latch-up performance exceeds JEDEC 78 conditions cessors, allowing ease of layout and greater PC board r i ■ ESD performance density. v e – Human body model > 2000V The LCX541 is designed for low voltage applications r w – Machine model > 200V with capability of interfacing to a 5V signal environment. i t h ■ Leadless DQFN package The LCX541 is fabricated with an advanced CMOS 5 technology to achieve high speed operation while V Note: maintaining CMOS low power dissipation. T o 1. To ensure the high impedance state during power up l e or down, OE should be tied to V through a pull-up r CC a resistor: the minimum value of the resistor is n t determined by the current-sourcing capability of the I n driver. p u t s a Ordering Information n d O Package u Order Number Number Package Description t p u 74LCX541WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide t s 74LCX541SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74LCX541BQX(2) MLP20B 20-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC MO-241, 2.5 x 4.5mm 74LCX541MSA MSA20 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide 74LCX541MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Note: 2. DQFN package available in Tape and Reel only. Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number. All packages are lead free per JEDEC: J-STD-020B standard. ©2006 Fairchild Semiconductor Corporation www.fairchildsemi.com 74LCX541 Rev. 1.6.1

7 4 Connection Diagrams Logic Symbol L C X Pin Assignments for IEEE/IEC 5 SOIC, SOP, SSOP, TSSOP 4 & 1 OE1 EN — OE1 12 2109 VCC OE2 L I0 OE2 o GNDIIIIIII1234567 134567890 1111111187654321 OOOOOOOO01234567 IIIIIIII01234567 OOOOOOOO01234567 w Voltage Octal B u f f e Truth Table Pad Assignment for DQFN r / L OE1 VCC Inputs Outputs in 1 20 e OE OE I O 1 2 n D I0 2 19 OE2 r L L H H i I1 3 18 O0 ve H X X Z r I2 4 17 O1 w X H X Z i I3 5 16 O2 th L L L L I4 6 15 O3 H = HIGH Voltage Level 5V I5 7 14 O4 T L = LOW Voltage Level o I6 8 13 O5 X = Immaterial ler I7 9 12 O6 Z = High Impedance an t 10 11 I n GND O7 p u (Top View) (Bottom View) ts a n d Pin Descriptions O u Pin Names Description tp u OE , OE 3-STATE Output Enable Inputs t 1 2 s I –I Inputs 0 7 O –O Outputs 0 7 DAP No Connect Note: DAP (Die Attach Pad) ©2006 Fairchild Semiconductor Corporation www.fairchildsemi.com 74LCX541 Rev. 1.6.1 2

7 4 Absolute Maximum Ratings L C Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be X 5 operable above the recommended operating conditions and stressing the parts to these levels is not recommended. 4 In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. 1 The absolute maximum ratings are stress ratings only. — L Symbol Parameter Conditions Value Units o w VCC Supply Voltage –0.5 to +7.0 V V V DC Input Voltage –0.5 to +7.0 V o I l t a V DC Output Voltage Output in 3-STATE –0.5 to +7.0 V O g Output in HIGH or LOW State(3) –0.5 to VCC + 0.5 e O I DC Input Diode Current V < GND –50 mA c IK I t IOK DC Output Diode Current VO < GND –50 mA al B VO > VCC +50 u f I DC Output Source/Sink Current ±50 mA f O e r ICC DC Supply Current per Supply Pin ±100 mA /L i I DC Ground Current per Ground Pin ±100 mA n GND e TSTG Storage Temperature –65 to +150 °C D r i v e Recommended Operating Conditions(4) r w The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended it h operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not 5 recommend exceeding them or designing to absolute maximum ratings. V T Symbol Parameter Conditions Min. Max. Units o l e VCC Supply Voltage Operating 2.0 3.6 V ra Data Retention 1.5 3.6 n t I V Input Voltage 0 5.5 V n I p V Output Voltage HIGH or LOW State 0 V V u O CC t s 3-STATE 0 5.5 a I /I Output Current V = 3.0V–3.6V ±24 mA n OH OL CC d VCC = 2.7V–3.0V ±12 O u VCC = 2.3V–2.7V ±8 tp T Free-Air Operating Temperature –40 85 °C u A t s ∆t/∆V Input Edge Rate V = 0.8V–2.0V, V = 3.0V 0 10 ns/V IN CC Notes: 3. I Absolute Maximum Rating must be observed. O 4. Unused inputs must be held HIGH or LOW. They may not float. ©2006 Fairchild Semiconductor Corporation www.fairchildsemi.com 74LCX541 Rev. 1.6.1 3

7 4 DC Electrical Characteristics L C X TA = –40°C to +85°C 5 4 Symbol Parameter V (V) Conditions Min. Max. Units 1 CC — V HIGH Level Input Voltage 2.3–2.7 1.7 V IH L 2.7–3.6 2.0 o w VIL LOW Level Input Voltage 2.3–2.7 0.7 V V o 2.7–3.6 0.8 l t VOH HIGH Level Output Voltage 2.3–3.6 IOH = –100µA VCC – 0.2 V ag e 2.3 IOH = –8mA 1.8 O 2.7 I = –12mA 2.2 c OH t a 3.0 IOH = –18mA 2.4 l B IOH = –24mA 2.2 u f VOL LOW Level Output Voltage 2.3–3.6 IOL = 100µA 0.2 V fe r 2.3 IOL = 8mA 0.6 /L i 2.7 I = 12mA 0.4 n OL e 3.0 I = 16mA 0.4 D OL r IOL = 24mA 0.55 iv e I Input Leakage Current 2.3–3.6 0 ≤ V ≤ 5.5V ±5.0 µA r I I w IOFF Power-Off Leakage Current 0 VI or VO = 5.5V 10 µA it h ICC Quiescent Supply Current 2.3–3.6 VI = VCC or GND 10 µA 5 3.6V ≤ V, V ≤ 5.5V(5) ±10 V I O T ∆I Increase in I per Input 2.3–3.6 V = V = 0.6V 500 µA o CC CC IH CC l e r a n t AC Electrical Characteristics I n p T = –40°C to +85°C, R = 500Ω u A L t VCC = 3.3V ± 0.3V, VCC = 2.7V, VCC = 2.5V ± 0.2V, s a C = 50pF C = 50pF C = 30pF n L L L d Symbol Parameter Min. Max. Min. Max. Min. Max. Units O u t , t Propagation Delay 1.5 6.5 1.5 7.5 1.5 7.8 ns PHL PLH t p t , t Output Enable Time 1.5 8.5 1.5 9.5 1.5 10.5 ns u PZL PZH t s t , t Output Disable Time 1.5 7.5 1.5 8.5 1.5 9.0 ns PLZ PHZ t , t Output to Output Skew(6) 1.0 ns OSHL OSLH Notes 5. Outputs disabled or 3-STATE only. 6. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t ) or LOW-to-HIGH (t ). OSHL OSLH ©2006 Fairchild Semiconductor Corporation www.fairchildsemi.com 74LCX541 Rev. 1.6.1 4

7 4 Dynamic Switching Characteristics L C X TA = 25°C 5 4 Symbol Parameter V (V) Conditions Typical Units 1 CC — V Quiet Output Dynamic Peak V 3.3 C = 50 pF, V = 3.3V, V = 0V 0.8 V OLP OL L IH IL L 2.5 C = 30 pF, V = 2.5V, V = 0V 0.6 o L IH IL w VOLV Quiet Output Dynamic Valley VOL 3.3 CL = 50 pF, VIH = 3.3V, VIL = 0V –0.8 V V 2.5 C = 30 pF, V = 2.5V, V = 0V –0.6 o L IH IL l t a g e Capacitance O c t Symbol Parameter Conditions Typical Units a l C Input Capacitance V = Open, V = 0V or V 7 pF B IN CC I CC u COUT Output Capacitance VCC = 3.3V, VI = 0V or VCC 8 pF ffe CPD Power Dissipation Capacitance VCC = 3.3V, VI = 0V or VCC, f = 10 MHz 25 pF r/L i n e D r i v e r w i t h 5 V T o l e r a n t I n p u t s a n d O u t p u t s ©2006 Fairchild Semiconductor Corporation www.fairchildsemi.com 74LCX541 Rev. 1.6.1 5

7 4 AC Loading and Waveforms (Generic for LCX Family) LC X 5 VCC 4 500Ω OPEN tPLH, tPHI 1 TEST DUT GND tPZH, tPHZ — SIGNAL VI tPZL, tPLZ L CL 500Ω o w V o l Figure 1. AC Test Circuit (C includes probe and jig capacitance) t L a g e Test Switch O tPLH, tPHL Open c t t , t 6V at V = 3.3 ± 0.3V a PZL PLZ CC l VCC x 2 at VCC = 2.5 ± 0.2V B u t , t GND PZH PHZ f f e r / DATINA Vmi VGCNCD COONUTTRPOUTL Vmi VGCNCD Lin tpxx tpxx tPZL tPLZ e D DOAUTAT Vmo DOAUTAT Vmo VX ri VOL v e Waveform for Inverting and 3-STATE Output High Enable and r w Non-Inverting Functions Disable Times for Logic i t h tW DATA VCC 5 COCNLTORCOINKL treVcmiVmi VGCNCD CONINTRPOUITLN tS VtHmi Vmi GVGCNNCDD V Tolera tPHL tPLH MR tS trec nt OUTPUT Vmo Vmo CLEOARR Vmi In p u Propagation Delay, Pulse Width and Setup Time, Hold Time and ts t Waveforms Recovery Time for Logic a rec n d tr tf O COONUTTRPOUTL tPZH tPHZ Vmi VGCNCD ANY 90% 90% VOH utpu DOAUTAT Vmo VVOYH OUTPUT 10% 10% VOL ts t and t 3-STATE Output Low Enable and rise fall Disable Times for Logic Figure 2. Waveforms (Input Characteristics; f = 1MHz, t = t = 3ns) r f V CC Symbol 3.3V ± 0.3V 2.7V 2.5V ± 0.2V V 1.5V 1.5V V / 2 mi CC V 1.5V 1.5V V / 2 mo CC V V + 0.3V V + 0.3V V + 0.15V x OL OL OL V V – 0.3V V – 0.3V V – 0.15V y OH OH OH ©2006 Fairchild Semiconductor Corporation www.fairchildsemi.com 74LCX541 Rev. 1.6.1 6

7 4 Schematic Diagram (Generic for LCX Family) LC X 5 Input Stage 4 1 — L o w P2 V o l P1 ta VCC g e O c Data ta l ESD B P5 X1 u D2 N+/P– f VDD fe N1 N2 r / L i n GTO™ Output e Input Stage D r i P4 D6 v N+/P– e r w i t h 5 V P3 T o N5 le r a n Enable t N4 I n ESD p u D4 N+/P– t s N3 a n d O u t p u t s ©2006 Fairchild Semiconductor Corporation www.fairchildsemi.com 74LCX541 Rev. 1.6.1 7

7 4 Tape and Reel Specification L C X Tape Format for DQFN 5 4 Package Tape Number Cavity Cover Tape 1 — Designator Section Cavities Status Status L BQX Leader (Start End) 125 (typ) Empty Sealed o w Carrier 3000 Filled Sealed V Trailer (Hub End) 75 (typ) Empty Sealed o l t a Tape Dimensions inches (millimeters) g e O c t a l B u f f e r / L i n e D r i v e r w i t h 5 V T o l e r a n t I n p u t s a n d O u t Reel Dimensions inches (millimeters) p u t s Tape Size A B C D N W1 W2 12mm 13.0 (330.0) 0.059 (1.50) 0.512 (13.00) 0.795 (20.20) 2.165 (55.00) 0.488 (12.4) 0.724 (18.4) ©2006 Fairchild Semiconductor Corporation www.fairchildsemi.com 74LCX541 Rev. 1.6.1 8

7 4 Physical Dimensions L C X 5 13.00 4 12.60 1 A — 11.43 L 20 11 o B w V o l t a 9.50 g e 10.65 7.60 10.00 7.40 O c t 2.25 a l B u f f e 1 10 0.65 r PINONE 0.51 1.27 1.27 /L INDICATOR 0.35 in 0.25 M C B A e LANDPATTERNRECOMMENDATION D r i v 2.65MAX e SEEDETAILA r w i t 0.33 h C 0.20 5 V 0.30 0.10 C T 0.75 0.10 SEATINGPLANE o 0.25X45° le NOTES:UNLESSOTHERWISESPECIFIED r a n (R0.10) A) THISPACKAGECONFORMSTOJEDEC t (R0.10) GAGEPLANE MS-013,VARIATIONAC,ISSUEE In p B) ALLDIMENSIONSAREINMILLIMETERS. u 8° 0.25 t 0° C) DIMENSIONSDONOTINCLUDEMOLD s FLASHORBURRS. a 1.27 D) CONFORMSTOASMEY14.5M-1994 n d 0.40 SEATINGPLANE E) LANDPATTERNSTANDARD:SOIC127P1030X265-20L O (1.40) DETAILA F) DRAWINGFILENAME:MKT-M20BREV3 u SCALE:2:1 tp u t Figure 3. 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide s Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ ©2006 Fairchild Semiconductor Corporation www.fairchildsemi.com 74LCX541 Rev. 1.6.1 9

7 4 Physical Dimensions (Continued) LC X 5 4 1 — L o w V o l t a g e O c t a l B u f f e r / L i n e D r i v e r w i t h 5 V T o l e r a n t I n p u t s a n d O u t p u t s Figure 4. 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ ©2006 Fairchild Semiconductor Corporation www.fairchildsemi.com 74LCX541 Rev. 1.6.1 10

7 4 Physical Dimensions (Continued) LC X 5 4 1 — L o w V o l t a g e O c t a l B u f f e r / L i n e D r i v e r w i t h 5 V T o l e r a n t I n p u t s a n d O u t p u t s Figure 5. 20-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC MO-241, 2.5 x 4.5mm Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ ©2006 Fairchild Semiconductor Corporation www.fairchildsemi.com 74LCX541 Rev. 1.6.1 11

7 4 Physical Dimensions (Continued) LC X 5 4 1 — L o w V o l t a g e O c t a l B u f f e r / L i n e D r i v e r w i t h 5 V T o l e r a n t I n p u t s a n d O u t p u t s Figure 6. 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ ©2006 Fairchild Semiconductor Corporation www.fairchildsemi.com 74LCX541 Rev. 1.6.1 12

7 4 Physical Dimensions (Continued) LC X 5 4 1 — L o w V o l t a g e O c t a l B u f f e r / L i n e D r i v e r w i t h 5 V T o l e r a n t I n p u t s a n d O u t p u t s Figure 7. 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ ©2006 Fairchild Semiconductor Corporation www.fairchildsemi.com 74LCX541 Rev. 1.6.1 13

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