Is Now Part of To learn more about ON Semiconductor, please visit our website at www.onsemi.com Please note: As part of the Fairchild Semiconductor integration, some of the Fairchild orderable part numbers will need to change in order to meet ON Semiconductor’s system requirements. Since the ON Semiconductor product management systems do not have the ability to manage part nomenclature that utilizes an underscore (_), the underscore (_) in the Fairchild part numbers will be changed to a dash (-). This document may contain device numbers with an underscore (_). Please check the ON Semiconductor website to verify the updated device numbers. The most current and up-to-date ordering information can be found at www.onsemi.com. Please email any questions regarding the system integration to Fairchild_questions@onsemi.com. ON Semiconductor and the ON Semiconductor logo are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

7 4 February 1994 L Revised May 2005 C X 1 6 3 74LCX16374 7 4 Low Voltage 16-Bit D-Type Flip-Flop L o w with 5V Tolerant Inputs and Outputs V o l General Description Features ta g The LCX16374 contains sixteen non-inverting D-type (cid:1) 5V tolerant inputs and outputs e felinpt-efldo pasp wpliitcha t3io-SnTs.A TTEh eo udtepvuictse ainsd b iyst ein tceonndterodl lefodr. bAu sb ourffi-- (cid:1) 2.3V–3.6V VCC specifications provided 16 ered clock (CP) and Output Enable (OE) are common to (cid:1) 6.2 ns tPD max (VCC 3.3V), 20 PA ICC max -B each byte and can be shorted together for full 16-bit opera- (cid:1) Power down high impedance inputs and outputs it tion. (cid:1) Supports live insertion/withdrawal (Note 1) D TVhCeC aLpCpXli1c6a3ti7o4n si sw ditehs ciganpeadb ilfiotyr olof win tveorfltaacgineg ( 2to.5 aV 5 oVr s3ig.3nVa)l (cid:1)(cid:1) rU2s4e sm pAr oopurtieptuatr dy rnivoeis (eV/CECM I r3e.d0uVc)tion circuitry -Typ environment. e The LCX16374 is fabricated with an advanced CMOS tech- (cid:1) Latch-up performance exceeds 500 mA F nology to achieve high speed operation while maintaining (cid:1) ESD performance: lip CMOS low power dissipation. Human body model ! 2000V - F Machine model ! 200V lo (cid:1) Also packaged in plastic Fine-Pitch Ball Grid Array p (FBGA) w Nshootuel d1 :b Teo t ieends tuor eV tChCe thhirgohu-gimh pae dpaunll-cuep srteasteis tdour:r inthge p mowineimr uump ovra dluoew onr, OthEe ith resistor is determined by the current-sourcing capability of the driver. 5 V T Ordering Code: o le r Order Number Package Number Package Description a n 74LCX16374G BGA54A 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide t (Note 2)(Note 3) I n 74LCX16374MEA MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide p (Note 3) u t 74LCX16374MTD MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide s (Note 3) a n Note 2: Ordering code “G” indicates Trays. d Note 3: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. O u Logic Symbol t p u t s © 2005 Fairchild Semiconductor Corporation DS012003 www.fairchildsemi.com

4 7 Connection Diagrams Pin Descriptions 3 6 1 X Pin Assignment for SSOP and TSSOP Pin Names Description C L OEn Output Enable Input (Active LOW) 4 7 CPn Clock Pulse Input I0–I15 Inputs O0–O15 Outputs NC No Connect FBGA Pin Assignments 1 2 3 4 5 6 A O0 NC OE1 CP1 NC I0 B O2 O1 NC NC I1 I2 C O4 O3 VCC VCC I3 I4 D O6 O5 GND GND I5 I6 E O8 O7 GND GND I7 I8 F O10 O9 GND GND I9 I10 G O12 O11 VCC VCC I11 I12 H O14 O13 NC NC I13 I14 J O15 NC OE2 CP2 NC I15 Truth Tables Pin Assignment for FBGA Inputs Outputs CP1 OE1 I0–I7 O0–O7 (cid:17) L H H (cid:17) L L L L L X O0 X H X Z Inputs Outputs CP2 OE2 I8–I15 O8–O15 (cid:17) L H H (Top Thru View) (cid:17) L L L L L X O0 X H X Z H HIGH Voltage Level L LOW Voltage Level X Immaterial Z High Impedance O0 Previous O0 before HIGH-to-LOW of CP www.fairchildsemi.com 2

7 Functional Description 4 L The LCX16374 consists of sixteen edge-triggered flip-flops state of their individual D inputs that meet the setup and C X with individual D-type inputs and 3-STATE true outputs. hold time requirements on the LOW-to-HIGH Clock (CPn) 1 The device is byte controlled with each byte functioning transition. With the Output Enable (OEn) LOW, the con- 6 identically, but independent of the other. The control pins tents of the flip-flops are available at the outputs. When 37 can be shorted together to obtain full 16-bit operation. Each OEn is HIGH, the outputs go to the high impedance state. 4 byte has a buffered clock and buffered Output Enable com- mon to all flip-flops within that byte. The description which Operation of the OEn input does not affect the state of the flip-flops. follows applies to each byte. Each flip-flop will store the Logic Diagrams Byte 1 (0:7) Byte 2 (8:15) Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 3 www.fairchildsemi.com

4 7 Absolute Maximum Ratings 3 (Note 4) 6 1 Symbol Parameter Value Conditions Units X C VCC Supply Voltage (cid:16)0.5 to (cid:14)7.0 V 4L VI DC Input Voltage (cid:16)0.5 to (cid:14)7.0 V 7 VO DC Output Voltage (cid:16)0.5 to (cid:14)7.0 3-STATE V (cid:16)0.5 to VCC (cid:14) 0.5 Output in HIGH or LOW State (Note 5) IIK DC Input Diode Current (cid:16)50 VI (cid:31) GND mA IOK DC Output Diode Current (cid:16)50 VO (cid:31) GND mA (cid:14)50 VO ! VCC IO DC Output Source/Sink Current r50 mA ICC DC Supply Current per Supply Pin r100 mA IGND DC Ground Current per Ground Pin r100 mA TSTG Storage Temperature (cid:16)65 to (cid:14)150 qC Note 4: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recom- mended Operating Conditions” table will define the conditions for actual device operation. Note 5: IO Absolute Maximum Rating must be observed. Recommended Operating Conditions (Note 6) Symbol Parameter Min Max Units VCC Supply Voltage Operating 2.0 3.6 V Data Retention 1.5 3.6 VI Input Voltage 0 5.5 V VO Output Voltage HIGH or LOW State 0 VCC V 3-STATE 0 5.5 IOH/IOL Output Current VCC 3.0V (cid:16) 3.6V r24 VCC 2.7V (cid:16) 3.0V r12 mA VCC 2.3V (cid:16) 2.7V r8 TA Free-Air Operating Temperature (cid:16)40 85 qC ’t/’V Input Edge Rate, VIN 0.8V – 2.0V, VCC 3.0V 0 10 ns/V Note 6: Unused inputs must be held HIGH or LOW. They may not float. DC Electrical Characteristics VCC TA (cid:16)40qC to (cid:14)85qC Symbol Parameter Conditions Units (V) Min Max VIH HIGH Level Input Voltage 2.3 (cid:16) 2.7 1.7 V 2.7 (cid:16) 3.6 2.0 VIL LOW Level Input Voltage 2.3 (cid:16) 2.7 0.7 V 2.7 (cid:16) 3.6 0.8 VOH HIGH Level Output Voltage IOH (cid:16)100 PA 2.3 (cid:16) 3.6 VCC (cid:16) 0.2 IOH (cid:16)8 mA 2.3 1.8 IOH (cid:16)12 mA 2.7 2.2 V IOH (cid:16)18 mA 3.0 2.4 IOH (cid:16)24 mA 3.0 2.2 VOL LOW Level Output Voltage IOL 100 PA 2.3 (cid:16) 3.6 0.2 IOL 8 mA 2.3 0.6 IOL 12 mA 2.7 0.4 V IOL 16 mA 3.0 0.4 IOL 24 mA 3.0 0.55 II Input Leakage Current 0 d VI d 5.5V 2.3 (cid:16) 3.6 r5.0 PA IOZ 3-STATE Output Leakage 0 d VO d 5.5V 2.3 (cid:16) 3.6 r5.0 PA VI VIH or VIL IOFF Power-Off Leakage Current VI or VO 5.5V 0 10 PA www.fairchildsemi.com 4

7 DC Electrical Characteristics 4 (Continued) L C X VCC TA (cid:16)40qC to (cid:14)85qC 1 Symbol Parameter Conditions Units 6 (V) Min Max 3 ICC Quiescent Supply Current VI VCC or GND 2.3 (cid:16) 3.6 20 PA 74 3.6V d VI, VO d 5.5V (Note 7) 2.3 (cid:16) 3.6 r20 ’ICC Increase in ICC per Input VIH VCC (cid:16)0.6V 2.3 (cid:16) 3.6 500 PA Note 7: Outputs disabled or 3-STATE only. AC Electrical Characteristics TA (cid:16)40q to (cid:14)85qC, RL 500: VCC 3.3V r 0.3V VCC 2.7V VCC 2.5V r 0.2V Symbol Parameter Units CL 50 pF CL 50 pF CL 30 pF Min Max Min Max Min Max fMAX Maximum Clock Frequency 170 MHz tPHL Propagation Delay 1.5 6.2 1.5 6.5 1.5 7.4 ns tPLH CP to On 1.5 6.2 1.5 6.5 1.5 7.4 tPZL Output Enable time 1.5 6.1 1.5 6.3 1.5 7.9 ns tPZH 1.5 6.1 1.5 6.3 1.5 7.9 tPLZ Output Disable Time 1.5 6.0 1.5 6.2 1.5 7.2 ns tPHZ 1.5 6.0 1.5 6.2 1.5 7.2 tS Setup Time 2.5 2.5 3.0 ns tH Hold Time 1.5 1.5 2.0 ns tW Pulse Width 3.0 3.0 3.5 ns tOSHL Output to Output Skew (Note 8) 1.0 ns tOSLH 1.0 Note 8: Skew is defined as the absolute value of the differences between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design. Dynamic Switching Characteristics VCC TA 25qC Symbol Parameter Conditions Units (V) Typical VOLP Quiet Output Dynamic Peak VOL CL 50 pF, VIH 3.3V, VIL 0V 3.3 0.8 V CL 30 pF, VIH 2.5V, VIL 0V 2.5 0.6 VOLV Quiet Output Dynamic Valley VOL CL 50 pF, VIH 3.3V, VIL 0V 3.3 (cid:16)0.8 V CL 30 pF, VIH 2.5V, VIL 0V 2.5 0.6 Capacitance Symbol Parameter Conditions Typical Units CIN Input Capacitance VCC Open, VI 0V or VCC 7 pF COUT Output Capacitance VCC 3.3V, VI 0V or VCC 8 pF CPD Power Dissipation Capacitance VCC 3.3V, VI 0V or VCC, f 10 MHz 20 pF 5 www.fairchildsemi.com

4 7 AC LOADING and WAVEFORMS 3 Generic for LCX Family 6 1 X C L 4 7 FIGURE 1. AC Test Circuit (CL includes probe and jig capacitance) Test Switch tPLH, tPHL Open tPZL, tPLZ 6V at VCC 3.3 r 0.3V, and 2.7V VCC x 2 at VCC 2.5 r 0.2V tPZH, tPHZ GND Waveform for Inverting and Non-Inverting Functions 3-STATE Output High Enable and Disable Times for Logic Propagation Delay. Pulse Width and trec Waveforms Setup Time, Hold Time and Recovery Time for Logic 3-STATE Output Low Enable and trise and tfall Disable Times for Logic FIGURE 2. Waveforms (Input Characteristics; f = 1MHz, tr = tf = 3ns) VCC Symbol 3.3V r 0.3V 2.7V 2.5V r 0.2V Vmi 1.5V 1.5V VCC/2 Vmo 1.5V 1.5V VCC/2 Vx VOL (cid:14) 0.3V VOL (cid:14) 0.3V VOL (cid:14) 0.15V Vy VOH (cid:16) 0.3V VOH (cid:16) 0.3V VOH (cid:16) 0.15V www.fairchildsemi.com 6

7 Schematic Diagram 4 Generic for LCX Family L C X 1 6 3 7 4 7 www.fairchildsemi.com

4 7 Physical Dimensions 3 inches (millimeters) unless otherwise noted 6 1 X C L 4 7 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide Package Number BGA54A www.fairchildsemi.com 8

7 Physical Dimensions 4 inches (millimeters) unless otherwise noted (Continued) L C X 1 6 3 7 4 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide Package Number MS48A 9 www.fairchildsemi.com

s ut Physical Dimensions inches (millimeters) unless otherwise noted (Continued) p t u O d n a s t u p n I t n a r e l o T V 5 h t i w p o l F - p i l F e p y T - D t i B - 6 1 e g a t l o V w o L 4 7 3 6 1 X 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide C Package Number MTD48 L 4 7 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems 2. A critical component in any component of a life support which, (a) are intended for surgical implant into the device or system whose failure to perform can be rea- body, or (b) support or sustain life, and (c) whose failure sonably expected to cause the failure of the life support to perform when properly used in accordance with device or system, or to affect its safety or effectiveness. instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the www.fairchildsemi.com user. www.fairchildsemi.com 10

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