74HC74; 74HCT74 Dual D-type flip-flop with set and reset; positive edge-trigger Rev. 6 — 21 April 2020 Product data sheet 1. General description The 74HC74 and 74HCT74 are dual positive edge triggered D-type flip-flop. They have individual data (nD), clock (nCP), set (nSD) and reset (nRD) inputs, and complementary nQ and nQ outputs. Data at the nD-input, that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition, is stored in the flip-flop and appears at the nQ output. Schmitt-trigger action in the clock input, makes the circuit highly tolerant to slower clock rise and fall times. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of V . CC 2. Features and benefits • Input levels: • For 74HC74: CMOS level • For 74HCT74: TTL level • Symmetrical output impedance • Low power dissipation • High noise immunity • Balanced propagation delays • Specified in compliance with JEDEC standard no. 7A • ESD protection: • HBM JESD22-A114F exceeds 2000 V • MM JESD22-A115-A exceeds 200 V • Multiple package options • Specified from -40 °C to +85 °C and from -40 °C to +125 °C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC74D -40 °C to +125 °C SO14 plastic small outline package; 14 leads; SOT108-1 body width 3.9 mm 74HCT74D 74HC74DB -40 °C to +125 °C SSOP14 plastic shrink small outline package; 14 leads; SOT337-1 body width 5.3 mm 74HCT74DB 74HC74PW -40 °C to +125 °C TSSOP14 plastic thin shrink small outline package; 14 leads; SOT402-1 body width 4.4 mm 74HCT74PW 74HC74BQ -40 °C to +125 °C DHVQFN14 plastic dual in-line compatible thermal enhanced SOT762-1 very thin quad flat package; no leads; 14 terminals; 74HCT74BQ body 2.5 × 3 × 0.85 mm

Nexperia 74HC74; 74HCT74 Dual D-type flip-flop with set and reset; positive edge-trigger 4. Functional diagram 1SD 4 SD 1D 1Q 2 D Q 5 1CP 3 CP FF 1Q Q 6 4 RD 4 10 S 5 1SD 2SD 3 C1 1 1RD SD 2 1D 6 10 2SD 2 1D 1Q 5 1 R D Q 12 2D 2Q 9 SD 3 1CP CP 12 2D D Q 2Q 9 11 2CP 10 FF S 9 2CP RD Q 12QQ 68 1112 1CD1 8 11 CPFF Q 2Q 8 1RD 2RD 13 R RD 1 13 mna418 mna419 13 2RD mna420 Fig. 1. Logic symbol Fig. 2. IEC logic symbol Fig. 3. Functional diagram Q C C C C C C D Q C C RD SD mna421 CP C C Fig. 4. Logic diagram for one flip-flop 74HC_HCT74 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2020. All rights reserved Product data sheet Rev. 6 — 21 April 2020 2 / 18

Nexperia 74HC74; 74HCT74 Dual D-type flip-flop with set and reset; positive edge-trigger 5. Pinning information 5.1. Pinning 74HC74 74HCT74 D C terminal 1 R C 1 V index area 1 14 1D 2 13 2RD 1CP 3 12 2D 74HC74 74HCT74 1SD 4 11 2CP 1Q 5 GND(1) 10 2SD 1RD 1 14 VCC 1Q 6 9 2Q 1D 2 13 2RD 7 8 1CP 3 12 2D D Q 1SD 4 11 2CP GN 2 aaa-003909 1Q 5 10 2SD Transparent top view 1Q 6 9 2Q (1) This is not a ground pin. There is no electrical or GND 7 8 2Q mechanical requirement to solder the pad. In case aaa-003908 soldered, the solder land should remain floating or connected to GND. Fig. 5. Pin configuration for SOT108-1 (SO14), SOT337-1 (SSOP14) and SOT402-1 (TSSOP14) Fig. 6. Pin configuration for SOT762-1 (DHVQFN14) 5.2. Pin description Table 2. Pin description Symbol Pin Description 1RD 1 asynchronous reset-direct input (active LOW) 1D 2 data input 1CP 3 clock input (LOW-to-HIGH, edge-triggered) 1SD 4 asynchronous set-direct input (active LOW) 1Q 5 output 1Q 6 complement output GND 7 ground (0 V) 2Q 8 complement output 2Q 9 output 2SD 10 asynchronous set-direct input (active LOW) 2CP 11 clock input (LOW-to-HIGH, edge-triggered) 2D 12 data input 2RD 13 asynchronous reset-direct input (active LOW) V 14 supply voltage CC 74HC_HCT74 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2020. All rights reserved Product data sheet Rev. 6 — 21 April 2020 3 / 18

Nexperia 74HC74; 74HCT74 Dual D-type flip-flop with set and reset; positive edge-trigger 6. Functional description Table 3. Function table H = HIGH voltage level; L = LOW voltage level; X = don’t care. Input Output nSD nRD nCP nD nQ nQ L H X X H L H L X X L H L L X X H H Table 4. Function table H = HIGH voltage level; L = LOW voltage level; X = don’t care; ↑ = LOW-to-HIGH transition; Q = state after the next LOW-to-HIGH CP transition. n+1 Input Output nSD nRD nCP nD nQ nQ n+1 n+1 H H ↑ L L H H H ↑ H H L 7. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit V supply voltage -0.5 +7 V CC I input clamping current V < -0.5 V or V > V + 0.5 V - ±20 mA IK I I CC I output clamping current V < -0.5 V or V > V + 0.5 V - ±20 mA OK O O CC I output current V = -0.5 V to (V + 0.5 V) - ±25 mA O O CC I supply current - +100 mA CC I ground current -100 - mA GND T storage temperature -65 +150 °C stg P total power dissipation [1] - 500 mW tot [1] For SOT108-1 (SO14) package: Ptot derates linearly with 10.1 mW/K above 100 °C. For SOT337-1 (SSOP14) package: Ptot derates linearly with 7.3 mW/K above 81 °C. For SOT402-1 (TSSOP14) package: Ptot derates linearly with 7.3 mW/K above 81 °C. For SOT762-1 (DHVQFN14) package: Ptot derates linearly with 9.6 mW/K above 98 °C. 74HC_HCT74 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2020. All rights reserved Product data sheet Rev. 6 — 21 April 2020 4 / 18

Nexperia 74HC74; 74HCT74 Dual D-type flip-flop with set and reset; positive edge-trigger 8. Recommended operating conditions Table 6. Recommended operating conditions Voltages are referenced to GND (ground = 0 V) Symbol Parameter Conditions 74HC74 74HCT74 Unit Min Typ Max Min Typ Max V supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V CC V input voltage 0 - V 0 - V V I CC CC V output voltage 0 - V 0 - V V O CC CC T ambient temperature -40 +25 +125 -40 +25 +125 °C amb Δt/ΔV input transition rise and fall rate V = 2.0 V - - 625 - - - ns/V CC V = 4.5 V - 1.67 139 - 1.67 139 ns/V CC V = 6.0 V - - 83 - - - ns/V CC 9. Static characteristics Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions T = -40 °C to +85 °C T = -40 °C Unit amb amb to +125 °C Min Typ [1] Max Min Max 74HC74 V HIGH-level V = 2.0 V 1.5 1.2 - 1.5 - V IH CC input voltage V = 4.5 V 3.15 2.4 - 3.15 - V CC V = 6.0 V 4.2 3.2 - 4.2 - V CC V LOW-level V = 2.0 V - 0.8 0.5 - 0.5 V IL CC input voltage V = 4.5 V - 2.1 1.35 - 1.35 V CC V = 6.0 V - 2.8 1.8 - 1.8 V CC V HIGH-level V = V or V OH I IH IL output voltage I = -4.0 mA; V = 4.5 V 3.84 4.32 - 3.7 - V O CC I = -5.2 mA; V = 6.0 V 5.34 5.81 - 5.2 - V O CC V LOW-level V = V or V OL I IH IL output voltage I = 4.0 mA; V = 4.5 V - 0.15 0.33 - 0.4 V O CC I = 5.2 mA; V = 6.0 V - 0.16 0.33 - 0.4 V O CC I input leakage V = V or GND; V = 6.0 V - - ±1.0 - ±1.0 μA I I CC CC current I supply current V = V or GND; I = 0 A; - - 40 - 80 μA CC I CC O V = 6.0 V CC C input - 3.5 - - - pF I capacitance 74HCT74 V HIGH-level V = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - V IH CC input voltage V LOW-level V = 4.5 V to 5.5 V - 1.2 0.8 - 0.8 V IL CC input voltage 74HC_HCT74 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2020. All rights reserved Product data sheet Rev. 6 — 21 April 2020 5 / 18

Nexperia 74HC74; 74HCT74 Dual D-type flip-flop with set and reset; positive edge-trigger Symbol Parameter Conditions T = -40 °C to +85 °C T = -40 °C Unit amb amb to +125 °C Min Typ [1] Max Min Max V HIGH-level V = V or V ; V = 4.5 V OH I IH IL CC output voltage I = -4 mA 3.84 4.32 - 3.7 - V O V LOW-level V = V or V ; V = 4.5 V OL I IH IL CC output voltage I = 4.0 mA - 0.15 0.33 - 0.4 V O I input leakage V = V or GND; V = 5.5 V - - ±1.0 - ±1.0 μA I I CC CC current I supply current V = V or GND; I = 0 A; - - 40 - 80 μA CC I CC O V = 5.5 V CC ΔI additional V = V - 2.1 V; CC I CC supply current other inputs at V or GND; CC V = 4.5 V to 5.5 V; I = 0 A CC O per input pin; nD, nRD inputs - 70 315 - 343 μA per input pin; nSD, nCP input - 80 360 - 392 μA C input - 3.5 - - - pF I capacitance [1] All typical values are measured at Tamb = 25 °C. 10. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); C = 50 pF unless otherwise specified; for test circuit see Fig. 9. L Symbol Parameter Conditions T = -40 °C to +85 °C T = -40 °C Unit amb amb to +125 °C Min Typ [1] Max Min Max 74HC74 t propagation nCP to nQ, nQ; see Fig. 7 [2] pd delay V = 2.0 V - 47 220 - 265 ns CC V = 4.5 V - 17 44 - 53 ns CC V = 5 V; C = 15 pF - 14 - - - ns CC L V = 6.0 V - 14 37 - 45 ns CC nSD to nQ, nQ; see Fig. 8 [2] V = 2.0 V - 50 250 - 300 ns CC V = 4.5 V - 18 50 - 60 ns CC V = 5 V; C = 15 pF - 15 - - - ns CC L V = 6.0 V - 14 43 - 51 ns CC nRD to nQ, nQ; see Fig. 8 [2] V = 2.0 V - 52 250 - 300 ns CC V = 4.5 V - 19 50 - 60 ns CC V = 5 V; C = 15 pF - 16 - - - ns CC L V = 6.0 V - 15 43 - 51 ns CC t transition time nQ, nQ; see Fig. 7 [3] t V = 2.0 V - 19 95 - 110 ns CC V = 4.5 V - 7 19 - 22 ns CC V = 6.0 V - 6 16 - 19 ns CC 74HC_HCT74 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2020. All rights reserved Product data sheet Rev. 6 — 21 April 2020 6 / 18

Nexperia 74HC74; 74HCT74 Dual D-type flip-flop with set and reset; positive edge-trigger Symbol Parameter Conditions T = -40 °C to +85 °C T = -40 °C Unit amb amb to +125 °C Min Typ [1] Max Min Max t pulse width nCP HIGH or LOW; see Fig. 7 W V = 2.0 V 100 19 - 120 - ns CC V = 4.5 V 20 7 - 24 - ns CC V = 6.0 V 17 6 - 20 - ns CC nSD, nRD LOW; see Fig. 8 V = 2.0 V 100 19 - 120 - ns CC V = 4.5 V 20 7 - 24 - ns CC V = 6.0 V 17 6 - 20 - ns CC t recovery time nSD, nRD; see Fig. 8 rec V = 2.0 V 40 3 - 45 - ns CC V = 4.5 V 8 1 - 9 - ns CC V = 6.0 V 7 1 - 8 - ns CC t set-up time nD to nCP; see Fig. 7 su V = 2.0 V 75 6 - 90 - ns CC V = 4.5 V 15 2 - 18 - ns CC V = 6.0 V 13 2 - 15 - ns CC t hold time nD to nCP; see Fig. 7 h V = 2.0 V 3 -6 - 3 - ns CC V = 4.5 V 3 -2 - 3 - ns CC V = 6.0 V 3 -2 - 3 - ns CC f maximum nCP; see Fig. 7 max frequency V = 2.0 V 4.8 23 - 4.0 - MHz CC V = 4.5 V 24 69 - 20 - MHz CC V = 5 V; C = 15 pF - 76 - - - MHz CC L V = 6.0 V 28 82 - 24 - MHz CC C power C = 50 pF; f = 1 MHz; [4] - 24 - - - pF PD L dissipation V = GND to V I CC capacitance 74HCT74 t propagation nCP to nQ, nQ; see Fig. 7 [2] pd delay V = 4.5 V - 18 44 - 53 ns CC V = 5 V; C = 15 pF - 15 - - - ns CC L nSD to nQ, nQ; see Fig. 8 [2] V = 4.5 V - 23 50 - 60 ns CC V = 5 V; C = 15 pF - 18 - - - ns CC L nRD to nQ, nQ; see Fig. 8 [2] V = 4.5 V - 24 50 - 60 ns CC V = 5 V; C = 15 pF - 18 - - - ns CC L 74HC_HCT74 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2020. All rights reserved Product data sheet Rev. 6 — 21 April 2020 7 / 18

Nexperia 74HC74; 74HCT74 Dual D-type flip-flop with set and reset; positive edge-trigger Symbol Parameter Conditions T = -40 °C to +85 °C T = -40 °C Unit amb amb to +125 °C Min Typ [1] Max Min Max t transition time nQ, nQ; see Fig. 7 [3] t V = 4.5 V - 7 19 - 22 ns CC t pulse width nCP HIGH or LOW; see Fig. 7 W V = 4.5 V 23 9 - 27 - ns CC nSD, nRD LOW; see Fig. 8 V = 4.5 V 20 9 - 24 - ns CC t recovery time nSD, nRD; see Fig. 8 rec V = 4.5 V 8 1 - 9 - ns CC t set-up time nD to nCP; see Fig. 7 su V = 4.5 V 15 5 - 18 - ns CC t hold time nD to nCP; see Fig. 7 h V = 4.5 V 3 -3 - 3 - ns CC f maximum nCP; see Fig. 7 max frequency V = 4.5 V 22 54 - 18 - MHz CC V = 5 V; C = 15 pF - 59 - - - MHz CC L C power C = 50 pF; f = 1 MHz; [4] - 29 - - - pF PD L dissipation V = GND to V - 1.5 V I CC capacitance [1] All typical values are measured at Tamb = 25 °C. [2] tpd is the same as tPLH and tPHL. [3] tt is the same as tTHL and tTLH. [4] CPD is used to determine the dynamic power dissipation (PD in μW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; Σ(CL × VCC2 × fo) = sum of outputs. 74HC_HCT74 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2020. All rights reserved Product data sheet Rev. 6 — 21 April 2020 8 / 18

Nexperia 74HC74; 74HCT74 Dual D-type flip-flop with set and reset; positive edge-trigger 10.1. Waveforms VI nD input VM GND th th tsu tsu 1/fmax VI nCP input VM GND tW tPHL tPLH VOH nQ output VM VOL tPLH tPHL VOH 90 % 90 % nQ output VM 10 % 10 % VOL tTLH tTHL aaa-004005 Measurement points are given in Table 9. V and V are typical voltage output levels that occur with the output load. OL OH Fig. 7. Propagation delay input (CP) to output (Qn), output transition time, clock input (CP) pulse width and the maximum frequency (CP) 74HC_HCT74 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2020. All rights reserved Product data sheet Rev. 6 — 21 April 2020 9 / 18

Nexperia 74HC74; 74HCT74 Dual D-type flip-flop with set and reset; positive edge-trigger VI nCP input VM GND trec VI nSD input VM GND tW tW VI nRD input VM GND tPLH tPHL VOH nQ output VM VOL VOH nQ output VM VOL tPHL tPLH mna423 Measurement points are given in Table 9. V and V are typical voltage output levels that occur with the output load. OL OH Fig. 8. The set (nSD) and reset (nRD) input to output (nQ,nQ) propagation delays, set and reset pulse widths and the nSD, nRD to nCP recovery time Table 9. Measurement points Type Input Output V V M M 74HC74 0.5V 0.5V CC CC 74HCT74 1.3 V 1.3 V 74HC_HCT74 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2020. All rights reserved Product data sheet Rev. 6 — 21 April 2020 10 / 18

Nexperia 74HC74; 74HCT74 Dual D-type flip-flop with set and reset; positive edge-trigger VI tW 90 % negative pulse VM VM 10 % GND tf tr tr tf VI 90 % positive pulse VM VM 10 % GND tW VCC VI VO G DUT RT CL 001aah768 Test data is given in Table 10. Definitions test circuit: R = Termination resistance should be equal to output impedance Z of the pulse generator. T o C = Load capacitance including jig and probe capacitance. L R = Load resistance. L S1 = Test selection switch. Fig. 9. Test circuit for measuring switching times Table 10. Test data Type Input Load Test V t, t C R I r f L L 74HC74 V 6 ns 15 pF, 50 pF 1 kΩ t , t CC PLH PHL 74HCT74 3 V 6 ns 15 pF, 50 pF 1 kΩ t , t PLH PHL 74HC_HCT74 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2020. All rights reserved Product data sheet Rev. 6 — 21 April 2020 11 / 18

Nexperia 74HC74; 74HCT74 Dual D-type flip-flop with set and reset; positive edge-trigger 11. Package outline SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y H E v M A Z 14 8 Q A 2 A 1 (A 3 ) A pin 1 index θ L p 1 7 L e w M detail X b p 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mAax . A 1 A 2 A 3 b p c D (1) E (1) e H E L L p Q v w y Z (1) θ 0.25 1.45 0.49 0.25 8.75 4.0 6.2 1.0 0.7 0.7 mm 1.75 0.25 1.27 1.05 0.25 0.25 0.1 0.10 1.25 0.36 0.19 8.55 3.8 5.8 0.4 0.6 0.3 8 o 0.010 0.057 0.019 0.0100 0.35 0.16 0.244 0.039 0.028 0.028 0 o inches 0.069 0.01 0.05 0.041 0.01 0.01 0.004 0.004 0.049 0.014 0.0075 0.34 0.15 0.228 0.016 0.024 0.012 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE REFERENCES EUROPEAN ISSUE DATE VERSION IEC JEDEC JEITA PROJECTION 99-12-27 SOT108-1 076E06 MS-012 03-02-19 Fig. 10. Package outline SOT108-1 (SO14) 74HC_HCT74 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2020. All rights reserved Product data sheet Rev. 6 — 21 April 2020 12 / 18

Nexperia 74HC74; 74HCT74 Dual D-type flip-flop with set and reset; positive edge-trigger SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1 D E A X c y H E v M A Z 14 8 Q A 2 A 1 (A 3 ) A pin 1 index θ L p L 1 7 detail X w M e b p 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT mAax . A 1 A 2 A 3 b p c D (1) E (1) e H E L L p Q v w y Z (1) θ 0.21 1.80 0.38 0.20 6.4 5.4 7.9 1.03 0.9 1.4 8 o mm 2 0.05 1.65 0.25 0.25 0.09 6.0 5.2 0.65 7.6 1.25 0.63 0.7 0.2 0.13 0.1 0.9 0 o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE REFERENCES EUROPEAN ISSUE DATE VERSION IEC JEDEC JEITA PROJECTION 99-12-27 SOT337-1 MO-150 03-02-19 Fig. 11. Package outline SOT337-1 (SSOP14) 74HC_HCT74 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2020. All rights reserved Product data sheet Rev. 6 — 21 April 2020 13 / 18

Nexperia 74HC74; 74HCT74 Dual D-type flip-flop with set and reset; positive edge-trigger TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 D E A X c y H E v M A Z 14 8 Q A 2 (A 3 ) A pin 1 index A 1 θ L p L 1 7 detail X w M e b p 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT mAax . A 1 A 2 A 3 b p c D (1) E (2) e H E L L p Q v w y Z (1) θ 0.15 0.95 0.30 0.2 5.1 4.5 6.6 0.75 0.4 0.72 8 o mm 1.1 0.05 0.80 0.25 0.19 0.1 4.9 4.3 0.65 6.2 1 0.50 0.3 0.2 0.13 0.1 0.38 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE REFERENCES EUROPEAN ISSUE DATE VERSION IEC JEDEC JEITA PROJECTION 99-12-27 SOT402-1 MO-153 03-02-18 Fig. 12. Package outline SOT402-1 (TSSOP14) 74HC_HCT74 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2020. All rights reserved Product data sheet Rev. 6 — 21 April 2020 14 / 18

Nexperia 74HC74; 74HCT74 Dual D-type flip-flop with set and reset; positive edge-trigger DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.5 x 3 x 0.85 mm SOT762-1 D B A A A1 E c terminal 1 detail X index area terminal 1 C e1 index area e b v C A B y1C y w C 2 6 L 1 7 Eh e 14 8 k 13 9 Dh X k 0 2 4 mm scale Dimensions (mm are the original dimensions) Unit A(1) A1 b c D(1) Dh E(1) Eh e e1 k L v w y y1 max 1 0.05 0.30 3.1 1.65 2.6 1.15 0.5 mm nom 0.02 0.25 0.2 3.0 1.50 2.5 1.00 0.5 2 0.4 0.1 0.05 0.05 0.1 min 0.00 0.18 2.9 1.35 2.4 0.85 0.2 0.3 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. sot762-1_po Outline References European Issue date version IEC JEDEC JEITA projection 15-04-10 SOT762-1 MO-241 15-05-05 Fig. 13. Package outline SOT762-1 (DHVQFN14) 74HC_HCT74 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2020. All rights reserved Product data sheet Rev. 6 — 21 April 2020 15 / 18

Nexperia 74HC74; 74HCT74 Dual D-type flip-flop with set and reset; positive edge-trigger 12. Abbreviations Table 11. Abbreviations Acronym Description CMOS Complementary Metal Oxide Semiconductor ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 13. Revision history Table 12. Revision history Document ID Release date Data sheet status Change notice Supersedes 74HC_HCT74 v.6 20200421 Product data sheet - 74HC_HCT74 v.5 Modifications: • The format of this data sheet has been redesigned to comply with the identity guidelines of Nexperia. • Legal texts have been adapted to the new company name where appropriate. • Fig. 6: Pin configuration for SOT762-1 (DHVQFN14) corrected (errata). • Table 5: Derating values for P total power dissipation updated. tot 74HC_HCT74 v.5 20151203 Product data sheet - 74HC_HCT74 v.4 Modifications: • Type numbers 74HC74N and 74HCT74N (SOT27-1) removed. 74HC_HCT74 v.4 20120827 Product data sheet - 74HC_HCT74 v.3 Modifications: • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. 74HC_HCT74 v.3 20030710 Product data sheet - 74HC_HCT74_CNV v.2 74HC_HCT74_CNV v.2 19980223 Product specification - - 74HC_HCT74 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2020. All rights reserved Product data sheet Rev. 6 — 21 April 2020 16 / 18

Nexperia 74HC74; 74HCT74 Dual D-type flip-flop with set and reset; positive edge-trigger injury, death or severe property or environmental damage. Nexperia and its 14. Legal information suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Quick reference data — The Quick reference data is an extract of the Data sheet status product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Document status Product Definition Applications — Applications that are described herein for any of these [1][2] status [3] products are for illustrative purposes only. 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Nexperia’s specifications such use shall be solely at customer’s own risk, Notwithstanding any damages that customer might incur for any reason and (c) customer fully indemnifies Nexperia for any liability, damages or failed whatsoever, Nexperia’s aggregate and cumulative liability towards customer product claims resulting from customer design and use of the product for for the products described herein shall be limited in accordance with the automotive applications beyond Nexperia’s standard warranty and Nexperia’s Terms and conditions of commercial sale of Nexperia. product specifications. Right to make changes — Nexperia reserves the right to make changes Translations — A non-English (translated) version of a document is for to information published in this document, including without limitation reference only. The English version shall prevail in case of any discrepancy specifications and product descriptions, at any time and without notice. This between the translated and English versions. document supersedes and replaces all information supplied prior to the publication hereof. Trademarks Suitability for use — Nexperia products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical Notice: All referenced brands, product names, service names and systems or equipment, nor in applications where failure or malfunction trademarks are the property of their respective owners. of an Nexperia product can reasonably be expected to result in personal 74HC_HCT74 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2020. All rights reserved Product data sheet Rev. 6 — 21 April 2020 17 / 18

Nexperia 74HC74; 74HCT74 Dual D-type flip-flop with set and reset; positive edge-trigger Contents 1. General description......................................................1 2. Features and benefits..................................................1 3. Ordering information....................................................1 4. Functional diagram.......................................................2 5. Pinning information......................................................3 5.1. Pinning.........................................................................3 5.2. Pin description.............................................................3 6. Functional description.................................................4 7. Limiting values.............................................................4 8. Recommended operating conditions..........................5 9. Static characteristics....................................................5 10. Dynamic characteristics............................................6 10.1. Waveforms.................................................................9 11. Package outline........................................................12 12. Abbreviations............................................................16 13. Revision history........................................................16 14. Legal information......................................................17 © Nexperia B.V. 2020. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 21 April 2020 74HC_HCT74 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2020. All rights reserved Product data sheet Rev. 6 — 21 April 2020 18 / 18