74HC32; 74HCT32 Quad 2-input OR gate Rev. 5 — 4 September 2012 Product data sheet 1. General description The 74HC32; 74HCT32 is a quad 2-input OR gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of V . CC 2. Features and benefits  Wide supply voltage range from 2.0 V to 6.0 V  Complies with JEDEC standard JESD7A  Symmetrical output impedance  High noise immunity  Low power dissipation  Balanced propagation delays  Input levels: For 74HC32: CMOS level For 74HCT32: TTL level  ESD protection: HBM JESD22-A114F exceeds 2000V MM JESD22-A115-A exceeds 200V  Multiple package options  Specified from 40C to +85C and from 40C to +125C

74HC32; 74HCT32 NXP Semiconductors Quad 2-input OR gate 3. Ordering information Table 1. Ordering info rmation Type number Package Temperature range Name Description Version 74HC32N 40 C to +125 C DIP14 plastic dual in-line package; 14leads (300mil) SOT27-1 74HCT32N 74HC32D 40 C to +125 C SO14 plastic small outline package; 14leads; body width SOT108-1 3.9mm 74HCT32D 74HC32DB 40 C to +125 C SSOP14 plastic shrink small outline package; 14leads; body SOT337-1 width 5.3mm 74HCT32DB 74HC32PW 40 C to +125 C TSSOP14 plastic thin shrink small outline package; 14leads; SOT402-1 body width 4.4mm 74HCT32PW 74HC32BQ 40 C to +125 C DHVQFN14 plastic dual in-line compatible thermal enhanced very SOT762-1 thin quad flat package; no leads; 14 terminals; 74HCT32BQ body2.530.85mm 4. Functional diagram 1 ≥1 3 2 4 1 1A ≥1 6 1Y 3 5 2 1B 4 2A 2Y 6 9 5 2B ≥1 8 9 3A 10 3Y 8 10 3B A 1132 44AB 4Y 11 1132 ≥1 11 Y B mna242 mna243 mna241 Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram (one gate) 74HC_HCT32 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 5 — 4 September 2012 2 of 17

74HC32; 74HCT32 NXP Semiconductors Quad 2-input OR gate 5. Pinning information 5.1 Pinning C terminal 1 A C 1A 1 14 VCC index area 1 V 1 14 1B 2 13 4B 1B 2 13 4B 1Y 3 12 4A 1Y 3 12 4A 2A 4 32 11 4Y 2A 4 32 11 4Y 2B 5 GND(1) 10 3B 2B 5 10 3B 2Y 6 9 3A 2Y 6 9 3A 7 8 D Y GND 7 8 3Y GN 3 001aad102 001aad101 Transparent top view (1) The die substrate is attached to this pad using conductive die attach material. It cannot be used as a supply pin or input. Fig 4. Pin configuration DIP14, SO14 and (T)SSOP14 Fig 5. Pin configuration DHVQFN14 5.2 Pin description Table 2. Pin descripti on Symbol Pin Description 1A to 4A 1, 4, 9, 12 data input 1B to 4B 2, 5, 10,13 data input 1Y to 4Y 3, 6, 8, 11 data output GND 7 ground (0 V) V 14 supply voltage CC 6. Functional description Table 3. Function tab le[1] Input Output nA nB nY L L L L H H H L H H H H [1] H=HIGH voltage level; L=LOW voltage level; X=don’t care. 74HC_HCT32 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 5 — 4 September 2012 3 of 17

74HC32; 74HCT32 NXP Semiconductors Quad 2-input OR gate 7. Limiting values Table 4. Limiting valu es In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit V supply voltage 0.5 +7 V CC I input clamping current V < 0.5V or V >V +0.5 V [1] - 20 mA IK I I CC I output clamping current V <0.5V or V >V +0.5V [1] - 20 mA OK O O CC I output current 0.5V < V < V +0.5V - 25 mA O O CC I supply current - 50 mA CC I ground current 50 - mA GND T storage temperature 65 +150 C stg P total power dissipation [2] tot DIP14 package - 750 mW SO14, (T)SSOP14 and - 500 mW DHVQFN14 packages [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] For DIP14 package: Ptot derates linearly with 12mW/K above 70 C. For SO14 package: Ptot derates linearly with 8mW/K above 70 C. For (T)SSOP14 packages: Ptot derates linearly with 5.5mW/K above 60C. For DHVQFN14 packages: Ptot derates linearly with 4.5mW/K above 60C. 8. Recommended operating conditions Table 5. Recommend ed operating conditions Voltages are referenced to GND (ground = 0V) Symbol Parameter Conditions 74HC32 74HCT32 Unit Min Typ Max Min Typ Max V supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V CC V input voltage 0 - V 0 - V V I CC CC V output voltage 0 - V 0 - V V O CC CC T ambient temperature 40 - +125 40 - +125 C amb t/V input transition rise and fall rate V = 2.0 V - - 625 - - - ns/V CC V = 4.5 V - 1.67 139 - 1.67 139 ns/V CC V = 6.0 V - - 83 - - - ns/V CC 74HC_HCT32 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 5 — 4 September 2012 4 of 17

74HC32; 74HCT32 NXP Semiconductors Quad 2-input OR gate 9. Static characteristics Table 6. Static charac teristics At recommended operating conditions; voltages are referenced to GND (ground=0V). Symbol Parameter Conditions 25C 40C to +85C 40C to +125C Unit Min Typ Max Min Max Min Max 74HC32 V HIGH-level V = 2.0V 1.5 1.2 - 1.5 - 1.5 - V IH CC inputvoltage V = 4.5V 3.15 2.4 - 3.15 - 3.15 - V CC V = 6.0V 4.2 3.2 - 4.2 - 4.2 - V CC V LOW-level V = 2.0V - 0.8 0.5 - 0.5 - 0.5 V IL CC inputvoltage V = 4.5V - 2.1 1.35 - 1.35 - 1.35 V CC V = 6.0V - 2.8 1.8 - 1.8 - 1.8 V CC V HIGH-level V = V or V OH I IH IL outputvoltage I = 20A; V = 2.0V 1.9 2.0 - 1.9 - 1.9 - V O CC I = 20A; V = 4.5V 4.4 4.5 - 4.4 - 4.4 - V O CC I = 20A; V = 6.0V 5.9 6.0 - 5.9 - 5.9 - V O CC I = 4.0mA; V = 4.5V 3.98 4.32 - 3.84 - 3.7 - V O CC I = 5.2mA; V = 6.0V 5.48 5.81 - 5.34 - 5.2 - V O CC V LOW-level V = V or V OL I IH IL outputvoltage I = 20A; V = 2.0V - 0 0.1 - 0.1 - 0.1 V O CC I = 20A; V = 4.5V - 0 0.1 - 0.1 - 0.1 V O CC I = 20A; V = 6.0V - 0 0.1 - 0.1 - 0.1 V O CC I = 4.0mA; V = 4.5V - 0.15 0.26 - 0.33 - 0.4 V O CC I = 5.2mA; V = 6.0V - 0.16 0.26 - 0.33 - 0.4 V O CC I input leakage V = V or GND; - - 0.1 - 1 - 1 A I I CC current V =6.0V CC I supply current V = V or GND; I =0A; - - 2.0 - 20 - 40 A CC I CC O V =6.0V CC C input - 3.5 - - - - - pF I capacitance 74HCT32 V HIGH-level V = 4.5V to 5.5V 2.0 1.6 - 2.0 - 2.0 - V IH CC inputvoltage V LOW-level V = 4.5V to 5.5V - 1.2 0.8 - 0.8 - 0.8 V IL CC inputvoltage V HIGH-level V = V or V ; V = 4.5V OH I IH IL CC outputvoltage I = 20A 4.4 4.5 - 4.4 - 4.4 - V O I = 4.0mA 3.98 4.32 - 3.84 - 3.7 - V O V LOW-level V = V or V ; V = 4.5V OL I IH IL CC outputvoltage I = 20A - 0 0.1 - 0.1 - 0.1 V O I = 5.2mA - 0.15 0.25 - 0.33 - 0.4 V O I input leakage V = V or GND; - - 0.1 - 1 - 1 A I I CC current V =5.5V CC 74HC_HCT32 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 5 — 4 September 2012 5 of 17

74HC32; 74HCT32 NXP Semiconductors Quad 2-input OR gate Table 6. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground=0V). Symbol Parameter Conditions 25C 40C to +85C 40C to +125C Unit Min Typ Max Min Max Min Max I supply current V = V or GND; I =0A; - - 2.0 - 20 - 40 A CC I CC O V =5.5V CC I additional per input pin; - - 430 - 540 - 590 A CC supply current V =V 2.1V; I =0A; I CC O otherinputs at V or GND; CC V =4.5Vto5.5V CC C input - 3.5 - - - - - pF I capacitance 10. Dynamic characteristics Table 7. Dynamic cha racteristics GND=0V; C =50pF; for load circuit see Figure7. L Symbol Parameter Conditions 25 C 40 C to +125 C Unit Min Typ Max Max Max (85C) (125C) 74HC32 t propagation delay nA, nB to nY; see Figure6 [1] pd V = 2.0 V - 22 90 115 135 ns CC V = 4.5 V - 8 18 23 27 ns CC V = 5.0 V; C =15pF - 6 - - - ns CC L V = 6.0 V - 6 15 20 23 ns CC t transition time seeFigure6 [2] t V = 2.0 V - 19 75 95 110 ns CC V = 4.5 V - 7 15 19 22 ns CC V = 6.0 V - 6 13 16 19 ns CC C power dissipation per package; V =GNDtoV [3] - 16 - - - pF PD I CC capacitance 74HC_HCT32 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 5 — 4 September 2012 6 of 17

74HC32; 74HCT32 NXP Semiconductors Quad 2-input OR gate Table 7. Dynamic characteristics GND=0V; C =50pF; for load circuit see Figure7. L Symbol Parameter Conditions 25 C 40 C to +125 C Unit Min Typ Max Max Max (85C) (125C) 74HCT32 t propagation delay nA, nB to nY; see Figure6 [1] pd V = 4.5 V - 11 24 30 36 ns CC V = 5.0 V; C =15pF - 9 - - - ns CC L t transition time V = 4.5 V; seeFigure6 [2] - 7 15 19 22 ns t CC C power dissipation per package; [3] - 28 - - - pF PD capacitance V =GNDtoV 1.5V I CC [1] t is the same as t and t . pd PHL PLH [2] t is the same as t and t . t THL TLH [3] CPD is used to determine the dynamic power dissipation (PD in W): PD=CPDVCC2fiN+ (CLVCC2fo) where: f =input frequency in MHz; i f =output frequency in MHz; o C =output load capacitance in pF; L V =supply voltage in V; CC N=number of inputs switching; (CLVCC2fo)=sum of outputs. 11. Waveforms (cid:5)(cid:16) (cid:9)(cid:21)(cid:22)(cid:11)(cid:9)(cid:23)(cid:11)(cid:24)(cid:9)(cid:15)(cid:13)(cid:14) (cid:5)(cid:19) (cid:2)(cid:3)(cid:4) (cid:14)(cid:17)(cid:7)(cid:8) (cid:14)(cid:17)(cid:8)(cid:7) (cid:5)(cid:6)(cid:7) (cid:5)(cid:10) (cid:9)(cid:10)(cid:11)(cid:12)(cid:13)(cid:14)(cid:15)(cid:13)(cid:14) (cid:5)(cid:19) (cid:5)(cid:6)(cid:8) (cid:5)(cid:20) (cid:14)(cid:18)(cid:7)(cid:8) (cid:14)(cid:18)(cid:8)(cid:7) (cid:2)(cid:2)(cid:2)(cid:3)(cid:4)(cid:4)(cid:5)(cid:4)(cid:6)(cid:7) Measurement points are given in Table9. VOL and VOH are typical voltage output levels that occur with the output load. Fig 6. Input to output propagation delays Table 8. Measuremen t points Type Input Output V V V V M M X Y 74HC32 0.5V 0.5V 0.1V 0.9V CC CC CC CC 74HCT32 1.3V 1.3V 0.1V 0.9V CC CC 74HC_HCT32 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 5 — 4 September 2012 7 of 17

74HC32; 74HCT32 NXP Semiconductors Quad 2-input OR gate VI tW 90 % negative pulse VM VM 10 % GND tf tr tr tf VI 90 % positive pulse VM VM 10 % GND tW VCC VI VO G DUT RT CL 001aah768 Test data is given in Table9. Definitions test circuit: RT = termination resistance should be equal to output impedance Zo of the pulse generator. C = load capacitance including jig and probe capacitance. L Fig 7. Load circuitry for measuring switching times Table 9. Test data Type Input Load Test V t, t C I r f L 74HC32 V 6.0 ns 15pF, 50pF t , t CC PLH PHL 74HCT32 3.0V 6.0 ns 15pF, 50pF t , t PLH PHL 74HC_HCT32 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 5 — 4 September 2012 8 of 17

74HC32; 74HCT32 NXP Semiconductors Quad 2-input OR gate 12. Package outline DIP14: plastic dual in-line package; 14 leads (300 mil) SOT27-1 D ME e n a pl g n eati A2 A s L A1 c Z e w M b1 (e ) 1 b 14 8 MH pin 1 index E 1 7 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mAax. mAi n1 . mAa 2x . b b1 c D(1) E(1) e e1 L ME MH w mZax(1.) 1.73 0.53 0.36 19.50 6.48 3.60 8.25 10.0 mm 4.2 0.51 3.2 2.54 7.62 0.254 2.2 1.13 0.38 0.23 18.55 6.20 3.05 7.80 8.3 0.068 0.021 0.014 0.77 0.26 0.14 0.32 0.39 inches 0.17 0.02 0.13 0.1 0.3 0.01 0.087 0.044 0.015 0.009 0.73 0.24 0.12 0.31 0.33 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE REFERENCES EUROPEAN ISSUE DATE VERSION IEC JEDEC JEITA PROJECTION 99-12-27 SOT27-1 050G04 MO-001 SC-501-14 03-02-13 Fig 8. Package outline SOT27-1 (DIP14) 74HC_HCT32 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 5 — 4 September 2012 9 of 17

74HC32; 74HCT32 NXP Semiconductors Quad 2-input OR gate SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y HE v M A Z 14 8 Q A2 A1 (A 3 ) A pin 1 index θ Lp 1 7 L e w M detail X bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mAax. A1 A2 A3 bp c D(1) E(1) e HE L Lp Q v w y Z(1) θ 0.25 1.45 0.49 0.25 8.75 4.0 6.2 1.0 0.7 0.7 mm 1.75 0.25 1.27 1.05 0.25 0.25 0.1 0.10 1.25 0.36 0.19 8.55 3.8 5.8 0.4 0.6 0.3 8o 0.010 0.057 0.019 0.0100 0.35 0.16 0.244 0.039 0.028 0.028 0o inches 0.069 0.01 0.05 0.041 0.01 0.01 0.004 0.004 0.049 0.014 0.0075 0.34 0.15 0.228 0.016 0.024 0.012 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE REFERENCES EUROPEAN ISSUE DATE VERSION IEC JEDEC JEITA PROJECTION 99-12-27 SOT108-1 076E06 MS-012 03-02-19 Fig 9. Package outline SOT108-1 (SO14) 74HC_HCT32 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 5 — 4 September 2012 10 of 17

74HC32; 74HCT32 NXP Semiconductors Quad 2-input OR gate SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1 D E A X c y HE v M A Z 14 8 Q A2 A1 (A 3 ) A pin 1 index θ Lp L 1 7 detail X w M e bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT mAax. A1 A2 A3 bp c D(1) E(1) e HE L Lp Q v w y Z(1) θ mm 2 00..2015 11..8605 0.25 00..3285 00..2009 66..40 55..42 0.65 77..96 1.25 10..0633 00..97 0.2 0.13 0.1 10..49 80oo Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE REFERENCES EUROPEAN ISSUE DATE VERSION IEC JEDEC JEITA PROJECTION 99-12-27 SOT337-1 MO-150 03-02-19 Fig 10. Package outline SOT337-1 (SSOP14) 74HC_HCT32 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 5 — 4 September 2012 11 of 17

74HC32; 74HCT32 NXP Semiconductors Quad 2-input OR gate TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 D E A X c y HE v M A Z 14 8 Q A2 (A 3 ) A pin 1 index A1 θ Lp L 1 7 detail X w M e bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT mAax. A1 A2 A3 bp c D(1) E(2) e HE L Lp Q v w y Z(1) θ mm 1.1 00..1055 00..9850 0.25 00..3109 00..21 54..19 44..53 0.65 66..62 1 00..7550 00..43 0.2 0.13 0.1 00..7328 80oo Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE REFERENCES EUROPEAN ISSUE DATE VERSION IEC JEDEC JEITA PROJECTION 99-12-27 SOT402-1 MO-153 03-02-18 Fig 11. Package outline SOT402-1 (TSSOP14) 74HC_HCT32 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 5 — 4 September 2012 12 of 17

74HC32; 74HCT32 NXP Semiconductors Quad 2-input OR gate DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.5 x 3 x 0.85 mm SOT762-1 D B A A A1 E c terminal 1 detail X index area terminal 1 e1 C index area e b v M C A B y1 C y w M C 2 6 L 1 7 Eh e 14 8 13 9 Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) A(1) UNIT max. A1 b c D(1) Dh E(1) Eh e e1 L v w y y1 0.05 0.30 3.1 1.65 2.6 1.15 0.5 mm 1 0.2 0.5 2 0.1 0.05 0.05 0.1 0.00 0.18 2.9 1.35 2.4 0.85 0.3 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE REFERENCES EUROPEAN ISSUE DATE VERSION IEC JEDEC JEITA PROJECTION 02-10-17 SOT762-1 - - - MO-241 - - - 03-01-27 Fig 12. Package outline SOT762-1 (DHVQFN14) 74HC_HCT32 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 5 — 4 September 2012 13 of 17

74HC32; 74HCT32 NXP Semiconductors Quad 2-input OR gate 13. Abbreviations Table 10. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model LSTTL Low-power Schottky Transistor-Transistor Logic MM Machine Model TTL Transistor-Transistor Logic 14. Revision history T able 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74HC_HCT32 v.5 20120904 Product data sheet - 74HC_HCT32 v.4 Modifications: • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. 74HC_HCT32 v.4 20031212 Product specification - 74HC_HCT32 v.3 74HC_HCT32 v.3 20030829 Product specification - 74HC_HCT32_CNV v.2 74HC_HCT32_CNV v.2 19970827 Product specification - - 74HC_HCT32 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 5 — 4 September 2012 14 of 17

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In case an individual with the Terms and conditions of commercial sale of NXP Semiconductors. agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to Right to make changes — NXP Semiconductors reserves the right to make applying the customer’s general terms and conditions with regard to the changes to information published in this document, including without purchase of NXP Semiconductors products by customer. limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior No offer to sell or license — Nothing in this document may be interpreted or to the publication hereof. construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 74HC_HCT32 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 5 — 4 September 2012 15 of 17

74HC32; 74HCT32 NXP Semiconductors Quad 2-input OR gate Export control — This document as well as the item(s) described herein NXP Semiconductors’ specifications such use shall be solely at customer’s may be subject to export control regulations. Export might require a prior own risk, and (c) customer fully indemnifies NXP Semiconductors for any authorization from competent authorities. liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ Non-automotive qualified products — Unless this data sheet expressly standard warranty and NXP Semiconductors’ product specifications. states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested Translations — A non-English (translated) version of a document is for in accordance with automotive testing or application requirements. NXP reference only. The English version shall prevail in case of any discrepancy Semiconductors accepts no liability for inclusion and/or use of between the translated and English versions. non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in 15.4 Trademarks automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the Notice: All referenced brands, product names, service names and trademarks product for such automotive applications, use and specifications, and (b) are the property of their respective owners. whenever customer uses the product for automotive applications beyond 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com 74HC_HCT32 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 5 — 4 September 2012 16 of 17

74HC32; 74HCT32 NXP Semiconductors Quad 2-input OR gate 17. Contents 1 General description. . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Functional description . . . . . . . . . . . . . . . . . . . 3 7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 8 Recommended operating conditions. . . . . . . . 4 9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 10 Dynamic characteristics. . . . . . . . . . . . . . . . . . 6 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 12 Package outline. . . . . . . . . . . . . . . . . . . . . . . . . 9 13 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 14 14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 14 15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 15 15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15 15.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 15.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 15 15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 16 16 Contact information. . . . . . . . . . . . . . . . . . . . . 16 17 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2012. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 4 September 2012 Document identifier: 74HC_HCT32