INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: •The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications •The IC06 74HC/HCT/HCU/HCMOS Logic Package Information •The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT377 Octal D-type flip-flop with data enable; positive-edge trigger Product specification December 1990 File under Integrated Circuits, IC06

Philips Semiconductors Product specification Octal D-type flip-flop with data enable; 74HC/HCT377 positive-edge trigger FEATURES GENERAL DESCRIPTION • Ideal for addressable register applications The 74HC/HCT377 are high-speed Si-gate CMOS devices • Data enable for address and data synchronization and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC applications standard no. 7A. • Eight positive-edge triggered D-type flip-flops • See “273” for master reset version The 74HC/HCT377 have eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. A common • See “373” for transparent latch version clock (CP) input loads all flip-flops simultaneously when • See “374” for 3-state version the data enable (E) is LOW. The state of each D input, one • Output capability: standard set-up time before the LOW-to-HIGH clock transition, is transferred to the corresponding output (Q ) of the flip-flop. • I category: MSI n CC TheEinput must be stable only one set-up time prior to the LOW-to-HIGH transition for predictable operation. QUICK REFERENCE DATA GND=0V; T =25(cid:176) C; t =t =6 ns amb r f TYPICAL SYMBOL PARAMETER CONDITIONS UNIT HC HCT t / t propagation delay CP to Q C =15pF; V =5V 13 14 ns PHL PLH n L CC f maximum clock frequency 77 53 MHz max C input capacitance 3.5 3.5 pF I C power dissipation capacitance per flip-flop notes 1 and 2 20 20 pF PD Notes 1. C is used to determine the dynamic power dissipation (P inm W): PD D P =C · V 2· f +(cid:229) (C · V 2 · f ) where: D PD CC i L CC o f =input frequency in MHz i f =output frequency in MHz o (cid:229) (C · V 2 · f )=sum of outputs L CC o C =output load capacitance in pF L V =supply voltage in V CC 2. For HC the condition is V =GND to V I CC For HCT the condition is V =GND to V - 1.5V I CC ORDERING INFORMATION See“74HC/HCT/HCU/HCMOS Logic Package Information”. December1990 2

Philips Semiconductors Product specification Octal D-type flip-flop with data enable; 74HC/HCT377 positive-edge trigger PIN DESCRIPTION PIN NO. SYMBOL NAME AND FUNCTION 1 E data enable input (active LOW) 2, 5, 6, 9, 12, 15, 16, 19 Q to Q flip-flop outputs 0 7 3, 4, 7, 8, 13, 14, 17, 18 D to D data inputs 0 7 10 GND ground (0V) 11 CP clock input (LOW-to-HIGH, edge-triggered) 20 V positive supply voltage CC Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol. December1990 3

Philips Semiconductors Product specification Octal D-type flip-flop with data enable; 74HC/HCT377 positive-edge trigger FUNCTION TABLE INPUTS OUTPUTS OPERATING MODES CP E D Q n n load “1” › l h H load “0” › l l L hold (do nothing) › h X no change X H X no change Notes 1. H =HIGH voltage level h =HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition L =LOW voltage level I =LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition › =LOW-to-HIGH CP transition X =don’t care Fig.4 Functional diagram. Fig.5 Logic diagram. December1990 4

Philips Semiconductors Product specification Octal D-type flip-flop with data enable; 74HC/HCT377 positive-edge trigger DC CHARACTERISTICS FOR 74HC For the DC characteristics see“74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: standard I category: MSI CC AC CHARACTERISTICS FOR 74HC GND=0V; t =t =6ns; C =50pF r f L T ((cid:176) C) TEST CONDITIONS amb 74HC SYMBOL PARAMETER UNIT WAVEFORMS V +25 - 40to+85 - 40 to+125 CC (V) min. typ. max. min. max. min. max. t / t propagation delay 44 160 200 240 ns 2.0 Fig.6 PHL PLH CP to Q 16 32 40 48 4.5 n 13 27 34 41 6.0 t / t output transition time 19 75 95 110 ns 2.0 Fig.6 THL TLH 7 15 19 22 4.5 6 13 16 19 6.0 t clock pulse width 80 14 100 120 ns 2.0 Fig.6 W HIGH or LOW 16 5 20 24 4.5 14 4 17 20 6.0 t set-up time 60 14 75 90 ns 2.0 Fig.7 su D to CP 12 5 15 18 4.5 n 10 4 13 15 6.0 t set-up time 60 6 75 90 ns 2.0 Fig.7 su E to CP 12 2 15 18 4.5 10 2 13 15 6.0 t hold time 3 - 8 3 3 ns 2.0 Fig.7 h D to CP 3 - 3 3 3 4.5 n 3 - 2 3 3 6.0 t hold time 4 - 3 4 4 ns 2.0 Fig.7 h E to CP 4 - 1 4 4 4.5 4 - 1 4 4 6.0 f maximum clock pulse 6 23 5 4 MHz 2.0 Fig.6 max frequency 30 70 24 20 4.5 35 83 28 24 6.0 December1990 5

Philips Semiconductors Product specification Octal D-type flip-flop with data enable; 74HC/HCT377 positive-edge trigger DC CHARACTERISTICS FOR 74HCT For the DC characteristics see“74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: standard I category: MSI CC Note to HCT types The value of additional quiescent supply current (D I ) for a unit load of 1 is given in the family specifications. CC To determineD I per input, multiply this value by the unit load coefficient shown in the table below. CC INPUT UNIT LOAD COEFFICIENT E 1.50 CP 0.50 D 0.20 n AC CHARACTERISTICS FOR 74HCT GND=0V; t =t =6ns; C =50pF r f L T ((cid:176) C) TEST CONDITIONS amb 74HCT SYMBOL PARAMETER UNIT WAVEFORMS V +25 - 40to+85 - 40 to+125 CC (V) min. typ. max. min. max. min. max. t / t propagation delay 17 32 40 48 ns 4.5 Fig.6 PHL PLH CP to Q n t / t output transition time 7 15 19 22 ns 4.5 Fig.6 THL TLH t clock pulse width 20 8 25 30 ns 4.5 Fig.6 W HIGH or LOW t set-up time 12 4 15 18 ns 4.5 Fig.7 su D to CP n t set-up time 22 12 28 33 ns 4.5 Fig.7 su E to CP t hold time 2 - 4 2 2 ns 4.5 Fig.7 h D to CP n t hold time 3 - 2 3 3 ns 4.5 Fig.7 h E to CP f maximum clock pulse 27 48 22 18 MHz 4.5 Fig.6 max frequency December1990 6

Philips Semiconductors Product specification Octal D-type flip-flop with data enable; 74HC/HCT377 positive-edge trigger AC WAVEFORMS (1) HC : VM=50%; VI=GND to VCC. HCT: VM=1.3V; VI=GND to 3V. Fig.6 Waveforms showing the clock (CP) to output (Q ) propagation delays, the clock pulse width, output n transition times and the maximum clock pulse frequency. The shaded areas indicate when the input is permitted to change for predictable output performance. (1) HC : VM=50%; VI=GND to VCC. HCT: VM=1.3V; VI=GND to 3V. Fig.7 Waveforms showing the data set-up and hold times from the data input (D ) and from the data enable input n (E) to the clock (CP). PACKAGE OUTLINES See“74HC/HCT/HCU/HCMOS Logic Package Outlines”. December1990 7