74HC165; 74HCT165 8-bit parallel-in/serial out shift register Rev. 5 — 21 August 2017 Product data sheet 1 General description The 74HC165; 74HCT165 are 8-bit serial or parallel-in/serial-out shift registers. The device features a serial data input (DS), eight parallel data inputs (D0 to D7) and two complementary serial outputs (Q7 and Q7). When the parallel load input (PL) is LOW the data from D0 to D7 is loaded into the shift register asynchronously. When PL is HIGH data enters the register serially at DS. When the clock enable input (CE) is LOW data is shifted on the LOW-to-HIGH transitions of the CP input. A HIGH on CE will disable the CP input. Inputs are overvoltage tolerant to 15 V. This enables the device to be used in HIGH-to-LOW level shifting applications. 2 Features and benefits • Asynchronous 8-bit parallel load • Synchronous serial input • Complies with JEDEC standard no. 7A • Input levels: –For 74HC165: CMOS level –For 74HCT165: TTL level • ESD protection: –HBM JESD22-A114F exceeds 2000 V –MM JESD22-A115-A exceeds 200 V • Specified from -40 °C to +85 °C and from -40 °C to +125 °C 3 Applications • Parallel-to-serial data conversion

Nexperia 74HC165; 74HCT165 8-bit parallel-in/serial out shift register 4 Ordering information Table 1. Ordering information Type number Package Temperature Name Description Version range 74HC165D -40 °C to +125 °C SO16 plastic small outline package; 16 leads; SOT109-1 body width 3.9 mm 74HCT165D 74HC165DB -40 °C to +125 °C SSOP16 plastic shrink small outline package; 16 leads; SOT338-1 body width 5.3 mm 74HCT165DB 74HC165PW -40 °C to +125 °C TSSOP16 plastic thin shrink small outline package; 16 leads; SOT403-1 body width 4.4 mm 74HCT165PW 74HC165BQ -40 °C to +125 °C DHVQFN16 plastic dual in-line compatible thermal enhanced SOT763-1 very thin quad flat package; no leads; 16 terminals; 74HCT165BQ body 2.5 × 3.5 × 0.85 mm 5 Functional diagram SRG8 1 C2[LOAD] G1[SHIFT] 15 ≥1 10 2 1 C3/ DS 11 D0 10 12 3D D1 11 13 2D D2 12 14 2D D3 13 3 D4 4 14 D5 5 9 3 D6 Q7 6 7 4 D7 Q7 1 5 PL 9 CP CE 6 7 2 15 mna985 mna986 Figure 1. Logic symbol Figure 2. IEC logic symbol 74HC_HCT165 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved. Product data sheet Rev. 5 — 21 August 2017 2 / 22

Nexperia 74HC165; 74HCT165 8-bit parallel-in/serial out shift register 11 12 13 14 3 4 5 6 D0 D1 D2D3 D4 D5 D6 D7 1 PL 10 DS Q7 9 2 CP 8-BIT SHIFT REGISTER PARALLEL-IN/SERIAL-OUT Q7 7 15 CE mna992 Figure 3. Functional diagram 6 Pinning information 6.1 Pinning 74HC165 74HCT165 C terminal 1 L C P V index area 1 16 74HC165 CP 2 15 CE 74HCT165 D4 3 14 D3 D5 4 13 D2 PL 1 16 VCC D6 5 12 D1 CP 2 15 CE D7 6 GND(1) 11 D0 D4 3 14 D3 Q7 7 10 DS 8 9 D5 4 13 D2 D 7 D6 5 12 D1 GN Q 001aah565 Transparenttopview D7 6 11 D0 (1) This is not a supply pin. The substrate is attached Q7 7 10 DS to this pad using conductive die attach material. There is no electrical or mechanical requirement to solder this GND 8 9 Q7 pad.However, if it is soldered, the solder land should remain 001aah564 floating or be connected to GND. Figure 4. Pin configuration (SO16 and (T)SSOP16) Figure 5. Pin configuration (DHVQFN16) 74HC_HCT165 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved. Product data sheet Rev. 5 — 21 August 2017 3 / 22

Nexperia 74HC165; 74HCT165 8-bit parallel-in/serial out shift register 6.2 Pin description Table 2. Pin description Symbol Pin Description PL 1 asynchronous parallel load input (active LOW) CP 2 clock input (LOW-to-HIGH edge-triggered) Q7 7 complementary output from the last stage GND 8 ground (0 V) Q7 9 serial output from the last stage DS 10 serial data input D0 to D7 11, 12, 13, 14, 3, 4, 5, 6 parallel data inputs (also referred to as Dn) CE 15 clock enable input (active LOW) V 16 positive supply voltage CC 7 Functional description [1] Table 3. Function table Operating modes Inputs Qn registers Outputs PL CE CP DS D0 to D7 Q0 Q1 to Q6 Q7 Q7 parallel load L X X X L L L to L L H L X X X H H H to H H L serial shift H L ↑ l X L q0 to q5 q6 q6 H L ↑ h X H q0 to q5 q6 q6 H ↑ L l X L q0 to q5 q6 q6 H ↑ L h X H q0 to q5 q6 q6 hold "do nothing" H H X X X q0 q1 to q6 q7 q7 H X H X X q0 q1 to q6 q7 q7 [1] H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition; L = LOW voltage level; l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition; q = state of the referenced output one set-up time prior to the LOW-to-HIGH clock transition; X = don’t care; ↑ = LOW-to-HIGH clock transition. 74HC_HCT165 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved. Product data sheet Rev. 5 — 21 August 2017 4 / 22

Nexperia 74HC165; 74HCT165 8-bit parallel-in/serial out shift register CP CE DS PL D0 D1 D2 D3 D4 D5 D6 D7 Q7 Q7 inhibit serial shift mna993 load Figure 6. Timing diagram 8 Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V) Symbol Parameter Conditions Min Max Unit V supply voltage -0.5 +7 V CC [1] I input clamping current V < -0.5 V or V > V + 0.5 V - ±20 mA IK I I CC [1] I output clamping current V < -0.5 V or V > V + 0.5 V - ±20 mA OK O O CC I output current -0.5 V < V < V + 0.5 V - ±25 mA O O CC I supply current - 50 mA CC I ground current -50 - mA GND T storage temperature -65 +150 °C stg [2] P total power dissipation T = -40 °C to +125 °C - 500 mW tot amb [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] For SO16 Packages: Ptot derates linearly with 8 mW/K above 70 °C. For (T)SSOP16 Packages: Ptot derates linearly with 5.5 mW/K above 60 °C. For DHVQFN16 Packages: Ptot derates linearly with 4.5 mW/K above 60 °C. 74HC_HCT165 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved. Product data sheet Rev. 5 — 21 August 2017 5 / 22

Nexperia 74HC165; 74HCT165 8-bit parallel-in/serial out shift register 9 Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V) Symbol Parameter Conditions 74HC165 74HCT165 Unit Min Typ Max Min Typ Max V supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V CC V input voltage 0 - V 0 - V V I CC CC V output voltage 0 - V 0 - V V O CC CC T ambient temperature -40 - +125 -40 - +125 °C amb Δt/ΔV input transition rise and fall rate V = 2.0 V - - 625 - - - ns/V CC V = 4.5 V - 1.67 139 - 1.67 139 ns/V CC V = 6.0 V - - 83 - - - ns/V CC 10 Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 25 °C -40 °C to -40 °C to Unit +85 °C +125 °C Min Typ Max Min Max Min Max 74HC165 V HIGH-level input V = 2.0 V 1.5 1.2 - 1.5 - 1.5 - V IH CC voltage V = 4.5 V 3.15 2.4 - 3.15 - 3.15 - V CC V = 6.0 V 4.2 3.2 - 4.2 - 4.2 - V CC V LOW-level input V = 2.0 V - 0.8 0.5 - 0.5 - 0.5 V IL CC voltage V = 4.5 V - 2.1 1.35 - 1.35 - 1.35 V CC V = 6.0 V - 2.8 1.8 - 1.8 - 1.8 V CC V HIGH-level V = V or V OH I IH IL output voltage I = -20 μA; V = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V O CC I = -20 μA; V = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V O CC I = -20 μA; V = 6.0 V 5.9 6.0 - 5.9 - 5.9 - V O CC I = -4.0 mA; V = 4.5 V 3.98 4.32 - 3.84 - 3.7 - V O CC I = -5.2 mA; V = 6.0 V 5.48 5.81 - 5.34 - 5.2 - V O CC 74HC_HCT165 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved. Product data sheet Rev. 5 — 21 August 2017 6 / 22

Nexperia 74HC165; 74HCT165 8-bit parallel-in/serial out shift register Symbol Parameter Conditions 25 °C -40 °C to -40 °C to Unit +85 °C +125 °C Min Typ Max Min Max Min Max V LOW-level V = V or V OL I IH IL output voltage I = 20 μA; V = 2.0 V - 0 0.1 - 0.1 - 0.1 V O CC I = 20 μA; V = 4.5 V - 0 0.1 - 0.1 - 0.1 V O CC I = 20 μA; V = 6.0 V - 0 0.1 - 0.1 - 0.1 V O CC I = 4.0 mA; V = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V O CC I = 5.2 mA; V = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V O CC I input leakage V = V or GND; V = 6.0 V - - ±0.1 - ±1 - ±1 μA I I CC CC current I supply current V = V or GND; I = 0 A; - - 8.0 - 80 - 160 μA CC I CC O V = 6.0 V CC C input - 3.5 - - - - - pF I capacitance 74HCT165 V HIGH-level input V = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - 2.0 - V IH CC voltage V LOW-level input V = 4.5 V to 5.5 V - 1.2 0.8 - 0.8 - 0.8 V IL CC voltage V HIGH-level V = V or V ; V = 4.5 V OH I IH IL CC output voltage I = -20 μA 4.4 4.5 - 4.4 - 4.4 - V O I = -4.0 mA 3.98 4.32 - 3.84 - 3.7 - V O V LOW-level V = V or V OL I IH IL output voltage I = 20 μA; V = 4.5 V - 0 0.1 - 0.1 - 0.1 V O CC I = 5.2 mA; V = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V O CC I input leakage V = V or GND; V = 6.0 V - - ±0.1 - ±1 - ±1 μA I I CC CC current I supply current V = V or GND; I = 0 A; - - 8.0 - 80 - 160 μA CC I CC O V = 6.0 V CC ΔI additional supply per input pin; V = V - 2.1 V; CC I CC current other inputs at V or GND; CC V = 4.5 V to 5.5 V CC Dn and DS inputs - 35 126 - 157.5 - 171.5 μA CP CE, and PL inputs - 65 234 - 292.5 - 318.5 μA C input - 3.5 - - - - - pF I capacitance 74HC_HCT165 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved. Product data sheet Rev. 5 — 21 August 2017 7 / 22

Nexperia 74HC165; 74HCT165 8-bit parallel-in/serial out shift register 11 Dynamic characteristics Table 7. Dynamic characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V); C = 50 pF unless otherwise specified; for test circuit, see Figure 12 L Symbol Parameter Conditions 25 °C -40 °C to -40 °C to Unit +85 °C +125 °C Min Typ Max Min Max Min Max 74HC165 [1] t propagation CP or CE to Q7, Q7; pd delay see Figure 7 V = 2.0 V - 52 165 - 205 - 250 ns CC V = 4.5 V - 19 33 - 41 - 50 ns CC V = 6.0 V - 15 28 - 35 - 43 ns CC V = 5.0 V; C = 15 pF - 16 - - - - - ns CC L PL to Q7, Q7; see Figure 8 V = 2.0 V - 50 165 - 205 - 250 ns CC V = 4.5 V - 18 33 - 41 - 50 ns CC V = 6.0 V - 14 28 - 35 - 43 ns CC V = 5.0 V; C = 15 pF - 15 - - - - - ns CC L D7 to Q7, Q7; see Figure 9 V = 2.0 V - 36 120 - 150 - 180 ns CC V = 4.5 V - 13 24 - 30 - 36 ns CC V = 6.0 V - 10 20 - 26 - 31 ns CC V = 5.0 V; C = 15 pF - 11 - - - - - ns CC L [2] t transition time Q7, Q7 output; see Figure 7 t V = 2.0 V - 19 75 - 95 - 110 ns CC V = 4.5 V - 7 15 - 19 - 22 ns CC V = 6.0 V - 6 13 - 16 - 19 ns CC t pulse width CP input HIGH or LOW; W see Figure 7 V = 2.0 V 80 17 - 100 - 120 - ns CC V = 4.5 V 16 6 - 20 - 24 - ns CC V = 6.0 V 14 5 - 17 - 20 - ns CC PL input LOW; see Figure 8 V = 2.0 V 80 14 - 100 - 120 - ns CC V = 4.5 V 16 5 - 20 - 24 - ns CC V = 6.0 V 14 4 - 17 - 20 - ns CC 74HC_HCT165 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved. Product data sheet Rev. 5 — 21 August 2017 8 / 22

Nexperia 74HC165; 74HCT165 8-bit parallel-in/serial out shift register Symbol Parameter Conditions 25 °C -40 °C to -40 °C to Unit +85 °C +125 °C Min Typ Max Min Max Min Max t recovery time PL to CP, CE; see Figure 8 rec V = 2.0 V 100 22 - 125 - 150 - ns CC V = 4.5 V 20 8 - 25 - 30 - ns CC V = 6.0 V 17 6 - 21 - 26 - ns CC t set-up time DS to CP, CE; see Figure 10 su V = 2.0 V 80 11 - 100 - 120 - ns CC V = 4.5 V 16 4 - 20 - 24 - ns CC V = 6.0 V 14 3 - 17 - 20 - ns CC CE to CP and CP to CE; see Figure 10 V = 2.0 V 80 17 - 100 - 120 - ns CC V = 4.5 V 16 6 - 20 - 24 - ns CC V = 6.0 V 14 5 - 17 - 20 - ns CC Dn to PL; see Figure 11 V = 2.0 V 80 22 - 100 - 120 - ns CC V = 4.5 V 16 8 - 20 - 24 - ns CC V = 6.0 V 14 6 - 17 - 20 - ns CC t hold time DS to CP, CE and Dn to PL; h see Figure 10 V = 2.0 V 5 2 - 5 - 5 - ns CC V = 4.5 V 5 2 - 5 - 5 - ns CC V = 6.0 V 5 2 - 5 - 5 - ns CC CE to CP and CP to CE; see Figure 10 V = 2.0 V 5 -17 - 5 - 5 - ns CC V = 4.5 V 5 -6 - 5 - 5 - ns CC V = 6.0 V 5 -5 - 5 - 5 - ns CC f maximum CP input; see Figure 7 max frequency V = 2.0 V 6 17 - 5 - 4 - MHz CC V = 4.5 V 30 51 - 24 - 20 - MHz CC V = 6.0 V 35 61 - 28 - 24 - MHz CC V = 5.0 V; C = 15 pF - 56 - - - - - MHz CC L [3] C power per package; V = GND to V - 35 - - - - - pF PD I CC dissipation capacitance 74HC_HCT165 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved. Product data sheet Rev. 5 — 21 August 2017 9 / 22

Nexperia 74HC165; 74HCT165 8-bit parallel-in/serial out shift register Symbol Parameter Conditions 25 °C -40 °C to -40 °C to Unit +85 °C +125 °C Min Typ Max Min Max Min Max 74HCT165 [1] t propagation CE, CP to Q7, Q7; pd delay see Figure 7 V = 4.5 V - 17 34 - 43 - 51 ns CC V = 5.0 V; C = 15 pF - 14 - - - - - ns CC L PL to Q7, Q7; see Figure 8 V = 4.5 V - 20 40 - 50 - 60 ns CC V = 5.0 V; C = 15 pF - 17 - - - - - ns CC L D7 to Q7, Q7; see Figure 9 V = 4.5 V - 14 28 - 35 - 42 ns CC V = 5.0 V; C = 15 pF - 11 - - - - - ns CC L [2] t transition time Q7, Q7 output; see Figure 7 t V = 4.5 V - 7 15 - 19 - 22 ns CC t pulse width CP input; see Figure 7 W V = 4.5 V 16 6 - 20 - 24 - ns CC PL input; see Figure 8 V = 4.5 V 20 9 - 25 - 30 - ns CC t recovery time PL to CP, CE; see Figure 8 rec V = 4.5 V 20 8 - 25 - 30 - ns CC t set-up time DS to CP, CE; see Figure 10 su V = 4.5 V 20 2 - 25 - 30 - ns CC CE to CP and CP to CE; see Figure 10 V = 4.5 V 20 7 - 25 - 30 - ns CC Dn to PL; see Figure 11 V = 4.5 V 20 10 - 25 - 30 - ns CC t hold time DS to CP, CE and Dn to PL; h see Figure 10 V = 4.5 V 7 -1 - 9 - 11 - ns CC CE to CP and CP to CE; see Figure 10 V = 4.5 V 0 -7 - 0 - 0 - ns CC 74HC_HCT165 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved. Product data sheet Rev. 5 — 21 August 2017 10 / 22

Nexperia 74HC165; 74HCT165 8-bit parallel-in/serial out shift register Symbol Parameter Conditions 25 °C -40 °C to -40 °C to Unit +85 °C +125 °C Min Typ Max Min Max Min Max f maximum CP input; see Figure 7 max frequency V = 4.5 V 26 44 - 21 - 17 - MHz CC V = 5.0 V; C = 15 pF - 48 - - - - - MHz CC L [3] C power per package; - 35 - - - - - pF PD dissipation V = GND to V - 1.5 V I CC capacitance [1] tpd is the same as tPHL and tPLH. [2] tt is the same as tTHL and tTLH. [3] CPD is used to determine the dynamic power dissipation (PD in μW). PD = CPD × VCC2 × fi + Σ (CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; Σ (CL × VCC2 × fo) = sum of outputs; CL = output load capacitance in pF; VCC = supply voltage in V. 11.1 Waveforms and test circuit 1/fmax VI CPorCEinput VM GND tW tPHL tPLH VOH 90 % 90 % Q7 or Q7 output VM 10 % 10 % VOL tTHL tTLH mna987 Measurement points are given in Table 8. V and V are typical voltage output levels that occur with the output load. OL OH Figure 7. The clock (CP) or clock enable (CE) to output (Q7 or Q7) propagation delays, the clock pulse width, the maximum clock frequency and the output transition times 74HC_HCT165 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved. Product data sheet Rev. 5 — 21 August 2017 11 / 22

Nexperia 74HC165; 74HCT165 8-bit parallel-in/serial out shift register VI PLinput VM GND tW trec VI CE, CPinput VM GND tPHL VOH Q7 or Q7output VM VOL mna988 Measurement points are given in Table 8. V and V are typical voltage output levels that occur with the output load. OL OH Figure 8. The parallel load (PL) pulse width, the parallel load to output (Q7 or Q7) propagation delays, the parallel load to clock (CP) and clock enable (CE) recovery time VI D7 input VM GND tPLH tPHL VOH Q7 output VM VOL tPHL tPLH VOH Q7 output VM VOL mna989 Measurement points are given in Table 8. V and V are typical voltage output levels that occur with the output load. OL OH Figure 9. The data input (D7) to output (Q7 or Q7) propagation delays when PL is LOW 74HC_HCT165 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved. Product data sheet Rev. 5 — 21 August 2017 12 / 22

Nexperia 74HC165; 74HCT165 8-bit parallel-in/serial out shift register VI (1) CP,CEinput VM GND th th tsu tsu VI DSinput VM GND tsu VI tW CP,CEinput VM GND mna990 (1) CE may change only from HIGH-to-LOW while CP is LOW. The shaded areas indicate when the input is permitted to change for predictable output performance Measurement points are given in Table 8. V and V are typical voltage output levels that occur with the output load. OL OH Figure 10. The set-up and hold times from the serial data input (DS) to the clock (CP) and clock enable (CE) inputs, from the clock enable input (CE) to the clock input (CP) and from the clock input (CP) to the clock enable input (CE) VI Dninput VM VM GND tsu th tsu th VI PLinput VM VM GND mna991 Measurement points are given in Table 8. V and V are typical voltage output levels that occur with the output load. OL OH Figure 11. The set-up and hold times from the data inputs (Dn) to the parallel load input (PL) Table 8. Measurement points Type Input Output V V V I M M 74HC165 V 0.5V 0.5V CC CC CC 74HCT165 3 V 1.3 V 1.3 V 74HC_HCT165 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved. Product data sheet Rev. 5 — 21 August 2017 13 / 22

Nexperia 74HC165; 74HCT165 8-bit parallel-in/serial out shift register tW VI 90% negative pulse VM VM 10% 0V tf tr tr tf VI 90% positive pulse VM VM 10% 0V tW VCC VCC VI VO RL S1 G DUT open RT CL 001aad983 Test data is given in Table 9. Definitions for test circuit: R = Termination resistance should be equal to output impedance Z of the pulse generator. T o C = Load capacitance including jig and probe capacitance. L R = Load resistance. L S1 = Test selection switch Figure 12. Test circuit for measuring switching times Table 9. Test data Type Input Load S1 position V t, t C R t , t I r f L L PHL PLH 74HC165 V 6 ns 15 pF, 50 pF 1 kΩ open CC 74HCT165 3 V 6 ns 15 pF, 50 pF 1 kΩ open 74HC_HCT165 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved. Product data sheet Rev. 5 — 21 August 2017 14 / 22

Nexperia 74HC165; 74HCT165 8-bit parallel-in/serial out shift register 12 Package outline SO16:plasticsmalloutlinepackage;16leads;bodywidth3.9mm SOT109-1 D E A X c y HE v M A Z 16 9 Q A2 A1 (A3) A pin1index θ Lp 1 8 L e w M detailX bp 0 2.5 5mm scale DIMENSIONS(inchdimensionsarederivedfromtheoriginalmmdimensions) UNIT mAax. A1 A2 A3 bp c D(1) E(1) e HE L Lp Q v w y Z(1) θ 0.25 1.45 0.49 0.25 10.0 4.0 6.2 1.0 0.7 0.7 mm 1.75 0.25 1.27 1.05 0.25 0.25 0.1 0.10 1.25 0.36 0.19 9.8 3.8 5.8 0.4 0.6 0.3 8o 0.010 0.057 0.019 0.0100 0.39 0.16 0.244 0.039 0.028 0.028 0o inches 0.069 0.01 0.05 0.041 0.01 0.01 0.004 0.004 0.049 0.014 0.0075 0.38 0.15 0.228 0.016 0.020 0.012 Note 1.Plasticormetalprotrusionsof0.15mm(0.006inch)maximumpersidearenotincluded. OUTLINE REFERENCES EUROPEAN ISSUEDATE VERSION IEC JEDEC JEITA PROJECTION 99-12-27 SOT109-1 076E07 MS-012 03-02-19 Figure 13. Package outline SOT109-1 (SO16) 74HC_HCT165 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved. Product data sheet Rev. 5 — 21 August 2017 15 / 22

Nexperia 74HC165; 74HCT165 8-bit parallel-in/serial out shift register SSOP16:plasticshrinksmalloutlinepackage;16leads;bodywidth5.3mm SOT338-1 D E A X c y HE v M A Z 16 9 Q A2 A1 (A3) A pin1index θ Lp L 1 8 detailX w M e bp 0 2.5 5mm scale DIMENSIONS(mmaretheoriginaldimensions) UNIT mAax. A1 A2 A3 bp c D(1) E(1) e HE L Lp Q v w y Z(1) θ 0.21 1.80 0.38 0.20 6.4 5.4 7.9 1.03 0.9 1.00 8o mm 2 0.05 1.65 0.25 0.25 0.09 6.0 5.2 0.65 7.6 1.25 0.63 0.7 0.2 0.13 0.1 0.55 0o Note 1.Plasticormetalprotrusionsof0.25mmmaximumpersidearenotincluded. OUTLINE REFERENCES EUROPEAN ISSUEDATE VERSION IEC JEDEC JEITA PROJECTION 99-12-27 SOT338-1 MO-150 03-02-19 Figure 14. Package outline SOT338-1 (SSOP16) 74HC_HCT165 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved. Product data sheet Rev. 5 — 21 August 2017 16 / 22

Nexperia 74HC165; 74HCT165 8-bit parallel-in/serial out shift register TSSOP16:plasticthinshrinksmalloutlinepackage;16leads;bodywidth4.4mm SOT403-1 D E A X c y HE v M A Z 16 9 Q A2 (A3) A pin1index A1 θ Lp L 1 8 detailX w M e bp 0 2.5 5mm scale DIMENSIONS(mmaretheoriginaldimensions) UNIT mAax. A1 A2 A3 bp c D(1) E(2) e HE L Lp Q v w y Z(1) θ 0.15 0.95 0.30 0.2 5.1 4.5 6.6 0.75 0.4 0.40 8o mm 1.1 0.05 0.80 0.25 0.19 0.1 4.9 4.3 0.65 6.2 1 0.50 0.3 0.2 0.13 0.1 0.06 0o Notes 1.Plasticormetalprotrusionsof0.15mmmaximumpersidearenotincluded. 2.Plasticinterleadprotrusionsof0.25mmmaximumpersidearenotincluded. OUTLINE REFERENCES EUROPEAN ISSUEDATE VERSION IEC JEDEC JEITA PROJECTION 99-12-27 SOT403-1 MO-153 03-02-18 Figure 15. Package outline SOT403-1 (TSSOP16) 74HC_HCT165 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved. Product data sheet Rev. 5 — 21 August 2017 17 / 22

Nexperia 74HC165; 74HCT165 8-bit parallel-in/serial out shift register DHVQFN16:plasticdualin-linecompatiblethermalenhancedverythinquadflatpackage;noleads; 16terminals;body2.5x3.5x0.85mm SOT763-1 D B A A A1 E c terminal1 detailX indexarea terminal1 e1 C indexarea e b v M C A B y1 C y w M C 2 7 L 1 8 Eh e 16 9 15 10 Dh X 0 2.5 5mm scale DIMENSIONS(mmaretheoriginaldimensions) A(1) UNIT max. A1 b c D(1) Dh E(1) Eh e e1 L v w y y1 0.05 0.30 3.6 2.15 2.6 1.15 0.5 mm 1 0.2 0.5 2.5 0.1 0.05 0.05 0.1 0.00 0.18 3.4 1.85 2.4 0.85 0.3 Note 1.Plasticormetalprotrusionsof0.075mmmaximumpersidearenotincluded. OUTLINE REFERENCES EUROPEAN ISSUEDATE VERSION IEC JEDEC JEITA PROJECTION 02-10-17 SOT763-1 --- MO-241 --- 03-01-27 Figure 16. Package outline SOT763-1 (DHVQFN16) 74HC_HCT165 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved. Product data sheet Rev. 5 — 21 August 2017 18 / 22

Nexperia 74HC165; 74HCT165 8-bit parallel-in/serial out shift register 13 Abbreviations Table 10. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 14 Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74HC_HCT165 v.5 20170821 Product data sheet - 74HC_HCT165 v.4 Modifications: • Hold time for 74HC165 has been updated. See Paragraph hold time. • The format of this data sheet has been redesigned to comply with the identity guidelines of Nexperia. • Legal texts have been adapted to the new company name where appropriate. 74HC_HCT165 v.4 20151228 Product data sheet - 74HC_HCT165 v.3 Modifications: • Type numbers 74HC165N and 74HCT165N (SOT38-4) removed. 74HC_HCT165 v.3 20080314 Product data sheet - 74HC_HCT165_CNV v.2 Modifications: • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Package SOT763-1 (DHVQFN16) added to Section 4 and Section 12. • Family data added, see Section 10 74HC_HCT165_CNV v.2 December 1990 Product specification - - 74HC_HCT165 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved. Product data sheet Rev. 5 — 21 August 2017 19 / 22

Nexperia 74HC165; 74HCT165 8-bit parallel-in/serial out shift register 15 Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term 'short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nexperia.com. systems or equipment, nor in applications where failure or malfunction of an Nexperia product can reasonably be expected to result in personal 15.2 Definitions injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in Draft — The document is a draft version only. The content is still under such equipment or applications and therefore such inclusion and/or use is at internal review and subject to formal approval, which may result in the customer’s own risk. modifications or additions. Nexperia does not give any representations or warranties as to the accuracy or completeness of information included herein Applications — Applications that are described herein for any of these and shall have no liability for the consequences of use of such information. products are for illustrative purposes only. Nexperia makes no representation or warranty that such applications will be suitable for the specified use Short data sheet — A short data sheet is an extract from a full data sheet without further testing or modification. Customers are responsible for the with the same product type number(s) and title. A short data sheet is design and operation of their applications and products using Nexperia intended for quick reference only and should not be relied upon to contain products, and Nexperia accepts no liability for any assistance with detailed and full information. For detailed and full information see the applications or customer product design. It is customer’s sole responsibility relevant full data sheet, which is available on request via the local Nexperia to determine whether the Nexperia product is suitable and fit for the sales office. In case of any inconsistency or conflict with the short data sheet, customer’s applications and products planned, as well as for the planned the full data sheet shall prevail. application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks Product specification — The information and data provided in a Product associated with their applications and products. Nexperia does not accept data sheet shall define the specification of the product as agreed between any liability related to any default, damage, costs or problem which is based Nexperia and its customer, unless Nexperia and customer have explicitly on any weakness or default in the customer’s applications or products, or agreed otherwise in writing. In no event however, shall an agreement be the application or use by customer’s third party customer(s). Customer is valid in which the Nexperia product is deemed to offer functions and qualities responsible for doing all necessary testing for the customer’s applications beyond those described in the Product data sheet. and products using Nexperia products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). Nexperia does not accept any liability in this respect. 15.3 Disclaimers Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent Limited warranty and liability — Information in this document is believed damage to the device. Limiting values are stress ratings only and (proper) to be accurate and reliable. However, Nexperia does not give any operation of the device at these or any other conditions above those representations or warranties, expressed or implied, as to the accuracy given in the Recommended operating conditions section (if present) or the or completeness of such information and shall have no liability for the Characteristics sections of this document is not warranted. Constant or consequences of use of such information. Nexperia takes no responsibility repeated exposure to limiting values will permanently and irreversibly affect for the content in this document if provided by an information source outside the quality and reliability of the device. of Nexperia. In no event shall Nexperia be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal Terms and conditions of commercial sale — Nexperia products are or replacement of any products or rework charges) whether or not such sold subject to the general terms and conditions of commercial sale, as damages are based on tort (including negligence), warranty, breach of published at http://www.nexperia.com/profile/terms, unless otherwise agreed contract or any other legal theory. Notwithstanding any damages that in a valid written individual agreement. In case an individual agreement is customer might incur for any reason whatsoever, Nexperia's aggregate and concluded only the terms and conditions of the respective agreement shall cumulative liability towards customer for the products described herein shall apply. Nexperia hereby expressly objects to applying the customer’s general be limited in accordance with the Terms and conditions of commercial sale of terms and conditions with regard to the purchase of Nexperia products by Nexperia. customer. Right to make changes — Nexperia reserves the right to make changes No offer to sell or license — Nothing in this document may be interpreted to information published in this document, including without limitation or construed as an offer to sell products that is open for acceptance or specifications and product descriptions, at any time and without notice. This the grant, conveyance or implication of any license under any copyrights, document supersedes and replaces all information supplied prior to the patents or other industrial or intellectual property rights. publication hereof. Export control — This document as well as the item(s) described herein Suitability for use — Nexperia products are not designed, authorized or may be subject to export control regulations. Export might require a prior warranted to be suitable for use in life support, life-critical or safety-critical authorization from competent authorities. 74HC_HCT165 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved. Product data sheet Rev. 5 — 21 August 2017 20 / 22

Nexperia 74HC165; 74HCT165 8-bit parallel-in/serial out shift register Non-automotive qualified products — Unless this data sheet expressly design and use of the product for automotive applications beyond Nexperia's states that this specific Nexperia product is automotive qualified, the standard warranty and Nexperia's product specifications. product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. Nexperia Translations — A non-English (translated) version of a document is for accepts no liability for inclusion and/or use of non-automotive qualified reference only. The English version shall prevail in case of any discrepancy products in automotive equipment or applications. In the event that customer between the translated and English versions. uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without Nexperia's warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for 15.4 Trademarks automotive applications beyond Nexperia's specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies Nexperia Notice: All referenced brands, product names, service names and for any liability, damages or failed product claims resulting from customer trademarks are the property of their respective owners. 74HC_HCT165 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved. Product data sheet Rev. 5 — 21 August 2017 21 / 22

Nexperia 74HC165; 74HCT165 8-bit parallel-in/serial out shift register Contents 1 General description ............................................1 2 Features and benefits .........................................1 3 Applications .........................................................1 4 Ordering information ..........................................2 5 Functional diagram .............................................2 6 Pinning information ............................................3 6.1 Pinning ...............................................................3 6.2 Pin description ...................................................4 7 Functional description ........................................4 8 Limiting values ....................................................5 9 Recommended operating conditions ................6 10 Static characteristics ..........................................6 11 Dynamic characteristics .....................................8 11.1 Waveforms and test circuit ..............................11 12 Package outline .................................................15 13 Abbreviations ....................................................19 14 Revision history ................................................19 15 Legal information ..............................................20 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section 'Legal information'. © Nexperia B.V. 2017. All rights reserved. For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 21 August 2017 Document identifier: 74HC_HCT165