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INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: •The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications •The IC06 74HC/HCT/HCU/HCMOS Logic Package Information •The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT160 Presettable synchronous BCD decade counter; asynchronous reset Product specification December 1990 File under Integrated Circuits, IC06

Philips Semiconductors Product specification Presettable synchronous BCD decade 74HC/HCT160 counter; asynchronous reset FEATURES input (PE) disables the counting action and causes the data at the data inputs (D to D ) to be loaded into the • Synchronous counting and loading 0 3 counter on the positive-going edge of the clock (providing • Two count enable inputs for n-bit cascading that the set-up and hold time requirements forPE are met). • Positive-edge triggered clock Preset takes place regardless of the levels at count enable inputs (CEP and CET). • Asynchronous reset • Output capability: standard A LOW level at the master reset input (MR) sets all four outputs of the flip-flops (Q to Q ) to LOW level regardless • I category: MSI 0 3 CC of the levels at CP,PE, CET and CEP inputs (thus providing an asynchronous clear function). GENERAL DESCRIPTION The look-ahead carry simplifies serial cascading of the The 74HC/HCT160 are high-speed Si-gate CMOS devices counters. Both count enable inputs (CEP and CET) must and are pin compatible with low power Schottky TTL be HIGH to count. The CET input is fed forward to enable (LSTTL). They are specified in compliance with JEDEC the terminal count output (TC). The TC output thus standard no. 7A. enabled will produce a HIGH output pulse of a duration approximately equal to a HIGH level output of Q . This 0 The 74HC/HCT160 are synchronous presettable decade pulse can be used to enable the next cascaded stage. counters which feature an internal look-ahead carry and can be used for high-speed counting. The maximum clock frequency for the cascaded counters Synchronous operation is provided by having all flip-flops is determined by the CP to TC propagation delay and CEP clocked simultaneously on the positive-going edge of the to CP set-up time, according to the following formula: clock (CP). 1 The outputs (Q0 to Q3) of the counters may be preset to a fmax= t------------------------(--C-----P------t--o-----T----C----)-----+------t----------(--C-----E----P-----t--o-----C----P-----) HIGH or LOW level. A LOW level at the parallel enable P(max) SU QUICK REFERENCE DATA GND=0 V; T =25(cid:176) C; t =t =6 ns amb r f Notes TYPICAL SYMBOL PARAMETER CONDITIONS UNIT 1. C is used to determine the PD HC HCT dynamic power dissipation t propagation delay C =15pF; (P inm W): PHL L D CP to Q V =5V 19 21 ns n CC CP to TC 21 24 ns P =C · V 2· f + D PD CC i MR to Q 21 23 ns (cid:229) (C · V 2 · f ) n L CC o MR to TC 21 26 ns where: CET to TC 14 14 ns f =input frequency in MHz t propagation delay i PLH f =output frequency in MHz CP to Q 19 21 ns o n (cid:229) (C · V 2· f )=sum of CP to TC 21 20 ns L CC o outputs CET to TC 14 7 ns C =output load capacitance in f maximum clock 61 31 MHz L max pF frequency V =supply voltage in V CC C input capacitance 3.5 3.5 pF I 2. For HC the condition is C power dissipation notes 1 and 2 PD V =GND to V I CC capacitance per 39 34 pF For HCT the condition is package V =GND to V - 1.5 V I CC December1990 2

Philips Semiconductors Product specification Presettable synchronous BCD decade 74HC/HCT160 counter; asynchronous reset ORDERING INFORMATION See“74HC/HCT/HCU/HCMOS Logic Package Information”. PIN DESCRIPTION PIN NO. SYMBOL NAME AND FUNCTION 1 MR asynchronous master reset (active LOW) 2 CP clock input (LOW-to-HIGH, edge-triggered) 3, 4, 5, 6 D to D data inputs 0 3 7 CEP count enable input 8 GND ground (0 V) 9 PE parallel enable input (active LOW) 10 CET count enable carry input 14, 13, 12, 11 Q to Q flip-flop outputs 0 3 15 TC terminal count output 16 V positive supply voltage CC Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol. December1990 3

Philips Semiconductors Product specification Presettable synchronous BCD decade 74HC/HCT160 counter; asynchronous reset Fig.4 Functional diagram. FUNCTION TABLE INPUTS OUTPUTS OPERATING MODE MR CP CEP CET PE D Q TC n n reset (clear) L X X X X X L L parallel load H › X X I I L L H › X X I h H (1) count H › h h h X count (1) hold H X I X h X q (1) n (do nothing) H X X I h X q L n Notes 1. The TC output is HIGH when CET is HIGH and the counter is at terminal count (HLLH). H=HIGH voltage level h=HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition L=LOW voltage level I=LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition q=lower case letters indicate the state of the referenced output one set-up time prior to the LOW-to-HIGH CP transition X=don’t care › =LOW-to-HIGH CP transition December1990 4

Philips Semiconductors Product specification Presettable synchronous BCD decade 74HC/HCT160 counter; asynchronous reset Fig.6 Typical timing sequence: reset outputs to zero; preset to BCD seven; count to eight, nine, zero, Fig.5 State diagram. one, two and three; inhibit. Fig.7 Logic diagram. December1990 5

Philips Semiconductors Product specification Presettable synchronous BCD decade 74HC/HCT160 counter; asynchronous reset DC CHARACTERISTICS FOR 74HC For the DC characteristics see“74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: standard I category: MSI CC AC CHARACTERISTICS FOR 74HC GND=0 V; t =t =6 ns; C =50 pF r f L T ((cid:176) C) TEST CONDITIONS amb 74HC SYMBOL PARAMETER UNIT WAVEFORMS V +25 - 40to+85 - 40to+125 CC (V) min. typ. max. min. max. min. max. t / t propagation delay 61 185 230 280 ns 2.0 Fig. 8 PHL PLH CP to Q 22 37 46 56 4.5 n 18 31 39 48 6.0 t / t propagation delay 69 215 270 325 ns 2.0 Fig. 8 PHL PLH CP to TC 25 43 54 65 4.5 20 31 46 55 6.0 t propagation delay 69 210 265 315 ns 2.0 Fig. 9 PHL MR to Q 25 42 53 63 4.5 n 20 36 45 54 6.0 t propagation delay 69 220 275 330 ns 2.0 Fig. 9 PHL MR to TC 25 44 55 66 4.5 20 37 47 56 6.0 t / t propagation delay 47 150 190 225 ns 2.0 Fig. 10 PHL PLH CET to TC 17 30 38 45 4.5 14 26 33 38 6.0 t / t output transition time 19 75 95 110 ns 2.0 Figs 8 and 10 THL TLH 7 15 19 22 4.5 6 13 16 19 6.0 t clock pulse width 80 22 100 120 ns 2.0 Fig. 8 W HIGH or LOW 16 8 20 24 4.5 14 6 17 20 6.0 t master reset pulse width 80 28 100 120 ns 2.0 Fig. 9 W LOW 16 10 20 24 4.5 14 8 17 20 6.0 t removal time 100 30 125 150 ns 2.0 Fig. 9 rem MR to CP 20 11 25 30 4.5 17 9 21 26 6.0 t set-up time 80 22 100 120 ns 2.0 Fig. 11 su D to CP 16 8 20 24 4.5 n 14 6 17 20 6.0 t set-up time 135 41 170 205 ns 2.0 Fig. 11 su PE to CP 27 15 34 41 4.5 23 12 29 35 6.0 December1990 6

Philips Semiconductors Product specification Presettable synchronous BCD decade 74HC/HCT160 counter; asynchronous reset T ((cid:176) C) TEST CONDITIONS amb 74HC SYMBOL PARAMETER UNIT WAVEFORMS V +25 - 40to+85 - 40to+125 CC (V) min. typ. max. min. max. min. max. t set-up time 200 63 250 300 ns 2.0 Fig. 12 su CEP, CET to CP 40 23 50 60 4.5 34 18 43 51 6.0 t hold time 0 - 17 0 0 ns 2.0 Figs 11 and 12 h D to CP 0 - 6 0 0 4.5 n 0 - 5 0 0 6.0 t hold time 0 - 41 0 0 ns 2.0 Figs 11 and 12 h PE to CP 0 - 15 0 0 4.5 0 - 12 0 0 6.0 t hold time 0 - 58 0 0 ns 2.0 Figs 11 and 12 h CEP, CET to CP 0 - 21 0 0 4.5 0 - 17 0 0 6.0 f maximum clock pulse 6.0 18 4.8 4.0 MHz 2.0 Fig. 8 max frequency 30 55 24 20 4.5 35 66 28 24 6.0 December1990 7

Philips Semiconductors Product specification Presettable synchronous BCD decade 74HC/HCT160 counter; asynchronous reset DC CHARACTERISTICS FOR 74HCT For the DC characteristics see“74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: standard I category: MSI CC Note to HCT types The value of additional quiescent supply current (D I ) for unit load of 1 is given in the family specifications. CC To determineD I per input, multiply this value by the unit load coefficient shown in the table below. CC INPUT UNIT LOAD COEFFICIENT MR 0.95 CP 0.80 CEP 0.25 D 0.25 n CET 1.05 PT 0.30 December1990 8

Philips Semiconductors Product specification Presettable synchronous BCD decade 74HC/HCT160 counter; asynchronous reset AC CHARACTERISTICS FOR 74HCT GND=0 V; t =t =6 ns; C =50 pF r f L T ((cid:176) C) TEST CONDITIONS amb 74HCT SYMBOL PARAMETER UNIT WAVEFORMS V +25 - 40to+85 - 40to+125 CC (V) min. typ. max. min. max. min. max. t / t propagation delay 25 43 54 65 ns 4.5 Fig. 8 PHL PLH CP to Q n t propagation delay 28 48 60 72 ns 4.5 Fig. 8 PHL CP to TC t propagation delay 23 39 49 59 ns 4.5 Fig. 8 PLH CP to TC t propagation delay 27 50 63 75 ns 4.5 Fig. 9 PHL MR to Q n t propagation delay 30 50 63 75 ns 4.5 Fig. 9 PHL MR to TC t propagation delay 17 35 44 53 ns 4.5 Fig. 10 PHL CET to TC t propagation delay 9 17 21 26 ns 4.5 Fig. 10 PLH CET to TC t / t output transition time 7 15 19 22 ns 4.5 Figs 8 and 10 THL TLH t clock pulse width 16 8 20 24 ns 4.5 Fig. 8 W HIGH or LOW t master reset pulse width 20 11 25 30 ns 4.5 Fig. 9 W LOW t removal time 20 9 25 30 ns 4.5 Fig. 9 rem MR to CP t set-up time 18 10 25 30 ns 4.5 Fig. 11 su D to CP n t set-up time 30 18 44 53 ns 4.5 Fig. 11 su PE to CP t set-up time 50 30 63 75 ns 4.5 Fig. 12 su CEP, CET to CP t hold time 0 - 8 0 0 ns 4.5 Figs 11 and 12 h D to CP n t hold time 0 - 13 0 0 ns 4.5 Figs 11 and 12 h PE to CP t hold time 0 - 21 0 0 ns 4.5 Figs 11 and 12 h CEP, CET to CP f maximum clock pulse 16 28 13 11 MHz 4.5 Fig. 8 max frequency PACKAGE OUTLINES See“74HC/HCT/HCU/HCMOS Logic Package Outlines”. December1990 9