74AVC2T45 Dual-bit, dual-supply voltage level translator/transceiver; 3-state Rev. 9 — 25 September 2018 Product data sheet 1. General description The 74AVC2T45 is a dual-bit, dual-supply transceiver that enables bidirectional level translation. It features two data input-output ports (nA and nB), a direction control input (DIR) and dual-supply pins (V and V ). Both V and V can be supplied at any voltage between 0.8 V CC(A) CC(B) CC(A) CC(B) and 3.6 V making the device suitable for translating between any of the low voltage nodes (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V and 3.3 V). Pins nA and DIR are referenced to V and pins nB CC(A) are referenced to V . A HIGH on DIR allows transmission from nA to nB and a LOW on DIR CC(B) allows transmission from nB to nA. The device is fully specified for partial power-down applications using I . The I circuitry OFF OFF disables the output, preventing any damaging backflow current through the device when it is powered down. In Suspend mode when either V or V are at GND level, both A and B are CC(A) CC(B) in the high-impedance OFF-state. 2. Features and benefits • Wide supply voltage range: • V : 0.8 V to 3.6 V CC(A) • V : 0.8 V to 3.6 V CC(B) • High noise immunity • Complies with JEDEC standards: • JESD8-12 (0.8 V to 1.3 V) • JESD8-11 (0.9 V to 1.65 V) • JESD8-7 (1.2 V to 1.95 V) • JESD8-5 (1.8 V to 2.7 V) • JESD8-B (2.7 V to 3.6 V) • ESD protection: • HBM JESD22-A114F Class 3B exceeds 8000 V • MM JESD22-A115-A exceeds 200 V • CDM JESD22-C101C exceeds 1000 V • Maximum data rates: • 500 Mbit/s (1.8 V to 3.3 V translation) • 320 Mbit/s (<1.8 V to 3.3 V translation) • 320 Mbit/s (translate to 2.5 V or 1.8 V) • 280 Mbit/s (translate to 1.5 V) • 240 Mbit/s (translate to 1.2 V) • Suspend mode • Latch-up performance exceeds 100 mA per JESD 78 Class II • Inputs accept voltages up to 3.6 V • Low noise overshoot and undershoot < 10 % of V CC • I circuitry provides partial Power-down mode operation OFF • Multiple package options • Specified from -40 °C to +85 °C and -40 °C to +125 °C

Nexperia 74AVC2T45 Dual-bit, dual-supply voltage level translator/transceiver; 3-state 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AVC2T45DP -40 °C to +125 °C TSSOP8 plastic thin shrink small outline package; 8 leads; SOT505-2 body width 3 mm; lead length 0.5 mm 74AVC2T45DC -40 °C to +125 °C VSSOP8 plastic very thin shrink small outline package; SOT765-1 8 leads; body width 2.3 mm 74AVC2T45GT -40 °C to +125 °C XSON8 plastic extremely thin small outline package; SOT833-1 no leads; 8 terminals; body 1 x 1.95 x 0.5 mm 74AVC2T45GF -40 °C to +125 °C XSON8 extremely thin small outline package; no leads; SOT1089 8 terminals; body 1.35 x 1 x 0.5 mm 74AVC2T45GN -40 °C to +125 °C XSON8 extremely thin small outline package; no leads; SOT1116 8 terminals; body 1.2 x 1.0 x 0.35 mm 74AVC2T45GS -40 °C to +125 °C XSON8 extremely thin small outline package; no leads; SOT1203 8 terminals; body 1.35 x 1.0 x 0.35 mm 4. Marking Table 2. Marking Type number Marking code [1] 74AVC2T45DP B45 74AVC2T45DC B45 74AVC2T45GT B45 74AVC2T45GF B5 74AVC2T45GN B5 74AVC2T45GS B5 [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram 5 DIR DIR 2 1A 1A 7 1B 1B 3 2A 2A 6 2B 2B VCC(A) VCC(B) VCC(A) VCC(B) 001aag577 001aag578 Fig. 1. Logic symbol Fig. 2. Logic diagram 74AVC2T45 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved Product data sheet Rev. 9 — 25 September 2018 2 / 23

Nexperia 74AVC2T45 Dual-bit, dual-supply voltage level translator/transceiver; 3-state 6. Pinning information 6.1. Pinning 74AVC2T45 VCC(A) 1 8 VCC(B) 1A 2 7 1B 74AVC2T45 2A 3 6 2B VCC(A) 1 8 VCC(B) 1A 2 7 1B GND 4 5 DIR 2A 3 6 2B 001aag580 GND 4 5 DIR Transparent top view 001aag579 Fig. 4. Pin configuration SOT833-1, SOT1089, Fig. 3. Pin configuration SOT505-2 and SOT765-1 SOT1116 and SOT1203 6.2. Pin description Table 3. Pin description Symbol Pin Description V 1 supply voltage A (referenced to pins 1A, 2A and DIR) CC(A) 1A 2 data input or output 2A 3 data input or output GND 4 ground (0 V) DIR 5 direction control 2B 6 data input or output 1B 7 data input or output V 8 supply voltage B (referenced to pins 1B and 2B) CC(B) 7. Functional description Table 4. Function table H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state. Supply voltage Input Input/output [1] V , V DIR [2] nA nB CC(A) CC(B) 0.8 V to 3.6 V L nA = nB input 0.8 V to 3.6 V H input nB = nA GND [3] X Z Z [1] The input circuit of the data I/O is always active. [2] The DIR input circuit is referenced to VCC(A). [3] If at least one of VCC(A) or VCC(B) is at GND level, the device goes into Suspend mode. 74AVC2T45 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved Product data sheet Rev. 9 — 25 September 2018 3 / 23

Nexperia 74AVC2T45 Dual-bit, dual-supply voltage level translator/transceiver; 3-state 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit V supply voltage A -0.5 +4.6 V CC(A) V supply voltage B -0.5 +4.6 V CC(B) I input clamping current V < 0 V -50 - mA IK I V input voltage [1] -0.5 +4.6 V I I output clamping current V < 0 V -50 - mA OK O V output voltage Active mode [1][2][3] -0.5 V + 0.5 V O CCO Suspend or 3-state mode [1] -0.5 +4.6 V I output current V = 0 V to V - ±50 mA O O CCO I supply current I or I - 100 mA CC CC(A) CC(B) I ground current -100 - mA GND T storage temperature -65 +150 °C stg P total power dissipation T = -40 °C to +125 °C [4] - 250 mW tot amb [1] The minimum input voltage rating and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] VCCO is the supply voltage associated with the output port. [3] VCCO + 0.5 V should not exceed 4.6 V. [4] For TSSOP8 package: above 55 °C the value of Ptot derates linearly at 2.5 mW/K. For VSSOP8 package: above 110 °C the value of Ptot derates linearly with 8 mW/K. For XSON8 packages: above 118 °C the value of Ptot derates linearly with 7.8 mW/K. 9. Recommended operating conditions Table 6. Recommended operating conditions Symbol Parameter Conditions Min Max Unit V supply voltage A 0.8 3.6 V CC(A) V supply voltage B 0.8 3.6 V CC(B) V input voltage 0 3.6 V I V output voltage Active mode [1] 0 V V O CCO Suspend or 3-state mode 0 3.6 V T ambient temperature -40 +125 °C amb Δt/ΔV input transition rise and fall rate V = 0.8 V to 3.6 V [2] - 5 ns/V CCI [1] VCCO is the supply voltage associated with the output port. [2] VCCI is the supply voltage associated with the input port. 74AVC2T45 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved Product data sheet Rev. 9 — 25 September 2018 4 / 23

Nexperia 74AVC2T45 Dual-bit, dual-supply voltage level translator/transceiver; 3-state 10. Static characteristics Table 7. Typical static characteristics at T = 25 °C amb At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit V HIGH-level output V = V or V ; I = -1.5 mA; - 0.69 - V OH I IH IL O voltage V = V = 0.8 V CC(A) CC(B) V LOW-level output V = V or V ; I = 1.5 mA; - 0.07 - V OL I IH IL O voltage V = V = 0.8 V CC(A) CC(B) I input leakage DIR input; V = 0 V or 3.6 V; - ±0.025 ±0.25 μA I I current V = V = 0.8 V to 3.6 V CC(A) CC(B) I OFF-state output A or B port; V = 0 V or V ; [1][2] - ±0.5 ±2.5 μA OZ O CCO current V = V = 0.8 V to 3.6 V CC(A) CC(B) I power-off leakage A port; V or V = 0 V to 3.6 V; V = 0 V; - ±0.1 ±1 μA OFF I O CC(A) current V = 0.8 V to 3.6 V CC(B) B port; V or V = 0 V to 3.6 V; V = 0 V; - ±0.1 ±1 μA I O CC(B) V = 0.8 V to 3.6 V CC(A) C input capacitance DIR input; V = 0 V or 3.3 V; - 1.0 - pF I I V = V = 3.3 V CC(A) CC(B) C input/output A and B port; Suspend mode; [2] - 4.0 - pF I/O capacitance V = V or GND; V = V = 3.3 V O CCO CC(A) CC(B) [1] For I/O ports, the parameter IOZ includes the input leakage current. [2] VCCO is the supply voltage associated with the output port. Table 8. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions -40 °C to +85 °C -40 °C to +125 °C Unit Min Max Min Max V HIGH-level data input [1] IH input voltage V = 0.8 V 0.70V - 0.70V - V CCI CCI CCI V = 1.1 V to 1.95 V 0.65V - 0.65V - V CCI CCI CCI V = 2.3 V to 2.7 V 1.6 - 1.6 - V CCI V = 3.0 V to 3.6 V 2 - 2 - V CCI DIR input V = 0.8 V 0.70V - 0.70V - V CC(A) CC(A) CC(A) V = 1.1 V to 1.95 V 0.65V - 0.65V - V CC(A) CC(A) CC(A) V = 2.3 V to 2.7 V 1.6 - 1.6 - V CC(A) V = 3.0 V to 3.6 V 2 - 2 - V CC(A) V LOW-level data input [1] IL input voltage V = 0.8 V - 0.30V - 0.30V V CCI CCI CCI V = 1.1 V to 1.95 V - 0.35V - 0.35V V CCI CCI CCI V = 2.3 V to 2.7 V - 0.7 - 0.7 V CCI V = 3.0 V to 3.6 V - 0.9 - 0.9 V CCI DIR input V = 0.8 V - 0.30V - 0.30V V CC(A) CC(A) CC(A) V = 1.1 V to 1.95 V - 0.35V - 0.35V V CC(A) CC(A) CC(A) V = 2.3 V to 2.7 V - 0.7 - 0.7 V CC(A) V = 3.0 V to 3.6 V - 0.9 - 0.9 V CC(A) 74AVC2T45 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved Product data sheet Rev. 9 — 25 September 2018 5 / 23

Nexperia 74AVC2T45 Dual-bit, dual-supply voltage level translator/transceiver; 3-state Symbol Parameter Conditions -40 °C to +85 °C -40 °C to +125 °C Unit Min Max Min Max V HIGH-level V = V or V [2] OH I IH IL output voltage I = -100 μA; V - 0.1 - V - 0.1 - V O CCO CCO V = V = 0.8 V to 3.6 V CC(A) CC(B) I = -3 mA; V = V = 1.1 V 0.85 - 0.85 - V O CC(A) CC(B) I = -6 mA; V = V = 1.4 V 1.05 - 1.05 - V O CC(A) CC(B) I = -8 mA; V = V = 1.65 V 1.2 - 1.2 - V O CC(A) CC(B) I = -9 mA; V = V = 2.3 V 1.75 - 1.75 - V O CC(A) CC(B) I = -12 mA; V = V = 3.0 V 2.3 - 2.3 - V O CC(A) CC(B) V LOW-level V = V or V OL I IH IL output voltage I = 100 μA; - 0.1 - 0.1 V O V = V = 0.8 V to 3.6 V CC(A) CC(B) I = 3 mA; V = V = 1.1 V - 0.25 - 0.25 V O CC(A) CC(B) I = 6 mA; V = V = 1.4 V - 0.35 - 0.35 V O CC(A) CC(B) I = 8 mA; V = V = 1.65 V - 0.45 - 0.45 V O CC(A) CC(B) I = 9 mA; V = V = 2.3 V - 0.55 - 0.55 V O CC(A) CC(B) I = 12 mA; V = V = 3.0 V - 0.7 - 0.7 V O CC(A) CC(B) I input leakage DIR input; V = 0 V or 3.6 V; - ±1 - ±1.5 μA I I current V = V = 0.8 V to 3.6 V CC(A) CC(B) I OFF-state A or B port; V = 0 V or V ; [2][3] - ±5 - ±7.5 μA OZ O CCO output current V = V = 3.6 V CC(A) CC(B) I power-off A port; V or V = 0 V to 3.6 V; - ±5 - ±35 μA OFF I O leakage V = 0 V; V = 0.8 V to 3.6 V CC(A) CC(B) current B port; V or V = 0 V to 3.6 V; - ±5 - ±35 μA I O V = 0 V; V = 0.8 V to 3.6 V CC(B) CC(A) I supply current A port; V = 0 V or V ; I = 0 A [1] CC I CCI O V = 0.8 V to 3.6 V; - 8 - 11.5 μA CC(A) V = 0.8 V to 3.6 V CC(B) V = 3.6 V; V = 0 V - 8 - 11.5 μA CC(A) CC(B) V = 0 V; V = 3.6 V -2 - -8 - μA CC(A) CC(B) B port; V = 0 V or V ; I = 0 A [1] I CCI O V = 0.8 V to 3.6 V; - 8 - 11.5 μA CC(A) V = 0.8 V to 3.6 V CC(B) V = 3.6 V; V = 0 V -2 - -8 - μA CC(A) CC(B) V = 0 V; V = 3.6 V - 8 - 11.5 μA CC(A) CC(B) A plus B port (I + I ); [1] - 16 - 23 μA CC(A) CC(B) I = 0 A; V = 0 V or V ; O I CCI V = 0.8 V to 3.6 V; CC(A) V = 0.8 V to 3.6 V CC(B) [1] VCCI is the supply voltage associated with the data input port. [2] VCCO is the supply voltage associated with the output port. [3] For I/O ports, the parameter IOZ includes the input leakage current. 74AVC2T45 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved Product data sheet Rev. 9 — 25 September 2018 6 / 23

Nexperia 74AVC2T45 Dual-bit, dual-supply voltage level translator/transceiver; 3-state 11. Dynamic characteristics Table 9. Typical dynamic characteristics at V = 0.8 V and T = 25 °C CC(A) amb Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 7; for wave forms see Fig. 5 and Fig. 6 Symbol Parameter Conditions V Unit CC(B) 0.8 V 1.2 V 1.5 V 1.8 V 2.5 V 3.3 V t propagation delay A to B [1] 15.5 8.1 7.6 7.7 8.4 9.2 ns pd B to A [1] 15.5 12.7 12.3 12.2 12.0 11.8 ns t disable time DIR to A [2] 12.2 12.2 12.2 12.2 12.2 12.2 ns dis DIR to B [2] 11.7 7.9 7.6 8.2 8.7 10.2 ns t enable time DIR to A [3] 27.2 20.6 19.9 20.4 20.7 22.0 ns en DIR to B [3] 27.7 20.3 19.8 19.9 20.6 21.4 ns [1] tpd is the same as tPLH and tPHL [2] tdis is the same as tPLZ and tPHZ [3] ten is the same as tPZL and tPZH ten is a calculated value using the formula shown in Section 12.4 Table 10. Typical dynamic characteristics at V = 0.8 V and T = 25 °C CC(B) amb Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 7; for wave forms see Fig. 5 and Fig. 6 Symbol Parameter Conditions V Unit CC(A) 0.8 V 1.2 V 1.5 V 1.8 V 2.5 V 3.3 V t propagation delay A to B [1] 15.5 12.7 12.3 12.2 12.0 11.8 ns pd B to A [1] 15.5 8.1 7.6 7.7 8.4 9.2 ns t disable time DIR to A [2] 12.2 4.9 3.8 3.7 2.8 3.4 ns dis DIR to B [2] 11.7 9.2 9.0 8.8 8.7 8.6 ns t enable time DIR to A [3] 27.2 17.3 16.6 16.5 17.1 17.8 ns en DIR to B [3] 27.7 17.6 16.1 15.9 14.8 15.2 ns [1] tpd is the same as tPLH and tPHL [2] tdis is the same as tPLZ and tPHZ [3] ten is the same as tPZL and tPZH ten is a calculated value using the formula shown in Section 12.4 Table 11. Typical power dissipation capacitance at V = V and T = 25 °C CC(A) CC(B) amb Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions V and V Unit CC(A) CC(B) 0.8 V 1.2 V 1.5 V 1.8 V 2.5 V 3.3 V C power dissipation [1][2] PD capacitance A port: (direction A to B); 1 2 2 2 2 2 pF B port: (direction B to A) A port: (direction B to A); 9 11 11 12 14 17 pF B port: (direction A to B) [1] CPD is used to determine the dynamic power dissipation (PD in μW). PD = CPD x VCC2 x fi x N + ∑(CL x VCC2 x fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; Σ(CL x VCC2 x fo) = sum of the outputs. [2] fi = 10 MHz; VI = GND to VCC; tr = tf = 1 ns; CL = 0 pF; RL = ∞ Ω. 74AVC2T45 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved Product data sheet Rev. 9 — 25 September 2018 7 / 23

Nexperia 74AVC2T45 Dual-bit, dual-supply voltage level translator/transceiver; 3-state Table 12. Dynamic characteristics for temperature range -40 °C to +85 °C Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 7; for wave forms see Fig. 5 and Fig. 6. Symbol Parameter Conditions V Unit CC(B) 1.2 V 1.5 V 1.8 V 2.5 V 3.3 V ± 0.1 V ± 0.1 V ± 0.15 V ± 0.2 V ± 0.3 V Min Max Min Max Min Max Min Max Min Max t propagation A to B [1] pd delay V = 1.1 V to 1.3 V 1.0 9.0 0.7 6.8 0.6 6.1 0.5 5.7 0.5 6.1 ns CC(A) V = 1.4 V to 1.6 V 1.0 8.0 0.7 5.4 0.6 4.6 0.5 3.7 0.5 3.5 ns CC(A) V = 1.65 V to 1.95 V 1.0 7.7 0.6 5.1 0.5 4.3 0.5 3.4 0.5 3.1 ns CC(A) V = 2.3 V to 2.7 V 1.0 7.2 0.5 4.7 0.5 3.9 0.5 3.0 0.5 2.6 ns CC(A) V = 3.0 V to 3.6 V 1.0 7.1 0.5 4.5 0.5 3.7 0.5 2.8 0.5 2.4 ns CC(A) B to A [1] V = 1.1 V to 1.3 V 1.0 9.0 0.8 8.0 0.7 7.7 0.6 7.2 0.5 7.1 ns CC(A) V = 1.4 V to 1.6 V 1.0 6.8 0.8 5.4 0.7 5.1 0.6 4.7 0.5 4.5 ns CC(A) V = 1.65 V to 1.95 V 1.0 6.1 0.7 4.6 0.5 4.4 0.5 3.9 0.5 3.7 ns CC(A) V = 2.3 V to 2.7 V 1.0 5.7 0.6 3.8 0.5 3.4 0.5 3.0 0.5 2.8 ns CC(A) V = 3.0 V to 3.6 V 1.0 6.1 0.6 3.6 0.5 3.1 0.5 2.6 0.5 2.4 ns CC(A) t disable time DIR to A [2] dis V = 1.1 V to 1.3 V 2.2 8.8 2.2 8.8 2.2 8.8 2.2 8.8 2.2 8.8 ns CC(A) V = 1.4 V to 1.6 V 1.6 6.3 1.6 6.3 1.6 6.3 1.6 6.3 1.6 6.3 ns CC(A) V = 1.65 V to 1.95 V 1.6 5.5 1.6 5.5 1.6 5.5 1.6 5.5 1.6 5.5 ns CC(A) V = 2.3 V to 2.7 V 1.5 4.2 1.5 4.2 1.5 4.2 1.5 4.2 1.5 4.2 ns CC(A) V = 3.0 V to 3.6 V 1.5 4.7 1.5 4.7 1.5 4.7 1.5 4.7 1.5 4.7 ns CC(A) DIR to B [2] V = 1.1 V to 1.3 V 2.2 8.4 1.8 6.7 2.0 6.9 1.7 6.2 2.4 7.2 ns CC(A) V = 1.4 V to 1.6 V 2.0 7.6 1.8 5.9 1.6 6.0 1.2 4.8 1.7 5.5 ns CC(A) V = 1.65 V to 1.95 V 1.8 7.7 1.8 5.7 1.4 5.8 1.0 4.5 1.5 5.2 ns CC(A) V = 2.3 V to 2.7 V 1.7 7.3 2.0 5.2 1.5 5.1 0.6 4.2 1.1 4.8 ns CC(A) V = 3.0 V to 3.6 V 1.7 7.2 0.7 5.5 0.6 5.5 0.7 4.1 1.7 4.7 ns CC(A) t enable time DIR to A [3][4] en V = 1.1 V to 1.3 V - 17.4 - 14.7 - 14.6 - 13.4 - 14.3 ns CC(A) V = 1.4 V to 1.6 V - 14.4 - 11.3 - 11.1 - 9.5 - 10.0 ns CC(A) V = 1.65 V to 1.95 V - 13.8 - 10.3 - 10.2 - 8.4 - 8.9 ns CC(A) V = 2.3 V to 2.7 V - 13.0 - 9.0 - 8.5 - 7.2 - 7.6 ns CC(A) V = 3.0 V to 3.6 V - 13.3 - 9.1 - 8.6 - 6.7 - 7.1 ns CC(A) DIR to B [3][4] V = 1.1 V to 1.3 V - 17.8 - 15.6 - 14.9 - 14.5 - 14.9 ns CC(A) V = 1.4 V to 1.6 V - 14.3 - 11.7 - 10.9 - 10.0 - 9.8 ns CC(A) V = 1.65 V to 1.95 V - 13.2 - 10.6 - 9.8 - 8.9 - 8.6 ns CC(A) V = 2.3 V to 2.7 V - 11.4 - 8.9 - 8.1 - 7.2 - 6.8 ns CC(A) V = 3.0 V to 3.6 V - 11.8 - 9.2 - 8.4 - 7.5 - 7.1 ns CC(A) [1] tpd is the same as tPLH and tPHL [2] tdis is the same as tPLZ and tPHZ [3] ten is the same as tPZL and tPZH [4] ten is a calculated value using the formula shown in Section 12.4 74AVC2T45 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved Product data sheet Rev. 9 — 25 September 2018 8 / 23

Nexperia 74AVC2T45 Dual-bit, dual-supply voltage level translator/transceiver; 3-state Table 13. Dynamic characteristics for temperature range -40 °C to +125 °C Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 7; for wave forms see Fig. 5 and Fig. 6. Symbol Parameter Conditions V Unit CC(B) 1.2 V 1.5 V 1.8 V 2.5 V 3.3 V ± 0.1 V ± 0.1 V ± 0.15 V ± 0.2 V ± 0.3 V Min Max Min Max Min Max Min Max Min Max t propagation A to B [1] pd delay V = 1.1 V to 1.3 V 1.0 9.9 0.7 7.5 0.6 6.8 0.5 6.3 0.5 6.8 ns CC(A) V = 1.4 V to 1.6 V 1.0 8.8 0.7 6.0 0.6 5.1 0.5 4.1 0.5 3.9 ns CC(A) V = 1.65 V to 1.95 V 1.0 8.5 0.6 5.7 0.5 4.8 0.5 3.8 0.5 3.5 ns CC(A) V = 2.3 V to 2.7 V 1.0 8.0 0.5 5.2 0.5 4.3 0.5 3.3 0.5 2.9 ns CC(A) V = 3.0 V to 3.6 V 1.0 7.9 0.5 5.0 0.5 4.1 0.5 3.1 0.5 2.7 ns CC(A) B to A [1] V = 1.1 V to 1.3 V 1.0 9.9 0.8 8.8 0.7 8.5 0.6 8.0 0.5 7.9 ns CC(A) V = 1.4 V to 1.6 V 1.0 7.5 0.8 6.0 0.7 5.7 0.6 5.2 0.5 5.0 ns CC(A) V = 1.65 V to 1.95 V 1.0 6.8 0.7 5.1 0.5 4.9 0.5 4.3 0.5 4.1 ns CC(A) V = 2.3 V to 2.7 V 1.0 6.3 0.6 4.2 0.5 3.8 0.5 3.3 0.5 3.1 ns CC(A) V = 3.0 V to 3.6 V 1.0 6.8 0.6 4.0 0.5 3.5 0.5 2.9 0.5 2.7 ns CC(A) t disable time DIR to A [2] dis V = 1.1 V to 1.3 V 2.2 9.7 2.2 9.7 2.2 9.7 2.2 9.7 2.2 9.7 ns CC(A) V = 1.4 V to 1.6 V 1.6 7.0 1.6 7.0 1.6 7.0 1.6 7.0 1.6 7.0 ns CC(A) V = 1.65 V to 1.95 V 1.6 6.1 1.6 6.1 1.6 6.1 1.6 6.1 1.6 6.1 ns CC(A) V = 2.3 V to 2.7 V 1.5 4.7 1.5 4.7 1.5 4.7 1.5 4.7 1.5 4.7 ns CC(A) V = 3.0 V to 3.6 V 1.5 5.2 1.5 5.2 1.5 5.2 1.5 5.2 1.5 5.2 ns CC(A) DIR to B [2] V = 1.1 V to 1.3 V 2.2 9.2 1.8 7.4 2.0 7.6 1.7 6.9 2.4 8.0 ns CC(A) V = 1.4 V to 1.6 V 2.0 8.3 1.8 6.5 1.6 6.6 1.2 5.3 1.7 6.1 ns CC(A) V = 1.65 V to 1.95 V 1.8 8.5 1.8 6.3 1.4 6.4 1.0 5.0 1.5 5.8 ns CC(A) V = 2.3 V to 2.7 V 1.7 8.0 2.0 5.8 1.5 5.7 0.6 4.7 1.1 5.3 ns CC(A) V = 3.0 V to 3.6 V 1.7 7.9 0.7 6.1 0.6 6.1 0.7 4.6 1.7 5.2 ns CC(A) t enable time DIR to A [3][4] en V = 1.1 V to 1.3 V - 19.1 - 16.2 - 16.1 - 14.9 - 15.9 ns CC(A) V = 1.4 V to 1.6 V - 15.8 - 12.5 - 12.3 - 10.5 - 11.1 ns CC(A) V = 1.65 V to 1.95 V - 15.3 - 11.4 - 11.3 - 9.3 - 9.9 ns CC(A) V = 2.3 V to 2.7 V - 14.3 - 10.0 - 9.5 - 8.0 - 8.4 ns CC(A) V = 3.0 V to 3.6 V - 14.7 - 10.1 - 9.6 - 7.5 - 7.9 ns CC(A) DIR to B [3][4] V = 1.1 V to 1.3 V - 19.6 - 17.2 - 16.5 - 16.0 - 16.5 ns CC(A) V = 1.4 V to 1.6 V - 15.8 - 13.0 - 12.1 - 11.1 - 10.9 ns CC(A) V = 1.65 V to 1.95 V - 14.6 - 11.8 - 10.9 - 9.9 - 9.6 ns CC(A) V = 2.3 V to 2.7 V - 12.7 - 9.9 - 9.0 - 8.0 - 7.6 ns CC(A) V = 3.0 V to 3.6 V - 13.1 - 10.2 - 9.3 - 8.3 - 7.9 ns CC(A) [1] tpd is the same as tPLH and tPHL [2] tdis is the same as tPLZ and tPHZ [3] ten is the same as tPZL and tPZH [4] ten is a calculated value using the formula shown in Section 12.4 74AVC2T45 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved Product data sheet Rev. 9 — 25 September 2018 9 / 23

Nexperia 74AVC2T45 Dual-bit, dual-supply voltage level translator/transceiver; 3-state 11.1. Waveforms and test circuit VI nA, nB input VM GND tPHL tPLH VOH nB, nA output VM VOL 001aak114 Measurement points are given in Table 14. V and V are typical output voltage levels that occur with the output load. OL OH Fig. 5. The data input (nA, nB) to output (nB, nA) propagation delay times VI DIR input VM GND tPLZ tPZL VCCO output LOW-to-OFF VM OFF-to-LOW VOL VX tPHZ tPZH output VOH VY HIGH-to-OFF VM OFF-to-HIGH GND outputs outputs outputs enabled disabled enabled 001aae968 Measurement points are given in Table 14. V and V are typical output voltage levels that occur with the output load. OL OH Fig. 6. Enable and disable times Table 14. Measurement points Supply voltage Input [1] Output [2] V , V V V V V CC(A) CC(B) M M X Y 1.1 V to 1.6 V 0.5V 0.5V V + 0.1 V V - 0.1 V CCI CCO OL OH 1.65 V to 2.7 V 0.5V 0.5V V + 0.15 V V - 0.15 V CCI CCO OL OH 3.0 V to 3.6 V 0.5V 0.5V V + 0.3 V V - 0.3 V CCI CCO OL OH [1] VCCI is the supply voltage associated with the data input port. [2] VCCO is the supply voltage associated with the output port. 74AVC2T45 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved Product data sheet Rev. 9 — 25 September 2018 10 / 23

Nexperia 74AVC2T45 Dual-bit, dual-supply voltage level translator/transceiver; 3-state tW VI 90 % negative pulse VM VM 10 % 0 V tf tr tr tf VI 90 % positive pulse VM VM 10 % 0 V tW VEXT VCC RL VI VO G DUT RT CL RL 001aae331 Test data is given in Table 15. R = Load resistance. L C = Load capacitance including jig and probe capacitance. L R = Termination resistance. T V = External voltage for measuring switching times. EXT Fig. 7. Test circuit for measuring switching times Table 15. Test data Supply voltage Input Load V EXT V , V V [1] Δt/ΔV [2] C R t , t t , t t , t [3] CC(A) CC(B) I L L PLH PHL PZH PHZ PZL PLZ 1.1 V to 1.6 V V ≤ 1.0 ns/V 15 pF 2 kΩ open GND 2V CCI CCO 1.65 V to 2.7 V V ≤ 1.0 ns/V 15 pF 2 kΩ open GND 2V CCI CCO 3.0 V to 3.6 V V ≤ 1.0 ns/V 15 pF 2 kΩ open GND 2V CCI CCO [1] VCCI is the supply voltage associated with the data input port. [2] dV/dt ≥ 1.0 V/ns [3] VCCO is the supply voltage associated with the output port. 74AVC2T45 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved Product data sheet Rev. 9 — 25 September 2018 11 / 23

Nexperia 74AVC2T45 Dual-bit, dual-supply voltage level translator/transceiver; 3-state 12. Application information 12.1. Unidirectional logic level-shifting application The circuit given in Fig. 8 is an example of the 74AVC2T45 being used in an unidirectional logic level-shifting application. VCC1 VCC2 74AVC2T45 VCC1 VCC(A) VCC(B) VCC2 1 8 1A 1B 2 7 2A 2B 3 6 GND DIR 4 5 VCC1 VCC2 system-1 system-2 001aag581 Fig. 8. Unidirectional logic level-shifting application Table 16. Unidirectional logic level-shifting application Pin Name Function Description 1 V V supply voltage of system-1 (0.8 V to 3.6 V) CC(A) CC1 2 1A OUT1 output level depends on V voltage CC1 3 2A OUT2 output level depends on V voltage CC1 4 GND GND device GND 5 DIR DIR the GND (LOW level) determines B port to A port direction 6 2B IN2 input threshold value depends on V voltage CC2 7 1B IN1 input threshold value depends on V voltage CC2 8 V V supply voltage of system-2 (0.8 V to 3.6 V) CC(B) CC2 74AVC2T45 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved Product data sheet Rev. 9 — 25 September 2018 12 / 23

Nexperia 74AVC2T45 Dual-bit, dual-supply voltage level translator/transceiver; 3-state 12.2. Bidirectional logic level-shifting application Fig. 9 shows the 74AVC2T45 being used in a bidirectional logic level-shifting application. Since the device does not have an output enable (OE) pin, the system designer should take precautions to avoid bus contention between system-1 and system-2 when changing directions. VCC1 VCC1 VCC2 VCC2 74AVC2T45 I/O-1 PULL-UP/DOWN VCC(A) VCC(B) PULL-UP/DOWN I/O-2 1 8 1A 1B 2 7 2A 2B 3 6 GND DIR 4 5 DIR CTRL DIR CTRL system-1 system-2 001aag582 System-1 and system-2 must use the same conditions, i.e., both pull-up or both pull-down. Fig. 9. Bidirectional logic level-shifting application Table 17 gives a sequence that will illustrate data transmission from system-1 to system-2 and then from system-2 to system-1. Table 17. Bidirectional logic level-shifting application H = HIGH voltage level; L = LOW voltage level; Z = high-impedance OFF-state. State DIR CTRL I/O-1 I/O-2 Description 1 H output input system-1 data to system-2 2 H Z Z system-2 is getting ready to send data to system-1. I/O-1 and I/O-2 are disabled. The bus-line state depends on the pull-up or pull-down. 3 L Z Z DIR bit is set LOW. I/O-1 and I/O-2 still are disabled. The bus-line state depends on the pull-up or pull-down. 4 L input output system-2 data to system-1 System-1 and system-2 must use the same conditions, i.e., both pull-up or both pull-down. 74AVC2T45 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved Product data sheet Rev. 9 — 25 September 2018 13 / 23

Nexperia 74AVC2T45 Dual-bit, dual-supply voltage level translator/transceiver; 3-state 12.3. Power-up considerations The device is designed such that no special power-up sequence is required other than GND being applied first. Table 18. Typical total supply current (I + I ) CC(A) CC(B) V V Unit CC(A) CC(B) 0 V 0.8 V 1.2 V 1.5 V 1.8 V 2.5 V 3.3 V 0 V 0 0.1 0.1 0.1 0.1 0.1 0.1 μA 0.8 V 0.1 0.1 0.1 0.1 0.1 0.7 2.3 μA 1.2 V 0.1 0.1 0.1 0.1 0.1 0.3 1.4 μA 1.5 V 0.1 0.1 0.1 0.1 0.1 0.1 0.9 μA 1.8 V 0.1 0.1 0.1 0.1 0.1 0.1 0.5 μA 2.5 V 0.1 0.7 0.3 0.1 0.1 0.1 0.1 μA 3.3 V 0.1 2.3 1.4 0.9 0.5 0.1 0.1 μA 12.4. Enable times The enable times for the 74AVC2T45 are calculated from the following formulas: • t (DIR to nA) = t (DIR to nB) + t (nB to nA) en dis pd • t (DIR to nB) = t (DIR to nA) + t (nA to nB) en dis pd In a bidirectional application, these enable times provide the maximum delay from the time the DIR bit is switched until an output is expected. For example, if the 74AVC2T45 initially is transmitting from A to B, then the DIR bit is switched, the B port of the device must be disabled before presenting it with an input. After the B port has been disabled, an input signal applied to it appears on the corresponding A port after the specified propagation delay. 74AVC2T45 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved Product data sheet Rev. 9 — 25 September 2018 14 / 23

Nexperia 74AVC2T45 Dual-bit, dual-supply voltage level translator/transceiver; 3-state 13. Package outline TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm SOT505-2 D E A X c y HE v M A Z 8 5 A A2 A1 (A3) pin 1 index θ Lp L 1 4 detail X e w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT mAax . A1 A2 A3 bp c D(1) E(1) e HE L Lp v w y Z(1) θ 0.15 0.95 0.38 0.18 3.1 3.1 4.1 0.47 0.70 8° mm 1.1 0.25 0.65 0.5 0.2 0.13 0.1 0.00 0.75 0.22 0.08 2.9 2.9 3.9 0.33 0.35 0° Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE REFERENCES EUROPEAN ISSUE DATE VERSION IEC JEDEC JEITA PROJECTION SOT505-2 - - - 02-01-16 Fig. 10. Package outline SOT505-2 (TSSOP8) 74AVC2T45 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved Product data sheet Rev. 9 — 25 September 2018 15 / 23

Nexperia 74AVC2T45 Dual-bit, dual-supply voltage level translator/transceiver; 3-state VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm SOT765-1 D E A X c y HE v A Z 8 5 Q A2 A pin 1 index A1 (A3) θ Lp 1 4 detail X L e w bp 0 5 mm scale Dimensions (mm are the original dimensions) A Unit max. A1 A2 A3 bp c D(1) E(2) e HE L Lp Q v w y Z(1) θ max 0.15 0.85 0.27 0.23 2.1 2.4 3.2 0.40 0.21 0.4 8° mm nom 1 0.12 0.5 0.4 0.2 0.08 0.1 min 0.00 0.60 0.17 0.08 1.9 2.2 3.0 0.15 0.19 0.1 0° Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. sot765-1_po Outline References European Issue date version IEC JEDEC JEITA projection 07-06-02 SOT765-1 MO-187 16-05-31 Fig. 11. Package outline SOT765-1 (VSSOP8) 74AVC2T45 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved Product data sheet Rev. 9 — 25 September 2018 16 / 23

Nexperia 74AVC2T45 Dual-bit, dual-supply voltage level translator/transceiver; 3-state XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1.95 x 0.5 mm SOT833-1 b 1 2 3 4 4× L1 L (2) e 8 7 6 5 e1 e1 e1 8× A (2) A1 D E terminal 1 index area 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT mA(a1x) mAa1x b D E e e1 L L1 0.25 2.0 1.05 0.35 0.40 mm 0.5 0.04 0.6 0.5 0.17 1.9 0.95 0.27 0.32 Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. OUTLINE REFERENCES EUROPEAN ISSUE DATE VERSION IEC JEDEC JEITA PROJECTION 07-11-14 SOT833-1 - - - MO-252 - - - 07-12-07 Fig. 12. Package outline SOT833-1 (XSON8) 74AVC2T45 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved Product data sheet Rev. 9 — 25 September 2018 17 / 23

Nexperia 74AVC2T45 Dual-bit, dual-supply voltage level translator/transceiver; 3-state XSON8: extremely thin small outline package; no leads; 8 terminals; body 1.35 x 1 x 0.5 mm SOT1089 E terminal 1 index area D A A1 detail X (4×)(2) e L (8×)(2) b 4 5 e1 1 8 terminal 1 index area L1 X 0 0.5 1 mm scale Dimensions Unit A(1) A1 b D E e e1 L L1 max 0.5 0.04 0.20 1.40 1.05 0.35 0.40 mm nom 0.15 1.35 1.00 0.55 0.35 0.30 0.35 min 0.12 1.30 0.95 0.27 0.32 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. sot1089_po Outline References European Issue date version IEC JEDEC JEITA projection 10-04-09 SOT1089 MO-252 10-04-12 Fig. 13. Package outline SOT1089 (XSON8) 74AVC2T45 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved Product data sheet Rev. 9 — 25 September 2018 18 / 23

Nexperia 74AVC2T45 Dual-bit, dual-supply voltage level translator/transceiver; 3-state XSON8: extremely thin small outline package; no leads; 8 terminals; body 1.2 x 1.0 x 0.35 mm SOT1116 b 1 2 3 4 (4×)(2) L1 L e 8 7 6 5 e1 e1 e1 (8×)(2) A1 A D E terminal 1 index area 0 0.5 1 mm scale Dimensions Unit A(1) A1 b D E e e1 L L1 max 0.35 0.04 0.20 1.25 1.05 0.35 0.40 mm nom 0.15 1.20 1.00 0.55 0.3 0.30 0.35 min 0.12 1.15 0.95 0.27 0.32 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. sot1116_po Outline References European Issue date version IEC JEDEC JEITA projection 10-04-02 SOT1116 10-04-07 Fig. 14. Package outline SOT1116 (XSON8) 74AVC2T45 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved Product data sheet Rev. 9 — 25 September 2018 19 / 23

Nexperia 74AVC2T45 Dual-bit, dual-supply voltage level translator/transceiver; 3-state XSON8: extremely thin small outline package; no leads; 8 terminals; body 1.35 x 1.0 x 0.35 mm SOT1203 b 1 2 3 4 (4×)(2) L1 L e 8 7 6 5 e1 e1 e1 (8×)(2) A1 A D E terminal 1 index area 0 0.5 1 mm scale Dimensions Unit A(1) A1 b D E e e1 L L1 max 0.35 0.04 0.20 1.40 1.05 0.35 0.40 mm nom 0.15 1.35 1.00 0.55 0.35 0.30 0.35 min 0.12 1.30 0.95 0.27 0.32 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. sot1203_po Outline References European Issue date version IEC JEDEC JEITA projection 10-04-02 SOT1203 10-04-06 Fig. 15. Package outline SOT1203 (XSON8) 74AVC2T45 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved Product data sheet Rev. 9 — 25 September 2018 20 / 23

Nexperia 74AVC2T45 Dual-bit, dual-supply voltage level translator/transceiver; 3-state 14. Abbreviations Table 19. Abbreviations Acronym Description CDM Charged Device Model DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model 15. Revision history Table 20. Revision history Document ID Release date Data sheet status Change notice Supersedes 74AVC2T45 v.9 20180925 Product data sheet - 74AVC2T45 v.8 Modifications: • Type number 74AVC2T45GD (SOT996-2) removed. 74AVC2T45 v.8 20171013 Product data sheet - 74AVC2T45 v.7 Modifications: • The format of this data sheet has been redesigned to comply with the identity guidelines of Nexperia. • Legal texts have been adapted to the new company name where appropriate. 74AVC2T45 v.7 20130208 Product data sheet - 74AVC2T45 v.6 Modifications: • For type number 74AVC2T45GD XSON8U has changed to XSON8. 74AVC2T45 v.6 20111208 Product data sheet - 74AVC2T45 v.5 74AVC2T45 v.5 20101130 Product data sheet - 74AVC2T45 v.4 74AVC2T45 v.4 20090505 Product data sheet - 74AVC2T45 v.3 74AVC2T45 v.3 20090129 Product data sheet - 74AVC2T45 v.2 74AVC2T45 v.2 20080620 Product data sheet - 74AVC2T45 v.1 74AVC2T45 v.1 20070703 Product data sheet - - 74AVC2T45 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved Product data sheet Rev. 9 — 25 September 2018 21 / 23

Nexperia 74AVC2T45 Dual-bit, dual-supply voltage level translator/transceiver; 3-state injury, death or severe property or environmental damage. Nexperia and its 16. Legal information suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Quick reference data — The Quick reference data is an extract of the Data sheet status product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Document status Product Definition Applications — Applications that are described herein for any of these [1][2] status [3] products are for illustrative purposes only. Nexperia makes no representation Objective [short] Development This document contains data from or warranty that such applications will be suitable for the specified use data sheet the objective specification for without further testing or modification. product development. Customers are responsible for the design and operation of their applications and products using Nexperia products, and Nexperia accepts no liability for Preliminary [short] Qualification This document contains data from any assistance with applications or customer product design. It is customer’s data sheet the preliminary specification. sole responsibility to determine whether the Nexperia product is suitable Product [short] Production This document contains the product and fit for the customer’s applications and products planned, as well as data sheet specification. for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. [1] Please consult the most recently issued document before initiating or completing a design. Nexperia does not accept any liability related to any default, damage, costs [2] The term 'short data sheet' is explained in section "Definitions". or problem which is based on any weakness or default in the customer’s [3] The product status of device(s) described in this document may have applications or products, or the application or use by customer’s third party changed since this document was published and may differ in case of customer(s). Customer is responsible for doing all necessary testing for the multiple devices. The latest product status information is available on customer’s applications and products using Nexperia products in order to the internet at https://www.nexperia.com. avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). Nexperia does not accept any liability in this respect. Definitions Limiting values — Stress above one or more limiting values (as defined in Draft — The document is a draft version only. The content is still under the Absolute Maximum Ratings System of IEC 60134) will cause permanent internal review and subject to formal approval, which may result in damage to the device. Limiting values are stress ratings only and (proper) modifications or additions. Nexperia does not give any representations or operation of the device at these or any other conditions above those warranties as to the accuracy or completeness of information included herein given in the Recommended operating conditions section (if present) or the and shall have no liability for the consequences of use of such information. Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect Short data sheet — A short data sheet is an extract from a full data sheet the quality and reliability of the device. with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain Terms and conditions of commercial sale — Nexperia products are detailed and full information. For detailed and full information see the relevant sold subject to the general terms and conditions of commercial sale, as full data sheet, which is available on request via the local Nexperia sales published at http://www.nexperia.com/profile/terms, unless otherwise agreed office. In case of any inconsistency or conflict with the short data sheet, the in a valid written individual agreement. In case an individual agreement is full data sheet shall prevail. concluded only the terms and conditions of the respective agreement shall apply. Nexperia hereby expressly objects to applying the customer’s general Product specification — The information and data provided in a Product terms and conditions with regard to the purchase of Nexperia products by data sheet shall define the specification of the product as agreed between customer. Nexperia and its customer, unless Nexperia and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be No offer to sell or license — Nothing in this document may be interpreted valid in which the Nexperia product is deemed to offer functions and qualities or construed as an offer to sell products that is open for acceptance or the beyond those described in the Product data sheet. grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein Disclaimers may be subject to export control regulations. Export might require a prior Limited warranty and liability — Information in this document is believed authorization from competent authorities. to be accurate and reliable. However, Nexperia does not give any Non-automotive qualified products — Unless this data sheet expressly representations or warranties, expressed or implied, as to the accuracy states that this specific Nexperia product is automotive qualified, the or completeness of such information and shall have no liability for the product is not suitable for automotive use. It is neither qualified nor tested in consequences of use of such information. Nexperia takes no responsibility accordance with automotive testing or application requirements. Nexperia for the content in this document if provided by an information source outside accepts no liability for inclusion and/or use of non-automotive qualified of Nexperia. products in automotive equipment or applications. In no event shall Nexperia be liable for any indirect, incidental, punitive, In the event that customer uses the product for design-in and use in special or consequential damages (including - without limitation - lost automotive applications to automotive specifications and standards, profits, lost savings, business interruption, costs related to the removal customer (a) shall use the product without Nexperia’s warranty of the or replacement of any products or rework charges) whether or not such product for such automotive applications, use and specifications, and (b) damages are based on tort (including negligence), warranty, breach of whenever customer uses the product for automotive applications beyond contract or any other legal theory. Nexperia’s specifications such use shall be solely at customer’s own risk, Notwithstanding any damages that customer might incur for any reason and (c) customer fully indemnifies Nexperia for any liability, damages or failed whatsoever, Nexperia’s aggregate and cumulative liability towards customer product claims resulting from customer design and use of the product for for the products described herein shall be limited in accordance with the automotive applications beyond Nexperia’s standard warranty and Nexperia’s Terms and conditions of commercial sale of Nexperia. product specifications. Right to make changes — Nexperia reserves the right to make changes Translations — A non-English (translated) version of a document is for to information published in this document, including without limitation reference only. The English version shall prevail in case of any discrepancy specifications and product descriptions, at any time and without notice. This between the translated and English versions. document supersedes and replaces all information supplied prior to the publication hereof. Trademarks Suitability for use — Nexperia products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical Notice: All referenced brands, product names, service names and systems or equipment, nor in applications where failure or malfunction trademarks are the property of their respective owners. of an Nexperia product can reasonably be expected to result in personal 74AVC2T45 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved Product data sheet Rev. 9 — 25 September 2018 22 / 23

Nexperia 74AVC2T45 Dual-bit, dual-supply voltage level translator/transceiver; 3-state Contents 1. General description......................................................1 2. Features and benefits..................................................1 3. Ordering information....................................................2 4. Marking..........................................................................2 5. Functional diagram.......................................................2 6. Pinning information......................................................3 6.1. Pinning.........................................................................3 6.2. Pin description.............................................................3 7. Functional description.................................................3 8. Limiting values.............................................................4 9. Recommended operating conditions..........................4 10. Static characteristics..................................................5 11. Dynamic characteristics.............................................7 11.1. Waveforms and test circuit.......................................10 12. Application information...........................................12 12.1. Unidirectional logic level-shifting application............12 12.2. Bidirectional logic level-shifting application..............13 12.3. Power-up considerations.........................................14 12.4. Enable times............................................................14 13. Package outline........................................................15 14. Abbreviations............................................................21 15. Revision history........................................................21 16. Legal information......................................................22 © Nexperia B.V. 2018. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 25 September 2018 74AVC2T45 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved Product data sheet Rev. 9 — 25 September 2018 23 / 23