74AUP1G373 Low-power D-type transparent latch; 3-state Rev. 6 — 4 July 2012 Product data sheet 1. General description The 74AUP1G373 provides the single D-type transparent latch with 3-state output. While the latch-enable (LE) input is high, the Q output follows the data (D) input. When pinLE is LOW, the latch stores the information that was present at the D-input one set-up time preceding the HIGH-to-LOW transition of pinLE. When pinOE is LOW, the contents of the latch is available at the (Q) output. When pinOE is HIGH, the output goes to the high-impedance OFF-state. Operation of input pinOE does not affect the state of the latch. Schmitt trigger action at all inputs makes the circuit tolerant to slower input riseand fall times across the entire V range from 0.8 V to 3.6 V. CC This device ensures a very low static and dynamic power consumption across the entire V range from 0.8 V to 3.6V. CC This device is fully specified for partial power-down applications usingI . OFF TheI circuitry disables the output, preventing the damaging backflow current through OFF the device when it is powered down. 2. Features and benefits  Wide supply voltage range from 0.8 Vto3.6V  High noise immunity  Complies with JEDEC standards: JESD8-12 (0.8 Vto1.3 V) JESD8-11 (0.9 Vto1.65V) JESD8-7 (1.2 Vto1.95V) JESD8-5 (1.8 Vto2.7V) JESD8-B (2.7 Vto3.6V)  ESD protection: HBM JESD22-A114F Class 3A exceeds 5000V MM JESD22-A115-A exceeds 200V CDM JESD22-C101E exceeds 1000V  Low static power consumption; I = 0.9 A (maximum) CC  Latch-up performance exceeds 100mA per JESD 78 Class II  Inputs accept voltages up to 3.6V  Low noise overshoot and undershoot < 10 % of V CC  I circuitry provides partial Power-down mode operation OFF  Multiple package options  Specified from 40 Cto+85C and 40 Cto+125C

74AUP1G373 Nexperia Low-power D-type transparent latch; 3-state 3. Ordering information Table 1. Ordering info rmation Type number Package Temperature range Name Description Version 74AUP1G373GW 40 C to +125 C SC-88 plastic surface-mounted package; 6 leads SOT363 74AUP1G373GM 40 C to +125 C XSON6 plastic extremely thin small outline package; noleads; SOT886 6 terminals; body 11.450.5mm 74AUP1G373GF 40 C to +125 C XSON6 plastic extremely thin small outline package; noleads; SOT891 6 terminals; body 110.5mm 74AUP1G373GN 40C to +125C XSON6 extremely thin small outline package; noleads; SOT1115 6terminals; body 0.91.00.35mm 74AUP1G373GS 40C to +125C XSON6 extremely thin small outline package; noleads; SOT1202 6terminals; body 1.01.00.35mm 4. Marking Table 2. Marking Type number Marking code[1] 74AUP1G373GW aW 74AUP1G373GM aW 74AUP1G373GF aW 74AUP1G373GN aW 74AUP1G373GS aW [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram D D Q Q 3 D Q 4 LE LE 1 C1 1 LE 3 4 LE OE 6 EN 6 OE 001aae247 001aae248 001aae249 Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram 74AUP1G373 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved Product data sheet Rev. 6 — 4 July 2012 2 of 25

74AUP1G373 Nexperia Low-power D-type transparent latch; 3-state 6. Pinning information 6.1 Pinning 74AUP1G373 74AUP1G373 LE 1 6 OE 74AUP1G373 LE 1 6 OE LE 1 6 OE GND 2 5 VCC GND 2 5 VCC GND 2 5 VCC D 3 4 Q D 3 4 Q D 3 4 Q 001aae251 001aae252 001aae250 Transparent top view Transparent top view Fig 4. Pin configuration SOT363 Fig 5. Pin configuration SOT886 Fig 6. Pin configuration SOT891, SOT1115 and SOT1202 6.2 Pin description Table 3. Pin descripti on Symbol Pin Description LE 1 latch enable input (active HIGH) GND 2 ground (0V) D 3 data input Q 4 latch output V 5 supply voltage CC OE 6 output enable input (active LOW) 7. Functional description Table 4. Function tab le[1] Operating modes Input Internal latch Output OE LE D Q Enable and read register (transparent L H L L L mode) L H H H H Latch and read register L L l L L L L h H H Latch register and disable outputs H X X X Z [1] H=HIGH voltage level; h =HIGH voltage level one setup time prior to the HIGH-to-LOW LE transition; L=LOW voltage level; l=LOW voltage level one setup time prior to the HIGH-to-LOW LE transition; X=Don’t care; Z=high-impedance OFF-state. 74AUP1G373 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved Product data sheet Rev. 6 — 4 July 2012 3 of 25

74AUP1G373 Nexperia Low-power D-type transparent latch; 3-state 8. Limiting values Table 5. Limiting valu es In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit V supply voltage 0.5 +4.6 V CC I input clamping current V <0V 50 - mA IK I V input voltage [1] 0.5 +4.6 V I I output clamping current V <0V 50 - mA OK O V output voltage Active mode and Power-down mode [1] 0.5 +4.6 V O I output current V =0 VtoV - 20 mA O O CC I supply current - 50 mA CC I ground current 50 - mA GND T storage temperature 65 +150 C stg P total power dissipation T =40 C to +125C [2] - 250 mW tot amb [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] For SC-88 packages: above 87.5C the value of Ptotderates linearly with 4.0mW/K. For XSON6 packages: above 118C the value of Ptotderates linearly with 7.8mW/K. 9. Recommended operating conditions Table 6. Recommend ed operating conditions Symbol Parameter Conditions Min Max Unit V supply voltage 0.8 3.6 V CC V input voltage 0 3.6 V I V output voltage Active mode 0 V V O CC Power-down mode; V =0V 0 3.6 V CC T ambient temperature 40 +125 C amb t/V input transition rise and fall rate V =0.8 V to3.6V - 200 ns/V CC 10. Static characteristics Table 7. Static charac teristics At recommended operating conditions; voltages are referenced to GND (ground=0V). Symbol Parameter Conditions Min Typ Max Unit T = 25 C amb V HIGH-level input voltage V = 0.8 V 0.70  V - - V IH CC CC V = 0.9 V to 1.95 V 0.65  V - - V CC CC V = 2.3 V to 2.7 V 1.6 - - V CC V = 3.0 V to 3.6 V 2.0 - - V CC V LOW-level input voltage V = 0.8 V - - 0.30  V V IL CC CC V = 0.9 V to 1.95 V - - 0.35  V V CC CC V = 2.3 V to 2.7 V - - 0.7 V CC V = 3.0 V to 3.6 V - - 0.9 V CC 74AUP1G373 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved Product data sheet Rev. 6 — 4 July 2012 4 of 25

74AUP1G373 Nexperia Low-power D-type transparent latch; 3-state Table 7. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground=0V). Symbol Parameter Conditions Min Typ Max Unit V HIGH-level output voltage V = V or V OH I IH IL I = 20 A; V = 0.8 V to 3.6 V V  0.1 - - V O CC CC I = 1.1 mA; V = 1.1 V 0.75  V - - V O CC CC I = 1.7 mA; V = 1.4 V 1.11 - - V O CC I = 1.9 mA; V = 1.65 V 1.32 - - V O CC I = 2.3 mA; V = 2.3 V 2.05 - - V O CC I = 3.1 mA; V = 2.3 V 1.9 - - V O CC I = 2.7 mA; V = 3.0 V 2.72 - - V O CC I = 4.0 mA; V = 3.0 V 2.6 - - V O CC V LOW-level output voltage V = V or V OL I IH IL I = 20 A; V = 0.8 V to 3.6 V - - 0.1 V O CC I = 1.1 mA; V = 1.1 V - - 0.3  V V O CC CC I = 1.7 mA; V = 1.4 V - - 0.31 V O CC I = 1.9 mA; V = 1.65 V - - 0.31 V O CC I = 2.3 mA; V = 2.3 V - - 0.31 V O CC I = 3.1 mA; V = 2.3 V - - 0.44 V O CC I = 2.7 mA; V = 3.0 V - - 0.31 V O CC I = 4.0 mA; V = 3.0 V - - 0.44 V O CC I input leakage current V = GND to 3.6 V; V = 0 V to 3.6 V - - 0.1 A I I CC I OFF-state output current V = V or V ; V = 0 V to 3.6V; - - 0.1 A OZ I IH IL O V = 0 V to 3.6 V CC I power-off leakage current V or V = 0 V to 3.6 V; V = 0 V - - 0.2 A OFF I O CC I additional power-off V or V = 0 V to 3.6V; - - 0.2 A OFF I O leakage current V =0Vto0.2 V CC I supply current V = GND or V ; I =0A; - - 0.5 A CC I CC O V =0.8V to 3.6 V CC I additional supply current V = V  0.6 V; I =0A; [1] - - 40 A CC I CC O V =3.3V CC C input capacitance V = 0 V to 3.6 V; V = GND or V - 0.8 - pF I CC I CC C output capacitance output enabled; V = GND; V = 0 V - 1.7 - pF O O CC output disabled; V = 0 V to 3.6 V; - 1.5 - pF CC V = GND or V O CC T = 40 C to +85C amb V HIGH-level input voltage V = 0.8 V 0.70  V - - V IH CC CC V = 0.9 V to 1.95 V 0.65  V - - V CC CC V = 2.3 V to 2.7 V 1.6 - - V CC V = 3.0 V to 3.6 V 2.0 - - V CC V LOW-level input voltage V = 0.8 V - - 0.30  V V IL CC CC V = 0.9 V to 1.95 V - - 0.35  V V CC CC V = 2.3 V to 2.7 V - - 0.7 V CC V = 3.0 V to 3.6 V - - 0.9 V CC 74AUP1G373 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved Product data sheet Rev. 6 — 4 July 2012 5 of 25

74AUP1G373 Nexperia Low-power D-type transparent latch; 3-state Table 7. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground=0V). Symbol Parameter Conditions Min Typ Max Unit V HIGH-level output voltage V = V or V OH I IH IL I = 20 A; V = 0.8 V to 3.6 V V  0.1 - - V O CC CC I = 1.1 mA; V = 1.1 V 0.7  V - - V O CC CC I = 1.7 mA; V = 1.4 V 1.03 - - V O CC I = 1.9 mA; V = 1.65 V 1.30 - - V O CC I = 2.3 mA; V = 2.3 V 1.97 - - V O CC I = 3.1 mA; V = 2.3 V 1.85 - - V O CC I = 2.7 mA; V = 3.0 V 2.67 - - V O CC I = 4.0 mA; V = 3.0 V 2.55 - - V O CC V LOW-level output voltage V = V or V OL I IH IL I = 20 A; V = 0.8 V to 3.6 V - - 0.1 V O CC I = 1.1 mA; V = 1.1 V - - 0.3  V V O CC CC I = 1.7 mA; V = 1.4 V - - 0.37 V O CC I = 1.9 mA; V = 1.65 V - - 0.35 V O CC I = 2.3 mA; V = 2.3 V - - 0.33 V O CC I = 3.1 mA; V = 2.3 V - - 0.45 V O CC I = 2.7 mA; V = 3.0 V - - 0.33 V O CC I = 4.0 mA; V = 3.0 V - - 0.45 V O CC I input leakage current V = GND to 3.6 V; V = 0 V to 3.6 V - - 0.5 A I I CC I OFF-state output current V = V or V ; V = 0 V to 3.6V; - - 0.5 A OZ I IH IL O V = 0 V to 3.6 V CC I power-off leakage current V or V = 0 V to 3.6 V; V = 0 V - - 0.5 A OFF I O CC I additional power-off V or V = 0 V to 3.6V; - - 0.6 A OFF I O leakage current V =0Vto0.2 V CC I supply current V = GND or V ; I =0A; - - 0.9 A CC I CC O V =0.8V to 3.6 V CC I additional supply current V = V  0.6 V; I =0A; [1] - - 50 A CC I CC O V =3.3V CC T = 40 C to +125C amb V HIGH-level input voltage V = 0.8 V 0.75  V - - V IH CC CC V = 0.9 V to 1.95 V 0.70  V - - V CC CC V = 2.3 V to 2.7 V 1.6 - - V CC V = 3.0 V to 3.6 V 2.0 - - V CC V LOW-level input voltage V = 0.8 V - - 0.25  V V IL CC CC V = 0.9 V to 1.95 V - - 0.30  V V CC CC V = 2.3 V to 2.7 V - - 0.7 V CC V = 3.0 V to 3.6 V - - 0.9 V CC 74AUP1G373 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved Product data sheet Rev. 6 — 4 July 2012 6 of 25

74AUP1G373 Nexperia Low-power D-type transparent latch; 3-state Table 7. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground=0V). Symbol Parameter Conditions Min Typ Max Unit V HIGH-level output voltage V = V or V OH I IH IL I = 20 A; V = 0.8 V to 3.6 V V  0.11 - - V O CC CC I = 1.1 mA; V = 1.1 V 0.6  V - - V O CC CC I = 1.7 mA; V = 1.4 V 0.93 - - V O CC I = 1.9 mA; V = 1.65 V 1.17 - - V O CC I = 2.3 mA; V = 2.3 V 1.77 - - V O CC I = 3.1 mA; V = 2.3 V 1.67 - - V O CC I = 2.7 mA; V = 3.0 V 2.40 - - V O CC I = 4.0 mA; V = 3.0 V 2.30 - - V O CC V LOW-level output voltage V = V or V OL I IH IL I = 20 A; V = 0.8 V to 3.6 V - - 0.11 V O CC I = 1.1 mA; V = 1.1 V - - 0.33  V V O CC CC I = 1.7 mA; V = 1.4 V - - 0.41 V O CC I = 1.9 mA; V = 1.65 V - - 0.39 V O CC I = 2.3 mA; V = 2.3 V - - 0.36 V O CC I = 3.1 mA; V = 2.3 V - - 0.50 V O CC I = 2.7 mA; V = 3.0 V - - 0.36 V O CC I = 4.0 mA; V = 3.0 V - - 0.50 V O CC I input leakage current V = GND to 3.6 V; V = 0 V to 3.6 V - - 0.75 A I I CC I OFF-state output current V = V or V ; V = 0 V to 3.6V; - - 0.75 A OZ I IH IL O V = 0 V to 3.6 V CC I power-off leakage current V or V = 0 V to 3.6 V; V = 0 V - - 0.75 A OFF I O CC I additional power-off V or V = 0 V to 3.6V; - - 0.75 A OFF I O leakage current V =0Vto0.2 V CC I supply current V = GND or V ; I =0A; - - 1.4 A CC I CC O V =0.8V to 3.6 V CC I additional supply current V = V  0.6 V; I =0A; [1] - - 75 A CC I CC O V =3.3V CC [1] One input at VCC  0.6 V, other input at VCC or GND. 74AUP1G373 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved Product data sheet Rev. 6 — 4 July 2012 7 of 25

74AUP1G373 Nexperia Low-power D-type transparent latch; 3-state 11. Dynamic characteristics Table 8. Dynamic cha racteristics Voltages are referenced to GND (ground=0V); for test circuit see Figure11. Symbol Parameter Conditions 25 C 40 C to +125 C Unit Min Typ[1] Max Min Max Min Max (85C) (85C) (125C) (125C) C = 5 pF L t propagation D to Q; see Figure7 [2] pd delay V = 0.8 V - 21.4 - - - - - ns CC V = 1.1 V to 1.3 V 2.8 6.6 13.5 2.6 13.8 2.6 15.2 ns CC V = 1.4 V to 1.6 V 2.4 4.6 7.8 2.1 8.3 2.1 9.1 ns CC V = 1.65 V to 1.95 V 1.9 3.7 6.2 1.6 6.7 1.6 7.3 ns CC V = 2.3 V to 2.7 V 1.8 2.9 4.1 1.5 4.5 1.5 4.9 ns CC V = 3.0 V to 3.6 V 1.5 2.5 3.5 1.2 4.0 1.2 4.5 ns CC LE to Q; see Figure8 [2] V = 0.8 V - 20.3 - - - - - ns CC V = 1.1 V to 1.3 V 2.7 6.2 13.6 2.5 14.0 2.5 15.4 ns CC V = 1.4 V to 1.6 V 2.3 4.4 7.6 2.0 8.5 2.0 9.3 ns CC V = 1.65 V to 1.95 V 1.8 3.5 5.8 1.5 6.7 1.5 7.3 ns CC V = 2.3 V to 2.7 V 1.5 2.6 4.0 1.3 4.4 1.3 4.8 ns CC V = 3.0 V to 3.6 V 1.3 2.2 3.3 1.1 3.8 1.1 4.2 ns CC t enable time OEtoQ; see Figure10 [3] en V = 0.8 V - 17.9 - - - - - ns CC V = 1.1 V to 1.3 V 3.2 5.1 9.2 3.0 9.2 3.0 10.1 ns CC V = 1.4 V to 1.6 V 2.6 3.8 5.8 2.4 6.1 2.4 6.7 ns CC V = 1.65 V to 1.95 V 2.2 3.3 4.8 2.0 5.0 2.0 5.5 ns CC V = 2.3 V to 2.7 V 2.0 2.7 3.8 1.8 4.0 1.8 4.4 ns CC V = 3.0 V to 3.6 V 1.9 2.5 3.4 1.8 3.6 1.8 4.0 ns CC t disable time OEtoQ; see Figure10 [4] dis V = 0.8 V - 9.4 - - - - - ns CC V = 1.1 V to 1.3 V 2.9 4.2 7.5 2.8 7.9 2.8 8.7 ns CC V = 1.4 V to 1.6 V 2.2 3.2 4.9 2.1 5.3 2.1 5.8 ns CC V = 1.65 V to 1.95 V 2.2 3.0 4.4 2.1 4.9 2.1 5.4 ns CC V = 2.3 V to 2.7 V 1.6 2.2 3.1 1.5 3.4 1.5 3.7 ns CC V = 3.0 V to 3.6 V 1.9 2.6 3.3 1.8 3.6 1.8 4.0 ns CC 74AUP1G373 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved Product data sheet Rev. 6 — 4 July 2012 8 of 25

74AUP1G373 Nexperia Low-power D-type transparent latch; 3-state Table 8. Dynamic characteristics …continued Voltages are referenced to GND (ground=0V); for test circuit see Figure11. Symbol Parameter Conditions 25 C 40 C to +125 C Unit Min Typ[1] Max Min Max Min Max (85C) (85C) (125C) (125C) C = 10 pF L t propagation D to Q; see Figure7 [2] pd delay V = 0.8 V - 24.4 - - - - - ns CC V = 1.1 V to 1.3 V 3.0 7.5 15.3 2.7 15.9 2.7 17.4 ns CC V = 1.4 V to 1.6 V 2.6 5.3 9.0 2.2 9.4 2.2 10.3 ns CC V = 1.65 V to 1.95 V 2.5 4.3 6.9 2.1 7.3 2.1 8.0 ns CC V = 2.3 V to 2.7 V 2.0 3.5 4.8 1.8 5.3 1.8 5.9 ns CC V = 3.0 V to 3.6 V 1.8 3.1 4.2 1.7 4.6 1.7 5.1 ns CC LE to Q; see Figure8 [2] V = 0.8 V - 23.3 - - - - - ns CC V = 1.1 V to 1.3 V 2.9 7.1 15.4 2.7 16.1 2.7 17.7 ns CC V = 1.4 V to 1.6 V 2.5 5.0 8.8 2.1 9.5 2.1 10.4 ns CC V = 1.65 V to 1.95 V 2.3 4.1 6.6 2.0 7.3 2.0 8.1 ns CC V = 2.3 V to 2.7 V 1.9 3.1 4.7 1.6 5.2 1.6 5.8 ns CC V = 3.0 V to 3.6 V 1.7 2.8 4.0 1.4 4.4 1.4 4.9 ns CC t enable time OEtoQ; see Figure10 [3] en V = 0.8 V - 21.2 - - - - - ns CC V = 1.1 V to 1.3 V 3.7 6.0 10.6 3.4 10.6 3.4 11.7 ns CC V = 1.4 V to 1.6 V 3.1 4.5 6.7 2.8 7.0 2.8 7.7 ns CC V = 1.65 V to 1.95 V 2.7 3.9 5.5 2.5 5.8 2.5 6.4 ns CC V = 2.3 V to 2.7 V 2.4 3.3 4.5 2.2 4.7 2.2 5.2 ns CC V = 3.0 V to 3.6 V 2.3 3.1 4.1 2.2 4.3 2.2 4.7 ns CC t disable time OEtoQ; see Figure10 [4] dis V = 0.8 V - 11.3 - - - - - ns CC V = 1.1 V to 1.3 V 3.9 5.3 8.7 3.8 9.2 3.8 10.1 ns CC V = 1.4 V to 1.6 V 3.0 4.1 5.8 2.9 6.2 2.9 6.8 ns CC V = 1.65 V to 1.95 V 3.2 4.2 5.7 3.1 6.0 3.1 6.6 ns CC V = 2.3 V to 2.7 V 2.3 3.0 4.0 2.2 4.3 2.2 4.7 ns CC V = 3.0 V to 3.6 V 3.0 3.8 4.7 2.9 5.0 2.9 5.5 ns CC 74AUP1G373 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved Product data sheet Rev. 6 — 4 July 2012 9 of 25

74AUP1G373 Nexperia Low-power D-type transparent latch; 3-state Table 8. Dynamic characteristics …continued Voltages are referenced to GND (ground=0V); for test circuit see Figure11. Symbol Parameter Conditions 25 C 40 C to +125 C Unit Min Typ[1] Max Min Max Min Max (85C) (85C) (125C) (125C) C = 15 pF L t propagation D to Q; see Figure7 [2] pd delay V = 0.8 V - 27.3 - - - - - ns CC V = 1.1 V to 1.3 V 3.5 8.3 16.9 3.2 17.5 3.2 19.2 ns CC V = 1.4 V to 1.6 V 3.1 5.9 9.6 2.7 10.5 2.7 11.6 ns CC V = 1.65 V to 1.95 V 2.6 4.8 7.6 2.2 8.5 2.2 9.3 ns CC V = 2.3 V to 2.7 V 2.5 3.9 5.5 2.2 5.9 2.2 6.5 ns CC V = 3.0 V to 3.6 V 2.2 3.6 4.9 1.8 5.5 1.8 6.0 ns CC LE to Q; see Figure8 [2] V = 0.8 V - 26.1 - - - - - ns CC V = 1.1 V to 1.3 V 3.3 7.9 17.3 3.0 18.0 3.0 19.8 ns CC V = 1.4 V to 1.6 V 3.0 5.6 9.7 2.5 10.7 2.5 11.8 ns CC V = 1.65 V to 1.95 V 2.5 4.6 7.4 2.2 8.3 2.2 9.1 ns CC V = 2.3 V to 2.7 V 2.3 3.6 5.3 2.0 5.9 2.0 6.4 ns CC V = 3.0 V to 3.6 V 2.1 3.2 4.6 1.8 5.1 1.8 5.6 ns CC t enable time OEtoQ; see Figure10 [3] en V = 0.8 V - 24.6 - - - - - ns CC V = 1.1 V to 1.3 V 4.1 6.8 12.1 3.8 12.1 3.8 13.3 ns CC V = 1.4 V to 1.6 V 3.5 5.1 7.5 3.2 7.9 3.2 8.7 ns CC V = 1.65 V to 1.95 V 3.1 4.4 6.1 2.8 6.5 2.8 7.2 ns CC V = 2.3 V to 2.7 V 2.8 3.7 5.0 2.5 5.3 2.5 5.8 ns CC V = 3.0 V to 3.6 V 2.6 3.5 4.7 2.5 4.9 2.5 5.4 ns CC t disable time OEtoQ; see Figure10 [4] dis V = 0.8 V - 13.1 - - - - - ns CC V = 1.1 V to 1.3 V 4.9 6.5 9.8 4.8 10.4 4.8 11.4 ns CC V = 1.4 V to 1.6 V 3.9 5.0 6.8 3.8 7.3 3.8 8.0 ns CC V = 1.65 V to 1.95 V 4.2 5.3 6.9 4.1 7.3 4.1 8.0 ns CC V = 2.3 V to 2.7 V 3.0 3.8 4.8 2.9 5.1 2.9 5.6 ns CC V = 3.0 V to 3.6 V 4.1 5.0 6.1 4.0 6.4 4.0 7.0 ns CC 74AUP1G373 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved Product data sheet Rev. 6 — 4 July 2012 10 of 25

74AUP1G373 Nexperia Low-power D-type transparent latch; 3-state Table 8. Dynamic characteristics …continued Voltages are referenced to GND (ground=0V); for test circuit see Figure11. Symbol Parameter Conditions 25 C 40 C to +125 C Unit Min Typ[1] Max Min Max Min Max (85C) (85C) (125C) (125C) C = 30 pF L t propagation D to Q; see Figure7 [2] pd delay V = 0.8 V - 35.9 - - - - - ns CC V = 1.1 V to 1.3 V 4.0 10.6 22.1 3.7 23.3 3.7 25.6 ns CC V = 1.4 V to 1.6 V 3.6 7.5 12.3 3.5 13.6 3.5 15.0 ns CC V = 1.65 V to 1.95 V 3.5 6.2 9.5 3.2 10.5 3.2 11.5 ns CC V = 2.3 V to 2.7 V 3.3 5.1 6.9 2.9 7.6 2.9 8.3 ns CC V = 3.0 V to 3.6 V 3.0 4.7 6.4 2.9 7.2 2.9 7.9 ns CC LE to Q; see Figure8 [2] V = 0.8 V - 34.8 - - - - - ns CC V = 1.1 V to 1.3 V 3.9 10.2 22.2 3.7 23.5 3.7 25.9 ns CC V = 1.4 V to 1.6 V 3.5 7.2 12.4 3.4 13.7 3.4 15.1 ns CC V = 1.65 V to 1.95 V 3.3 5.9 9.5 3.0 10.5 3.0 11.6 ns CC V = 2.3 V to 2.7 V 3.1 4.8 6.8 2.7 7.5 2.7 8.2 ns CC V = 3.0 V to 3.6 V 2.9 4.4 6.1 2.6 7.0 2.6 7.7 ns CC t enable time OEtoQ; see Figure10 [3] en V = 0.8 V - 34.5 - - - - - ns CC V = 1.1 V to 1.3 V 5.5 9.1 16.2 4.9 16.2 4.9 17.8 ns CC V = 1.4 V to 1.6 V 4.6 6.7 9.9 4.2 10.5 4.2 11.6 ns CC V = 1.65 V to 1.95 V 4.2 5.7 7.9 3.7 8.6 3.7 9.5 ns CC V = 2.3 V to 2.7 V 3.6 4.9 6.4 3.4 6.9 3.4 7.6 ns CC V = 3.0 V to 3.6 V 3.4 4.7 6.1 3.3 6.5 3.3 7.2 ns CC t disable time OEtoQ; see Figure10 [4] dis V = 0.8 V - 19.2 - - - - - ns CC V = 1.1 V to 1.3 V 8.0 9.9 13.7 7.9 14.5 7.9 16.0 ns CC V = 1.4 V to 1.6 V 6.3 7.7 9.7 6.2 10.5 6.2 11.6 ns CC V = 1.65 V to 1.95 V 7.3 8.7 10.6 7.2 11.3 7.2 12.4 ns CC V = 2.3 V to 2.7 V 5.2 6.2 7.5 5.1 7.8 5.1 8.6 ns CC V = 3.0 V to 3.6 V 7.5 8.8 10.2 7.4 10.5 7.4 11.6 ns CC C = 5 pF, 10 pF, 15 pF and 30 pF L t pulse width LE HIGH; see Figure8 W V = 0.8 V - 4.0 - - - - - ns CC V = 1.1 V to 1.3 V - 0.7 - 2.1 - 2.1 - ns CC V = 1.4 V to 1.6 V - 0.5 - 1.3 - 1.3 - ns CC V = 1.65 V to 1.95 V - 0.4 - 1.0 - 1.0 - ns CC V = 2.3 V to 2.7 V - 0.3 - 0.8 - 0.8 - ns CC V = 3.0 V to 3.6 V - 0.2 - 0.8 - 0.8 - ns CC 74AUP1G373 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved Product data sheet Rev. 6 — 4 July 2012 11 of 25

74AUP1G373 Nexperia Low-power D-type transparent latch; 3-state Table 8. Dynamic characteristics …continued Voltages are referenced to GND (ground=0V); for test circuit see Figure11. Symbol Parameter Conditions 25 C 40 C to +125 C Unit Min Typ[1] Max Min Max Min Max (85C) (85C) (125C) (125C) t set-up time DtoLE; seeF igure9 su(H) HIGH V = 0.8 V - 4.6 - - - - - ns CC V = 1.1 V to 1.3 V - 0.9 - 2.2 - 2.2 - ns CC V = 1.4 V to 1.6 V - 0.6 - 1.4 - 1.4 - ns CC V = 1.65 V to 1.95 V - 0.4 - 1.0 - 1.0 - ns CC V = 2.3 V to 2.7 V - 0 - 0.6 - 0.6 - ns CC V = 3.0 V to 3.6 V - 0.1 - 0.4 - 0.4 - ns CC t set-up time DtoLE; seeF igure9 su(L) LOW V = 0.8 V - 4.0 - - - - - ns CC V = 1.1 V to 1.3 V - 1.2 - 2.7 - 2.7 - ns CC V = 1.4 V to 1.6 V - 0.7 - 1.5 - 1.5 - ns CC V = 1.65 V to 1.95 V - 0.6 - 1.2 - 1.2 - ns CC V = 2.3 V to 2.7 V - 0.4 - 0.9 - 0.9 - ns CC V = 3.0 V to 3.6 V - 0.3 - 0.7 - 0.7 - ns CC t hold time D to LE HIGH or LOW; h seeFigure9 V = 0.8 V - 4.6 - - - - - ns CC V = 1.1 V to 1.3 V - 0.9 - 0.1 - 0.1 - ns CC V = 1.4 V to 1.6 V - 0.6 - 0.1 - 0.1 - ns CC V = 1.65 V to 1.95 V - 0.4 - 0 - 0 - ns CC V = 2.3 V to 2.7 V - 0.2 - 0.2 - 0.2 - ns CC V = 3.0 V to 3.6 V - 0.1 - 0.3 - 0.3 - ns CC 74AUP1G373 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved Product data sheet Rev. 6 — 4 July 2012 12 of 25

74AUP1G373 Nexperia Low-power D-type transparent latch; 3-state Table 8. Dynamic characteristics …continued Voltages are referenced to GND (ground=0V); for test circuit see Figure11. Symbol Parameter Conditions 25 C 40 C to +125 C Unit Min Typ[1] Max Min Max Min Max (85C) (85C) (125C) (125C) C power f = 1 MHz; V =GNDto V [5][6] PD i I CC dissipation output enabled capacitance V = 0.8 V - 2.0 - - - - - pF CC V = 1.1 V to 1.3 V - 2.0 - - - - - pF CC V = 1.4 V to 1.6 V - 2.0 - - - - - pF CC V = 1.65 V to 1.95 V - 2.1 - - - - - pF CC V = 2.3 V to 2.7 V - 2.4 - - - - - pF CC V = 3.0 V to 3.6 V - 2.8 - - - - - pF CC [1] All typical values are measured at nominal V . CC [2] t is the same as t and t . pd PLH PHL [3] t is the same as t and t . en PZH PZL [4] t is the same as t and t . dis PHZ PLZ [5] All specified values are the average typical values over all stated loads. [6] CPD is used to determine the dynamic power dissipation (PD in W). PD=CPDVCC2fiN+(CLVCC2fo) where: f =input frequency in MHz; i f =output frequency in MHz; o C =output load capacitance in pF; L V =supply voltage in V; CC (CLVCC2fo)=sum of the outputs; N=number of inputs switching. 12. Waveforms VI D input VM GND tPHL tPLH VOH Q output VM VOL 001aae253 Measurement points are given in Table9. Logic levels: V and V are typical output voltage levels that occur with the output load. OL OH Fig 7. The data input (D) to output (Q) propagation delays 74AUP1G373 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved Product data sheet Rev. 6 — 4 July 2012 13 of 25

74AUP1G373 Nexperia Low-power D-type transparent latch; 3-state VI LE input VM GND tW tPHL tPLH VOH Q output VM VOL 001aae254 Measurement points are given in Table9. Logic levels: V and V are typical output voltage levels that occur with the output load. OL OH Fig 8. The latch enable input (LE) to output (Q) propagation delays, the latch enable input (LE) pulse width VI D input VM GND th th tsu tsu VI LE input VM GND 001aae255 Measurement points are given in Table9. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. Fig 9. Data set-up and hold times for the D input to the LEinput Table 9. Measuremen t points Supply voltage Output Input V V V V t = t CC M M I r f 0.8 V to 3.6 V 0.5  V 0.5  V V  3.0 ns CC CC CC 74AUP1G373 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved Product data sheet Rev. 6 — 4 July 2012 14 of 25

74AUP1G373 Nexperia Low-power D-type transparent latch; 3-state VI OE input VM GND tPLZ tPZL VCC output LOW-to-OFF VM OFF-to-LOW VOL VX tPHZ tPZH VOH VY output HIGH-to-OFF VM OFF-to-HIGH GND outputs outputs outputs enabled disabled enabled mna644 Measurement points are given in Table10. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. Fig 10. Turn-on and turn-off times Table 10. Measuremen t points Supply voltage Input Output V V V V V CC M M X Y 0.8 V to 1.6 V 0.5  V 0.5  V V +0.1V V 0.1V CC CC OL OH 1.65 V to 2.7 V 0.5  V 0.5  V V +0.15V V 0.15V CC CC OL OH 3.0 V to 3.6 V 0.5  V 0.5  V V +0.3V V 0.3V CC CC OL OH 74AUP1G373 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved Product data sheet Rev. 6 — 4 July 2012 15 of 25

74AUP1G373 Nexperia Low-power D-type transparent latch; 3-state VCC VEXT 5 kΩ VI VO G DUT RT CL RL 001aac521 Test data is given in Table11. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. R = Termination resistance should be equal to the output impedance Z of the pulse generator. T o VEXT = External voltage for measuring switching times. Fig 11. Test circuit for measuring switching times Table 11. Test data Supply voltage Load V EXT V C R [1] t , t t , t t , t CC L L PLH PHL PZH PHZ PZL PLZ 0.8 V to 3.6 V 5 pF, 10 pF, 15pF and 30 pF 5 k or 1 M open GND 2  V CC [1] For measuring enable and disable times RL = 5 k, for measuring propagation delays, setup and hold times and pulse width RL = 1 M. 74AUP1G373 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved Product data sheet Rev. 6 — 4 July 2012 16 of 25

74AUP1G373 Nexperia Low-power D-type transparent latch; 3-state 13. Package outline Plastic surface-mounted package; 6 leads SOT363 D B E A X y HE v M A 6 5 4 Q pin 1 index A A1 1 2 3 c e1 bp w M B Lp e detail X 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) A1 UNIT A max bp c D E e e1 HE Lp Q v w y 1.1 0.30 0.25 2.2 1.35 2.2 0.45 0.25 mm 0.1 1.3 0.65 0.2 0.2 0.1 0.8 0.20 0.10 1.8 1.15 2.0 0.15 0.15 OUTLINE REFERENCES EUROPEAN ISSUE DATE VERSION IEC JEDEC JEITA PROJECTION 04-11-08 SOT363 SC-88 06-03-16 Fig 12. Package outline SOT363 (SC-88) 74AUP1G373 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved Product data sheet Rev. 6 — 4 July 2012 17 of 25

74AUP1G373 Nexperia Low-power D-type transparent latch; 3-state XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm SOT886 b 1 2 3 4x L1 L (2) e 6 5 4 e1 e1 6x A (2) A1 D E terminal 1 index area 0 1 2 mm scale Dimensions (mm are the original dimensions) Unit A(1) A1 b D E e e1 L L1 max 0.5 0.04 0.25 1.50 1.05 0.35 0.40 mm nom 0.20 1.45 1.00 0.6 0.5 0.30 0.35 min 0.17 1.40 0.95 0.27 0.32 Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. sot886_po Outline References European Issue date version IEC JEDEC JEITA projection 04-07-22 SOT886 MO-252 12-01-05 Fig 13. Package outline SOT886 (XSON6) 74AUP1G373 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved Product data sheet Rev. 6 — 4 July 2012 18 of 25

74AUP1G373 Nexperia Low-power D-type transparent latch; 3-state XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1 x 0.5 mm SOT891 b 1 2 3 4× (1) L L1 e 6 5 4 e1 e1 6× A (1) A1 D E terminal 1 index area 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT mAax mAa1x b D E e e1 L L1 0.20 1.05 1.05 0.35 0.40 mm 0.5 0.04 0.55 0.35 0.12 0.95 0.95 0.27 0.32 Note 1. Can be visible in some manufacturing processes. OUTLINE REFERENCES EUROPEAN ISSUE DATE VERSION IEC JEDEC JEITA PROJECTION 05-04-06 SOT891 07-05-15 Fig 14. Package outline SOT891 (XSON6) 74AUP1G373 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved Product data sheet Rev. 6 — 4 July 2012 19 of 25

74AUP1G373 Nexperia Low-power D-type transparent latch; 3-state XSON6: extremely thin small outline package; no leads; 6 terminals; body 0.9 x 1.0 x 0.35 mm SOT1115 b 1 2 3 (4×)(2) L1 L e 6 5 4 e1 e1 (6×)(2) A1 A D E terminal 1 index area 0 0.5 1 mm scale Dimensions Unit A(1) A1 b D E e e1 L L1 max 0.35 0.04 0.20 0.95 1.05 0.35 0.40 mm nom 0.15 0.90 1.00 0.55 0.3 0.30 0.35 min 0.12 0.85 0.95 0.27 0.32 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. sot1115_po Outline References European Issue date version IEC JEDEC JEITA projection 10-04-02 SOT1115 10-04-07 Fig 15. Package outline SOT1115 (XSON6) 74AUP1G373 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved Product data sheet Rev. 6 — 4 July 2012 20 of 25

74AUP1G373 Nexperia Low-power D-type transparent latch; 3-state XSON6: extremely thin small outline package; no leads; 6 terminals; body 1.0 x 1.0 x 0.35 mm SOT1202 b 1 2 3 (4×)(2) L1 L e 6 5 4 e1 e1 (6×)(2) A1 A D E terminal 1 index area 0 0.5 1 mm scale Dimensions Unit A(1) A1 b D E e e1 L L1 max 0.35 0.04 0.20 1.05 1.05 0.35 0.40 mm nom 0.15 1.00 1.00 0.55 0.35 0.30 0.35 min 0.12 0.95 0.95 0.27 0.32 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. sot1202_po Outline References European Issue date version IEC JEDEC JEITA projection 10-04-02 SOT1202 10-04-06 Fig 16. Package outline SOT1202 (XSON6) 74AUP1G373 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved Product data sheet Rev. 6 — 4 July 2012 21 of 25

74AUP1G373 Nexperia Low-power D-type transparent latch; 3-state 14. Abbreviations Table 12. Abbreviation s Acronym Description CDM Charged Device Model DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model 15. Revision history T able 13. Revision history Document ID Release date Data sheet status Change notice Supersedes 74AUP1G373 v.6 20120704 Product data sheet - 74AUP1G373 v.5 Modifications: • Package outline drawing of SOT886 (Figure13) modified. 74AUP1G373 v.5 20111125 Product data sheet - 74AUP1G373 v.4 Modifications: • Legal pages updated. 74AUP1G373 v.4 20100715 Product data sheet - 74AUP1G373 v.3 74AUP1G373 v.3 20080109 Product data sheet - 74AUP1G373 v.2 74AUP1G373 v.2 20070720 Product data sheet - 74AUP1G373 v.1 74AUP1G373 v.1 20061129 Product data sheet - - 74AUP1G373 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved Product data sheet Rev. 6 — 4 July 2012 22 of 25

74AUP1G373 Nexperia Low-power D-type transparent latch; 3-state 16. Legal information 16.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. 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Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in In no event shall Nexperia be liable for any indirect, incidental, the Recommended operating conditions section (if present) or the punitive, special or consequential damages (including - without limitation - lost Characteristics sections of this document is not warranted. Constant or profits, lost savings, business interruption, costs related to the removal or repeated exposure to limiting values will permanently and irreversibly affect replacement of any products or rework charges) whether or not such the quality and reliability of the device. damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Terms and conditions of commercial sale — Nexperia products are sold subject to the general terms and conditions of commercial Notwithstanding any damages that customer might incur for any reason whatsoever, Nexperia’s aggregate and cumulative liability towards sale, as published at http://www.nexperia.com/profile/terms, unless otherwise customer for the products described herein shall be limited in accordance agreed in a valid written individual agreement. In case an individual with the Terms and conditions of commercial sale of Nexperia. agreement is concluded only the terms and conditions of the respective agreement shall apply. Nexperia hereby expressly objects to Right to make changes — Nexperia reserves the right to make applying the customer’s general terms and conditions with regard to the changes to information published in this document, including without purchase of Nexperia products by customer. limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior No offer to sell or license — Nothing in this document may be interpreted or to the publication hereof. construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 74AUP1G373 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved Product data sheet Rev. 6 — 4 July 2012 23 of 25

74AUP1G373 Nexperia Low-power D-type transparent latch; 3-state Export control — This document as well as the item(s) described herein Nexperia’s specifications such use shall be solely at customer’s may be subject to export control regulations. Export might require a prior own risk, and (c) customer fully indemnifies Nexperia for any authorization from competent authorities. liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond Nexperia’s Non-automotive qualified products — Unless this data sheet expressly standard warranty and Nexperia’s product specifications. states that this specific Nexperia product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested Translations — A non-English (translated) version of a document is for in accordance with automotive testing or application requirements. Nexperia reference only. The English version shall prevail in case of any discrepancy accepts no liability for inclusion and/or use of between the translated and English versions. non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in 16.4 Trademarks automotive applications to automotive specifications and standards, customer (a) shall use the product without Nexperia’s warranty of the Notice: All referenced brands, product names, service names and trademarks product for such automotive applications, use and specifications, and (b) are the property of their respective owners. whenever customer uses the product for automotive applications beyond 17. Contact information For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com 74AUP1G373 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved Product data sheet Rev. 6 — 4 July 2012 24 of 25

74AUP1G373 Nexperia Low-power D-type transparent latch; 3-state 18. Contents 1 General description. . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2 4 Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 Functional description . . . . . . . . . . . . . . . . . . . 3 8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 9 Recommended operating conditions. . . . . . . . 4 10 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4 11 Dynamic characteristics. . . . . . . . . . . . . . . . . . 8 12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 13 Package outline. . . . . . . . . . . . . . . . . . . . . . . . 17 14 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 22 15 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 22 16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 23 16.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 23 16.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 16.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 23 16.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 24 17 Contact information. . . . . . . . . . . . . . . . . . . . . 24 18 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 © Nexperia B.V. 2017. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 04 July 2012