74AUP1G32-Q100 Low-power 2-input OR-gate Rev. 3 — 28 January 2019 Product data sheet 1. General description The 74AUP1G32-Q100 provides the single 2-input OR function. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire V range from 0.8 V to 3.6 V. CC This device ensures a very low static and dynamic power consumption across the entire V range CC from 0.8 V to 3.6 V. This device is fully specified for partial power-down applications using I . The I circuitry OFF OFF disables the output, preventing the damaging backflow current through the device when it is powered down. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits • Automotive product qualification in accordance with AEC-Q100 (Grade 1) • Specified from -40 °C to +85 °C and from -40 °C to +125 °C • Wide supply voltage range from 0.8 V to 3.6 V • High noise immunity • Complies with JEDEC standards: • JESD8-12 (0.8 V to 1.3 V) • JESD8-11 (0.9 V to 1.65 V) • JESD8-7 (1.2 V to 1.95 V) • JESD8-5 (1.8 V to 2.7 V) • JESD8-B (2.7 V to 3.6 V) • ESD protection: • MIL-STD-883, method 3015 Class 3A. Exceeds 5000 V • HBM JESD22-A114F Class 3A. Exceeds 5000 V • MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω) • Low static power consumption; I = 0.9 µA (maximum) CC • Latch-up performance exceeds 100 mA per JESD 78 Class II • Inputs accept voltages up to 3.6 V • Low noise overshoot and undershoot < 10 % of V CC • I circuitry provides partial power-down mode operation OFF 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AUP1G32GW-Q100 -40 °C to +125 °C TSSOP5 plastic thin shrink small outline package; 5 leads; SOT353-1 body width 1.25 mm 74AUP1G32GM-Q100 -40 °C to +125 °C XSON6 plastic extremely thin small outline package; SOT886 no leads; 6 terminals; body 1 × 1.45 × 0.5 mm

Nexperia 74AUP1G32-Q100 Low-power 2-input OR-gate 4. Marking Table 2. Marking Type number Marking code [1] 74AUP1G32GW-Q100 pG 74AUP1G32GM-Q100 pG [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram Fig. 1. B 1 B 1 Y 4 ≥1 4 Y 2 A 2 A mna164 mna165 mna166 Fig. 2. Logic symbol Fig. 3. IEC logic symbol Fig. 4. Logic diagram 6. Pinning information 6.1. Pinning 74AUP1G32 74AUP1G32 B 1 6 VCC B 1 5 VCC A 2 5 n.c. A 2 GND 3 4 Y GND 3 4 Y 001aaf029 001aaf028 Transparent top view Fig. 5. Pin configuration SOT353-1 (TSSOP5) Fig. 6. Pin configuration SOT886 (XSON6) 6.2. Pin description Table 3. Pin description Symbol Pin Description TSSOP5 XSON6 B 1 1 data input A 2 2 data input GND 3 3 ground (0 V) Y 4 4 data output n.c. - 5 not connected V 5 6 supply voltage CC 74AUP1G32_Q100 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2019. All rights reserved Product data sheet Rev. 3 — 28 January 2019 2 / 14

Nexperia 74AUP1G32-Q100 Low-power 2-input OR-gate 7. Functional description Table 4. Function table H = HIGH voltage level; L = LOW voltage level. Input Output A B Y L L L L H H H L H H H H 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit V supply voltage -0.5 +4.6 V CC I input clamping current V < 0 V -50 - mA IK I V input voltage [1] -0.5 +4.6 V I I output clamping current V < 0 V -50 - mA OK O V output voltage Active mode and Power-down mode [1] -0.5 +4.6 V O I output current V = 0 V to V - ±20 mA O O CC I supply current - +50 mA CC I ground current -50 - mA GND T storage temperature -65 +150 °C stg P total power dissipation T = -40 °C to +125 °C [2] - 250 mW tot amb [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] For TSSOP5 packages: above 87.5 °C the value of Ptot derates linearly with 4.0 mW/K. For XSON6 packages: above 118 °C the value of Ptot derates linearly with 7.8 mW/K. 9. Recommended operating conditions Table 6. Recommended operating conditions Symbol Parameter Conditions Min Max Unit V supply voltage 0.8 3.6 V CC V input voltage 0 3.6 V I V output voltage Active mode 0 V V O CC Power-down mode; V = 0 V 0 3.6 V CC T ambient temperature -40 +125 °C amb Δt/ΔV input transition rise and fall rate V = 0.8 V to 3.6 V 0 200 ns/V CC 74AUP1G32_Q100 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2019. All rights reserved Product data sheet Rev. 3 — 28 January 2019 3 / 14

Nexperia 74AUP1G32-Q100 Low-power 2-input OR-gate 10. Static characteristics Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit T = 25 °C amb V HIGH-level input V = 0.8 V 0.70 × V - - V IH CC CC voltage V = 0.9 V to 1.95 V 0.65 × V - - V CC CC V = 2.3 V to 2.7 V 1.6 - - V CC V = 3.0 V to 3.6 V 2.0 - - V CC V LOW-level input V = 0.8 V - - 0.30 × V V IL CC CC voltage V = 0.9 V to 1.95 V - - 0.35 × V V CC CC V = 2.3 V to 2.7 V - - 0.7 V CC V = 3.0 V to 3.6 V - - 0.9 V CC V HIGH-level output V = V or V OH I IH IL voltage I = -20 μA; V = 0.8 V to 3.6 V V - 0.1 - - V O CC CC I = -1.1 mA; V = 1.1 V 0.75 × V - - V O CC CC I = -1.7 mA; V = 1.4 V 1.11 - - V O CC I = -1.9 mA; V = 1.65 V 1.32 - - V O CC I = -2.3 mA; V = 2.3 V 2.05 - - V O CC I = -3.1 mA; V = 2.3 V 1.9 - - V O CC I = -2.7 mA; V = 3.0 V 2.72 - - V O CC I = -4.0 mA; V = 3.0 V 2.6 - - V O CC V LOW-level output V = V or V OL I IH IL voltage I = 20 μA; V = 0.8 V to 3.6 V - - 0.1 V O CC I = 1.1 mA; V = 1.1 V - - 0.3 × V V O CC CC I = 1.7 mA; V = 1.4 V - - 0.31 V O CC I = 1.9 mA; V = 1.65 V - - 0.31 V O CC I = 2.3 mA; V = 2.3 V - - 0.31 V O CC I = 3.1 mA; V = 2.3 V - - 0.44 V O CC I = 2.7 mA; V = 3.0 V - - 0.31 V O CC I = 4.0 mA; V = 3.0 V - - 0.44 V O CC I input leakage current V = GND to 3.6 V; V = 0 V to 3.6 V - - ±0.1 μA I I CC I power-off leakage V or V = 0 V to 3.6 V; V = 0 V - - ±0.2 μA OFF I O CC current ΔI additional power-off V or V = 0 V to 3.6 V; - - ±0.2 μA OFF I O leakage current V = 0 V to 0.2 V CC I supply current V = GND or V ; I = 0 A; - - 0.5 μA CC I CC O V = 0.8 V to 3.6 V CC ΔI additional supply V = V - 0.6 V; I = 0 A; V = 3.3 V [1] - - 40 μA CC I CC O CC current C input capacitance V = 0 V to 3.6 V; V = GND or V - 0.8 - pF I CC I CC C output capacitance V = GND; V = 0 V - 1.7 - pF O O CC 74AUP1G32_Q100 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2019. All rights reserved Product data sheet Rev. 3 — 28 January 2019 4 / 14

Nexperia 74AUP1G32-Q100 Low-power 2-input OR-gate Symbol Parameter Conditions Min Typ Max Unit T = -40 °C to +85 °C amb V HIGH-level input V = 0.8 V 0.70 × V - - V IH CC CC voltage V = 0.9 V to 1.95 V 0.65 × V - - V CC CC V = 2.3 V to 2.7 V 1.6 - - V CC V = 3.0 V to 3.6 V 2.0 - - V CC V LOW-level input V = 0.8 V - - 0.30 × V V IL CC CC voltage V = 0.9 V to 1.95 V - - 0.35 × V V CC CC V = 2.3 V to 2.7 V - - 0.7 V CC V = 3.0 V to 3.6 V - - 0.9 V CC V HIGH-level output V = V or V OH I IH IL voltage I = -20 μA; V = 0.8 V to 3.6 V V - 0.1 - - V O CC CC I = -1.1 mA; V = 1.1 V 0.7 × V - - V O CC CC I = -1.7 mA; V = 1.4 V 1.03 - - V O CC I = -1.9 mA; V = 1.65 V 1.30 - - V O CC I = -2.3 mA; V = 2.3 V 1.97 - - V O CC I = -3.1 mA; V = 2.3 V 1.85 - - V O CC I = -2.7 mA; V = 3.0 V 2.67 - - V O CC I = -4.0 mA; V = 3.0 V 2.55 - - V O CC V LOW-level output V = V or V OL I IH IL voltage I = 20 μA; V = 0.8 V to 3.6 V - - 0.1 V O CC I = 1.1 mA; V = 1.1 V - - 0.3 × V V O CC CC I = 1.7 mA; V = 1.4 V - - 0.37 V O CC I = 1.9 mA; V = 1.65 V - - 0.35 V O CC I = 2.3 mA; V = 2.3 V - - 0.33 V O CC I = 3.1 mA; V = 2.3 V - - 0.45 V O CC I = 2.7 mA; V = 3.0 V - - 0.33 V O CC I = 4.0 mA; V = 3.0 V - - 0.45 V O CC I input leakage current V = GND to 3.6 V; V = 0 V to 3.6 V - - ±0.5 μA I I CC I power-off leakage V or V = 0 V to 3.6 V; V = 0 V - - ±0.5 μA OFF I O CC current ΔI additional power-off V or V = 0 V to 3.6 V; - - ±0.6 μA OFF I O leakage current V = 0 V to 0.2 V CC I supply current V = GND or V ; I = 0 A; - - 0.9 μA CC I CC O V = 0.8 V to 3.6 V CC ΔI additional supply V = V - 0.6 V; I = 0 A; V = 3.3 V [1] - - 50 μA CC I CC O CC current T = -40 °C to +125 °C amb V HIGH-level input V = 0.8 V 0.75 × V - - V IH CC CC voltage V = 0.9 V to 1.95 V 0.70 × V - - V CC CC V = 2.3 V to 2.7 V 1.6 - - V CC V = 3.0 V to 3.6 V 2.0 - - V CC V LOW-level input V = 0.8 V - - 0.25 × V V IL CC CC voltage V = 0.9 V to 1.95 V - - 0.30 × V V CC CC V = 2.3 V to 2.7 V - - 0.7 V CC V = 3.0 V to 3.6 V - - 0.9 V CC 74AUP1G32_Q100 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2019. All rights reserved Product data sheet Rev. 3 — 28 January 2019 5 / 14

Nexperia 74AUP1G32-Q100 Low-power 2-input OR-gate Symbol Parameter Conditions Min Typ Max Unit V HIGH-level output V = V or V OH I IH IL voltage I = -20 μA; V = 0.8 V to 3.6 V V - 0.11 - - V O CC CC I = -1.1 mA; V = 1.1 V 0.6 × V - - V O CC CC I = -1.7 mA; V = 1.4 V 0.93 - - V O CC I = -1.9 mA; V = 1.65 V 1.17 - - V O CC I = -2.3 mA; V = 2.3 V 1.77 - - V O CC I = -3.1 mA; V = 2.3 V 1.67 - - V O CC I = -2.7 mA; V = 3.0 V 2.40 - - V O CC I = -4.0 mA; V = 3.0 V 2.30 - - V O CC V LOW-level output V = V or V OL I IH IL voltage I = 20 μA; V = 0.8 V to 3.6 V - - 0.11 V O CC I = 1.1 mA; V = 1.1 V - - 0.33 × V V O CC CC I = 1.7 mA; V = 1.4 V - - 0.41 V O CC I = 1.9 mA; V = 1.65 V - - 0.39 V O CC I = 2.3 mA; V = 2.3 V - - 0.36 V O CC I = 3.1 mA; V = 2.3 V - - 0.50 V O CC I = 2.7 mA; V = 3.0 V - - 0.36 V O CC I = 4.0 mA; V = 3.0 V - - 0.50 V O CC I input leakage current V = GND to 3.6 V; V = 0 V to 3.6 V - - ±0.75 μA I I CC I power-off leakage V or V = 0 V to 3.6 V; V = 0 V - - ±0.75 μA OFF I O CC current ΔI additional power-off V or V = 0 V to 3.6 V; - - ±0.75 μA OFF I O leakage current V = 0 V to 0.2 V CC I supply current V = GND or V ; I = 0 A; - - 1.4 μA CC I CC O V = 0.8 V to 3.6 V CC ΔI additional supply V = V - 0.6 V; I = 0 A; V = 3.3 V [1] - - 75 μA CC I CC O CC current [1] One input at VCC - 0.6 V, other input at VCC or GND. 11. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 8 Symbol Parameter Conditions Min Typ [1] Max Unit T = 25 °C; C = 5 pF amb L t propagation delay A, B to Y; see Fig. 7 [2] pd V = 0.8 V - 16.8 - ns CC V = 1.1 V to 1.3 V 2.4 5.1 10.9 ns CC V = 1.4 V to 1.6 V 1.6 3.6 6.6 ns CC V = 1.65 V to 1.95 V 1.4 3.0 5.2 ns CC V = 2.3 V to 2.7 V 1.1 2.4 3.9 ns CC V = 3.0 V to 3.6 V 1.0 2.1 3.5 ns CC 74AUP1G32_Q100 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2019. All rights reserved Product data sheet Rev. 3 — 28 January 2019 6 / 14

Nexperia 74AUP1G32-Q100 Low-power 2-input OR-gate Symbol Parameter Conditions Min Typ [1] Max Unit T = 25 °C; C = 10 pF amb L t propagation delay A, B to Y; see Fig. 7 [2] pd V = 0.8 V - 20.3 - ns CC V = 1.1 V to 1.3 V 2.3 5.9 12.7 ns CC V = 1.4 V to 1.6 V 1.9 4.2 7.7 ns CC V = 1.65 V to 1.95 V 1.7 3.5 6.0 ns CC V = 2.3 V to 2.7 V 1.4 2.9 4.6 ns CC V = 3.0 V to 3.6 V 1.3 2.7 4.3 ns CC T = 25 °C; C = 15 pF amb L t propagation delay A, B to Y; see Fig. 7 [2] pd V = 0.8 V - 23.8 - ns CC V = 1.1 V to 1.3 V 3.3 6.7 14.3 ns CC V = 1.4 V to 1.6 V 2.3 4.8 8.6 ns CC V = 1.65 V to 1.95 V 2.0 4.0 6.7 ns CC V = 2.3 V to 2.7 V 1.7 3.3 5.3 ns CC V = 3.0 V to 3.6 V 1.5 3.1 4.9 ns CC T = 25 °C; C = 30 pF amb L t propagation delay A, B to Y; see Fig. 7 [2] pd V = 0.8 V - 34.1 - ns CC V = 1.1 V to 1.3 V 4.5 9.0 19.1 ns CC V = 1.4 V to 1.6 V 3.4 6.3 11.3 ns CC V = 1.65 V to 1.95 V 2.6 5.3 8.9 ns CC V = 2.3 V to 2.7 V 2.3 4.4 7.0 ns CC V = 3.0 V to 3.6 V 2.2 4.2 6.4 ns CC T = 25 °C amb C power dissipation f = 1 MHz; V = GND to V [3] PD I CC capacitance V = 0.8 V - 2.5 - pF CC V = 1.1 V to 1.3 V - 2.6 - pF CC V = 1.4 V to 1.6 V - 2.8 - pF CC V = 1.65 V to 1.95 V - 2.9 - pF CC V = 2.3 V to 2.7 V - 3.4 - pF CC V = 3.0 V to 3.6 V - 3.9 - pF CC [1] All typical values are measured at nominal VCC. [2] tpd is the same as tPLH and tPHL. [3] CPD is used to determine the dynamic power dissipation (PD in μW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; Σ(CL × VCC2 × fo) = sum of the outputs. 74AUP1G32_Q100 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2019. All rights reserved Product data sheet Rev. 3 — 28 January 2019 7 / 14

Nexperia 74AUP1G32-Q100 Low-power 2-input OR-gate Table 9. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 8 Symbol Parameter Conditions -40 °C to +85 °C -40 °C to +125 °C Unit Min Max Min Max C = 5 pF L t propagation delay A, B to Y; see Fig. 7 [1] pd V = 1.1 V to 1.3 V 2.1 11.9 2.1 13.2 ns CC V = 1.4 V to 1.6 V 1.4 7.5 1.4 8.3 ns CC V = 1.65 V to 1.95 V 1.2 6.0 1.2 6.6 ns CC V = 2.3 V to 2.7 V 1.0 4.6 1.0 5.1 ns CC V = 3.0 V to 3.6 V 0.9 4.1 0.9 4.6 ns CC C = 10 pF L t propagation delay A, B to Y; see Fig. 7 [1] pd V = 1.1 V to 1.3 V 2.1 13.8 2.1 15.2 ns CC V = 1.4 V to 1.6 V 1.7 8.7 1.7 9.6 ns CC V = 1.65 V to 1.95 V 1.5 6.9 1.5 7.7 ns CC V = 2.3 V to 2.7 V 1.3 5.5 1.3 6.1 ns CC V = 3.0 V to 3.6 V 1.2 5.0 1.2 5.5 ns CC C = 15 pF L t propagation delay A, B to Y; see Fig. 7 [1] pd V = 1.1 V to 1.3 V 3.0 15.6 3.0 17.2 ns CC V = 1.4 V to 1.6 V 2.0 9.8 2.0 10.8 ns CC V = 1.65 V to 1.95 V 1.8 7.9 1.8 8.7 ns CC V = 2.3 V to 2.7 V 1.6 6.3 1.6 6.9 ns CC V = 3.0 V to 3.6 V 1.5 5.8 1.5 6.4 ns CC C = 30 pF L t propagation delay A, B to Y; see Fig. 7 [1] pd V = 1.1 V to 1.3 V 4.0 21.5 4.0 23.7 ns CC V = 1.4 V to 1.6 V 2.9 13.3 2.9 14.7 ns CC V = 1.65 V to 1.95 V 2.4 10.7 2.4 11.8 ns CC V = 2.3 V to 2.7 V 2.2 8.4 2.2 9.3 ns CC V = 3.0 V to 3.6 V 2.1 7.7 2.1 8.5 ns CC [1] tpd is the same as tPLH and tPHL. 74AUP1G32_Q100 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2019. All rights reserved Product data sheet Rev. 3 — 28 January 2019 8 / 14

Nexperia 74AUP1G32-Q100 Low-power 2-input OR-gate 11.1. Waveforms and test circuit VI A, B input VM GND tPHL tPLH VOH Y output VM VOL mna615 Measurement points are given in Table 10. Logic levels: V and V are typical output voltage drop that occur with the output load. OL OH Fig. 7. The data input (A or B) to output (Y) propagation delays Table 10. Measurement points Supply voltage Output Input V V V V t = t CC M M I r f 0.8 V to 3.6 V 0.5 × V 0.5 × V V ≤ 3.0 ns CC CC CC VCC VEXT 5 kΩ VI VO G DUT RT CL RL 001aac521 Test data is given in Table 11. Definitions for test circuit: R = Load resistance. L C = Load capacitance including jig and probe capacitance. L R = Termination resistance should be equal to the output impedance Z of the pulse generator. T o V = External voltage for measuring switching times. EXT Fig. 8. Test circuit for measuring switching times Table 11. Test data Supply voltage Load V EXT V C R [1] t , t t , t t , t CC L L PLH PHL PZH PHZ PZL PLZ 0.8 V to 3.6 V 5 pF, 10 pF, 15 pF and 30 pF 5 kΩ or 1 MΩ open GND 2 × V CC [1] For measuring enable and disable times RL = 5 kΩ, for measuring propagation delays, setup and hold times and pulse width RL = 1 MΩ. 74AUP1G32_Q100 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2019. All rights reserved Product data sheet Rev. 3 — 28 January 2019 9 / 14

Nexperia 74AUP1G32-Q100 Low-power 2-input OR-gate 12. Package outline TSSOP5: plastic thin shrink small outline package; 5 leads; body width 1.25 mm SOT353-1 D E A X c y HE v M A Z 5 4 A2 A A1 (A3) θ 1 3 Lp L e w M bp e1 detail X 0 1.5 3 mm scale DIMENSIONS (mm are the original dimensions) UNIT mAax . A1 A2 A3 bp c D(1) E(1) e e1 HE L Lp v w y Z(1) θ 0.1 1.0 0.30 0.25 2.25 1.35 2.25 0.46 0.60 7° mm 1.1 0.15 0.65 1.3 0.425 0.3 0.1 0.1 0 0.8 0.15 0.08 1.85 1.15 2.0 0.21 0.15 0° Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE REFERENCES EUROPEAN ISSUE DATE VERSION IEC JEDEC JEITA PROJECTION 00-09-01 SOT353-1 MO- 203 SC-88A 03-02-19 Fig. 9. Package outline SOT353-1 (TSSOP5) 74AUP1G32_Q100 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2019. All rights reserved Product data sheet Rev. 3 — 28 January 2019 10 / 14

Nexperia 74AUP1G32-Q100 Low-power 2-input OR-gate XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm SOT886 b 1 2 3 4x L1 L (2) e 6 5 4 e1 e1 6x A (2) A1 D E terminal 1 index area 0 1 2 mm scale Dimensions (mm are the original dimensions) Unit A(1) A1 b D E e e1 L L1 max 0.5 0.04 0.25 1.50 1.05 0.35 0.40 mm nom 0.20 1.45 1.00 0.6 0.5 0.30 0.35 min 0.17 1.40 0.95 0.27 0.32 Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. sot886_po Outline References European Issue date version IEC JEDEC JEITA projection 04-07-22 SOT886 MO-252 12-01-05 Fig. 10. Package outline SOT886 (XSON6) 74AUP1G32_Q100 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2019. All rights reserved Product data sheet Rev. 3 — 28 January 2019 11 / 14

Nexperia 74AUP1G32-Q100 Low-power 2-input OR-gate 13. Abbreviations Table 12. Abbreviations Acronym Description CDM Charged Device Model DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MIL Military MM Machine Model 14. Revision history Table 13. Revision history Document ID Release date Data sheet status Change notice Supersedes 74AUP1G32_Q100 v.3 20190128 Product data sheet - 74AUP1G32_Q100 v.2 Modifications: • The format of this data sheet has been redesigned to comply with the identity guidelines of Nexperia. • Legal texts have been adapted to the new company name where appropriate. • Type number 74AUP1G32GM-Q100 (SOT886) added. 74AUP1G32_Q100 v.2 20130704 Product data sheet - 74AUP1G32_Q100 v.1 Modifications: • Typical values C and C corrected (errata). I O 74AUP1G32_Q100 v.1 20130320 Product data sheet - - 74AUP1G32_Q100 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2019. All rights reserved Product data sheet Rev. 3 — 28 January 2019 12 / 14

Nexperia 74AUP1G32-Q100 Low-power 2-input OR-gate equipment, nor in applications where failure or malfunction of an Nexperia 15. Legal information product can reasonably be expected to result in personal injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer's own Data sheet status risk. Quick reference data — The Quick reference data is an extract of the Document status Product Definition product data given in the Limiting values and Characteristics sections of this [1][2] status [3] document, and as such is not complete, exhaustive or legally binding. Objective [short] Development This document contains data from Applications — Applications that are described herein for any of these data sheet the objective specification for products are for illustrative purposes only. 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The English version shall prevail in case of any discrepancy for the content in this document if provided by an information source outside between the translated and English versions. of Nexperia. In no event shall Nexperia be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost Trademarks profits, lost savings, business interruption, costs related to the removal Notice: All referenced brands, product names, service names and or replacement of any products or rework charges) whether or not such trademarks are the property of their respective owners. damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, Nexperia’s aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of Nexperia. Right to make changes — Nexperia reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use in automotive applications — This Nexperia product has been qualified for use in automotive applications. Unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or 74AUP1G32_Q100 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2019. All rights reserved Product data sheet Rev. 3 — 28 January 2019 13 / 14

Nexperia 74AUP1G32-Q100 Low-power 2-input OR-gate Contents 1. General description......................................................1 2. Features and benefits..................................................1 3. Ordering information....................................................1 4. Marking..........................................................................2 5. Functional diagram.......................................................2 6. Pinning information......................................................2 6.1. Pinning.........................................................................2 6.2. Pin description.............................................................2 7. Functional description.................................................3 8. Limiting values.............................................................3 9. Recommended operating conditions..........................3 10. Static characteristics..................................................4 11. Dynamic characteristics.............................................6 11.1. Waveforms and test circuit........................................9 12. Package outline........................................................10 13. Abbreviations............................................................12 14. Revision history........................................................12 15. Legal information......................................................13 © Nexperia B.V. 2019. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 28 January 2019 74AUP1G32_Q100 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2019. All rights reserved Product data sheet Rev. 3 — 28 January 2019 14 / 14