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ICGOO电子元器件商城为您提供74ALVC162244TX由Fairchild Semiconductor设计生产,在icgoo商城现货销售,并且可以通过原厂、代理商等渠道进行代购。 74ALVC162244TX价格参考¥11.45-¥20.71。Fairchild Semiconductor74ALVC162244TX封装/规格:逻辑 - 缓冲器,驱动器,接收器,收发器, 缓冲器,非反向 4 Element 4 Bit per Element 三态 Output 48-TSSOP。您可以下载74ALVC162244TX参考资料、Datasheet数据手册功能说明书,资料中有74ALVC162244TX 详细功能的应用电路图电压和使用方法及教程。
参数 | 数值 |
产品目录 | 集成电路 (IC)半导体 |
描述 | IC BUFF DVR 16BIT LOW V 48TSSOP缓冲器和线路驱动器 Buffer/Line Driver LV 16Bit Inverting |
产品分类 | |
品牌 | Fairchild Semiconductor |
产品手册 | |
产品图片 | |
rohs | 符合RoHS无铅 / 符合限制有害物质指令(RoHS)规范要求 |
产品系列 | 逻辑集成电路,缓冲器和线路驱动器,Fairchild Semiconductor 74ALVC162244TX74ALVC |
数据手册 | |
产品型号 | 74ALVC162244TX |
产品种类 | 缓冲器和线路驱动器 |
传播延迟时间 | 4.3 ns at 2.7 V, 3.8 ns at 3.3 V |
低电平输出电流 | 12 mA |
供应商器件封装 | 48-TSSOP |
元件数 | 4 |
其它名称 | 74ALVC162244TXDKR |
包装 | Digi-Reel® |
单位重量 | 421 mg |
商标 | Fairchild Semiconductor |
安装类型 | 表面贴装 |
安装风格 | SMD/SMT |
封装 | Reel |
封装/外壳 | 48-TFSOP(0.240",6.10mm 宽) |
封装/箱体 | TSSOP-48 |
工作温度 | -40°C ~ 85°C |
工厂包装数量 | 1000 |
最大工作温度 | + 85 C |
最小工作温度 | - 40 C |
极性 | Non-Inverting |
标准包装 | 1 |
每元件位数 | 4 |
每芯片的通道数量 | 16 |
电压-电源 | 1.65 V ~ 3.6 V |
电流-输出高,低 | 12mA,12mA |
电源电压-最大 | 3.6 V |
电源电压-最小 | 1.65 V |
系列 | 74ALVC162244 |
输入线路数量 | 16 |
输出类型 | 3-State |
输出线路数量 | 3 |
逻辑类型 | CMOS |
逻辑系列 | ALVC |
高电平输出电流 | - 12 mA |
Is Now Part of To learn more about ON Semiconductor, please visit our website at www.onsemi.com Please note: As part of the Fairchild Semiconductor integration, some of the Fairchild orderable part numbers will need to change in order to meet ON Semiconductor’s system requirements. Since the ON Semiconductor product management systems do not have the ability to manage part nomenclature that utilizes an underscore (_), the underscore (_) in the Fairchild part numbers will be changed to a dash (-). This document may contain device numbers with an underscore (_). Please check the ON Semiconductor website to verify the updated device numbers. The most current and up-to-date ordering information can be found at www.onsemi.com. Please email any questions regarding the system integration to Fairchild_questions@onsemi.com. ON Semiconductor and the ON Semiconductor logo are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
R 7 November 2001 es 4A Revised November 2001 i L s V t o C 74ALVC162244 r in 162 O 2 Low Voltage 16-Bit Buffer/Line Driver u 44 tp L with 3.6V Tolerant Inputs and Outputs u o ts w and 26Ω Series Resistor in Outputs V o lt a General Description g e The ALVC162244 contains sixteen non-inverting buffers Features 1 with 3-STATE outputs to be employed as a memory and 6 address driver, clock driver, or bus oriented transmitter/ (cid:1) 1.65V to 3.6V VCC supply operation -B receiver. The device is nibble (4-bit) controlled. Each nibble (cid:1) 3.6V tolerant inputs and outputs it has separate 3-STATE control inputs which can be shorted (cid:1) 26Ω series resistors in outputs B tTohgee t7h4eAr LfoVrC fu1l6l 21264-b4i ti so pdeersaitgionne.d for low voltage (1.65V to (cid:1) tPD uff 3.6V) VCC applications with I/O capability up to 3.6V. The 3.8 ns max for 3.0V to 3.6V VCC er 74ALVC162244 is also designed with 26Ω series resistors 4.3 ns max for 2.3V to 2.7V VCC /L itnio nthse s ouuchtp uatss .m Tehmiso rdye saidgdnr eresds udcreivse rlisn,e c nloociks ed riniv earpsp, laicnad- 7.6 ns max for 1.65V to 1.95V VCC ine bus transceivers/transmitters. (cid:1) Power-off high impedance inputs and outputs D The 74ALVC162244 is fabricated with an advanced CMOS (cid:1) Supports live insertion and withdrawal r technology to achieve high speed operation while maintain- (cid:1) Uses patented noise/EMI reduction circuitry ive ing low CMOS power dissipation. (cid:1) Latchup conforms to JEDEC JED78 r w (cid:1) ESD performance: i Human body model > 2000V th Machine model > 200V 3 (cid:1) Also packaged in plastic Fine-Pitch Ball Grid Array .6 V (FBGA) T Note 1: To ensure the high-impedance state during power up or power o down, OE should be tied to VCC through a pull-up resistor; the minimum le value of the resistor is determined by the current-sourcing capability of the r driver. a n t I n p Ordering Code: u t s Order Number Package Number Package Description a n 74ALVC162244GX BGA54A 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide d (Note 2) [TAPE and REEL] O 74ALVC162244T MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide u (Note 3) t p Note 2: BGA package available in Tape and Reel only. u Note 3: Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. ts a n d 2 6 Ω S e r ie s © 2001 Fairchild Semiconductor Corporation DS500696 www.fairchildsemi.com
4 4 Logic Symbol Pin Descriptions 2 2 6 1 Pin Names Description C V OEn Output Enable Input (Active LOW) L A I0–I15 Inputs 74 O0–O15 Outputs NC No Connect Connection Diagrams FBGA Pin Assignments Pin Assignment for TSSOP 1 2 3 4 5 6 A O0 NC OE1 OE2 NC I0 B O2 O1 NC NC I1 I2 C O4 O3 VCC VCC I3 I4 D O6 O5 GND GND I5 I6 E O8 O7 GND GND I7 I8 F O10 O9 GND GND I9 I10 G O12 O11 VCC VCC I11 I12 H O14 O13 NC NC I13 I14 J O15 NC OE4 OE3 NC I15 Truth Tables Inputs Outputs OE1 I0–I3 O0–O3 L L L L H H H X Z Inputs Outputs Pin Assignment for FBGA OE2 I4–I7 O4–O7 L L L L H H H X Z Inputs Outputs OE3 I8–I11 O8–O11 L L L L H H H X Z Inputs Outputs (Top Thru View) OE4 I12–I15 O12–O15 L L L L H H H X Z H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial (HIGH or LOW, inputs may not float) Z = High Impedance www.fairchildsemi.com 2
7 Functional Description 4 A The 74ALVC162244 contains sixteen non-inverting buffers puts are controlled by an Output Enable (OEn) input. When LV with 3-STATE outputs. The device is nibble (4 bits) con- OEn is LOW, the outputs are in the 2-state mode. When C tdreonllet do wf iteha ecahc ho tnhiebrb. leT fhuen cctioonntinrogl idpeinnsti cmallayy, bbuet insdheopretend- OEn is HIGH, the standard outputs are in the high imped- 16 together to obtain full 16-bit operation.The 3-STATE out- ance mode but this does not interfere with entering new 2 data into the inputs. 2 4 4 Logic Diagram 3 www.fairchildsemi.com
4 4 Absolute Maximum Ratings Recommended Operating 2 (Note 4) 2 Conditions 16 Supply Voltage (VCC) −0.5V to +4.6V (Note 6) C DC Input Voltage (VI) −0.5V to 4.6V Power Supply LV Output Voltage (VO) (Note 5) −0.5V to VCC +0.5V Operating 1.65V to 3.6V A DC Input Diode Current (IIK) Input Voltage 0V to VCC 74 VI < 0V −50 mA Output Voltage (VO) 0V to VCC DC Output Diode Current (IOK) Free Air Operating Temperature (TA) −40°C to +85°C VO < 0V −50 mA Minimum Input Edge Rate (∆t/∆V) DC Output Source/Sink Current VIN = 0.8V to 2.0V, VCC = 3.0V 10 ns/V (IOH/IOL) ±50 mA Note 4: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be DC VCC or GND Current per operated at these limits. The parametric values defined in the Electrical Supply Pin (ICC or GND) ±100 mA Characteristics tables are not guaranteed at the Absolute Maximum Rat- ings. The “Recommended Operating Conditions” table will define the condi- Storage Temperature Range (TSTG) −65°C to +150°C tions for actual device operation. Note 5: IO Absolute Maximum Rating must be observed. Note 6: Floating or unused control inputs must be held HIGH or LOW. DC Electrical Characteristics VCC Symbol Parameter Conditions Min Max Units (V) VIH HIGH Level Input Voltage 1.65 - 1.95 0.65 x VCC 2.3 - 2.7 1.7 V 2.7 - 3.6 2.0 VIL LOW Level Input Voltage 1.65 - 1.95 0.35 x VCC 2.3 - 2.7 0.7 V 2.7 - 3.6 0.8 VOH HIGH Level Output Voltage IOH = −100 µA 1.65 - 3.6 VCC - 0.2 IOH = −2 mA 1.65 1.2 IOH = −4 mA 2.3 1.9 IOH = −6 mA 2.3 1.7 V 3 2.4 IOH = −8 mA 2.7 2 IOH = −12 mA 3.0 2 VOL LOW Level Output Voltage IOL = 100 µA 1.65 - 3.6 0.2 IOL = 2 mA 1.65 0.45 IOL = 4 mA 2.3 0.4 IOL = 6 mA 2.3 0.55 V 3 0.55 IOL = 8 mA 2.7 0.6 IOL = 12 mA 3 0.8 II Input Leakage Current 0 ≤ VI ≤ 3.6V 3.6 ±5.0 µA IOZ 3-STATE Output Leakage 0 ≤ VO ≤ 3.6V 3.6 ±10 µA ICC Quiescent Supply Current VI = VCC or GND, IO = 0 3.6 40 µA ∆ICC Increase in ICC per Input VIH = VCC − 0.6V 3 - 3.6 750 µA www.fairchildsemi.com 4
7 AC Electrical Characteristics 4 A L TA = −40°C to +85°C, RL = 500Ω V Symbol Parameter CL = 50 pF CL = 30 pF Units C1 VCC = 3.3V ± 0.3V VCC = 2.7V VCC = 2.5V ± 0.2V VCC = 1.8V ± 0.15V 6 2 Min Max Min Max Min Max Min Max 2 4 tPHL, tPLH Propagation Delay 1.3 3.8 1.5 4.3 1.0 3.8 1.5 7.6 ns 4 tPZL, tPZH Output Enable Time 1.3 4.3 1.5 5.6 1.0 5.1 1.5 9.8 ns tPLZ, tPHZ Output Disable Time 1.3 4.1 1.5 4.5 1.0 4.0 1.5 7.2 ns Capacitance TA = +25°C Symbol Parameter Conditions Units VCC Typical CIN Input Capacitance VI = 0V or VCC 3.3 6 pF COUT Output Capacitance VI = 0V or VCC 3.3 7 pF CPD Power Dissipation Capacitance Outputs Enabled f = 10 MHz, CL = 50 pF 3.3 20 pF 2.5 20 5 www.fairchildsemi.com
4 4 AC Loading and Waveforms 2 2 TABLE 1. Values for Figure 1 6 1 TEST SWITCH C V tPLH, tPHL Open L A tPZL, tPLZ VL 4 tPZH, tPHZ GND 7 FIGURE 1. AC Test Circuit TABLE 2. Variable Matrix (Input Characteristics: f = tr = tf = 2ns; Z0 = 50Ω VCC Symbol 3.3V ± 0.3V 2.7V 2.5V ± 0.2V 1.8V ± 0.15V Vmi 1.5V 1.5V VCC/2 VCC/2 Vmo 1.5V 1.5V VCC/2 VCC/2 VX VOL + 0.3V VOL + 0.3V VOL + 0.15V VOL + 0.15V VY VOH − 0.3V VOH − 0.3V VOH − 0.15V VOH − 0.15V VL 6V 6V VCC*2 VCC*2 FIGURE 2. Waveform for Inverting and Non-Inverting Functions FIGURE 3. 3-STATE Output High Enable and Disable Times for Low Voltage Logic FIGURE 4. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic www.fairchildsemi.com 6
7 Physical Dimensions 4 inches (millimeters) unless otherwise noted A L V C 1 6 2 2 4 4 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide Package Number BGA54A 7 www.fairchildsemi.com
s s e t Physical Dimensions ri pu inches (millimeters) unless otherwise noted (Continued) e S ut Ω O 6 n 2 i d or n t a s s si t e u R p t u O d n a s t u p n I t n a r e l o T V 6 . 3 h t i w r e v ri D e n i L / r e f f u B t i B - 6 1 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide e Package Number MTD48 g a t l o V w Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and o Fairchild reserves the right at any time without notice to change said circuitry and specifications. L 4 LIFE SUPPORT POLICY 4 2 FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT 2 6 DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD 1 SEMICONDUCTOR CORPORATION. As used herein: C V 1. Life support devices or systems are devices or systems 2. A critical component in any component of a life support L which, (a) are intended for surgical implant into the device or system whose failure to perform can be rea- A body, or (b) support or sustain life, and (c) whose failure sonably expected to cause the failure of the life support 4 to perform when properly used in accordance with device or system, or to affect its safety or effectiveness. 7 instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the www.fairchildsemi.com user. www.fairchildsemi.com 8
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