74AHC595; 74AHCT595 8-bit serial-in/serial-out or parallel-out shift register with output latches Rev. 5 — 4 July 2012 Product data sheet 1. General description The 74AHC595; 74AHCT595 are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No.7A. The 74AHC595; 74AHCT595 are 8-stage serial shift registers with a storage register and 3-state outputs. The registers have separate clocks. Data is shifted on the positive-going transitions of the shift register clock input (SHCP). The data in each register is transferred to the storage register on a positive-going transition of the storage register clock input (STCP). If both clocks are connected together, the shift register will always be one clock pulse ahead of the storage register. The shift register has a serial input (DS) and a serial standard output (Q7S) for cascading. It is also provided with asynchronous reset (active LOW) for all 8 shift register stages. The storage register has 8 parallel 3-state bus driver outputs. Data in the storage register appears at the output whenever the output enable input (OE) is LOW. 2. Features and benefits  Balanced propagation delays  All inputs have Schmitt-trigger action  Inputs accept voltages higher than V CC  Input levels: The 74AHC595 operates with CMOS input levels The 74AHCT595 operates with TTL input levels  ESD protection: HBMJESD22-A114F exceeds2000V MMJESD22-A115-A exceeds200V CDM JESD22-C101E exceeds1000V  Multiple package options  Specified from 40C to+85C and from 40C to+125C 3. Applications  Serial-to-parallel data conversion  Remote control holding register

74AHC595; 74AHCT595 Nexperia 8-bit serial-in/serial-out or parallel-out shift register with output latches 4. Ordering information Table 1. Ordering info rmation Type number Package Temperature range Name Description Version 74AHC595 74AHC595D 40 C to +125 C SO16 plastic small outline package; 16 leads; body SOT109-1 width 3.9 mm 74AHC595PW 40 C to +125 C TSSOP16 plastic thin shrink small outline package; 16 leads; SOT403-1 body width 4.4 mm 74AHC595BQ 40 C to +125 C DHVQFN16 plastic dual in-line compatible thermal enhanced SOT763-1 very thin quad flat package; no leads; 16terminals; body2.53.50.85 mm 74AHCT595 74AHCT595D 40 C to +125 C SO16 plastic small outline package; 16 leads; body SOT109-1 width 3.9 mm 74AHCT595PW 40 C to +125 C TSSOP16 plastic thin shrink small outline package; 16 leads; SOT403-1 body width 4.4 mm 74AHCT595BQ 40 C to +125 C DHVQFN16 plastic dual in-line compatible thermal enhanced SOT763-1 very thin quad flat package; no leads; 16terminals; body2.53.50.85 mm 5. Functional diagram 14 DS 11 SHCP 8-STAGE SHIFT REGISTER 10 MR Q7S 9 12 STCP 8-BIT STORAGE REGISTER 13 OE 3-STATE OUTPUTS Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 15 1 2 3 4 5 6 7 mna554 Fig 1. Functional diagram 74AHC_AHCT595 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved Product data sheet Rev. 5 — 4 July 2012 2 of 22

74AHC595; 74AHCT595 Nexperia 8-bit serial-in/serial-out or parallel-out shift register with output latches 13 EN3 12 11 12 C2 10 SHCP STCP R SRG8 Q7S 9 11 C1/ 15 Q0 14 15 1 1D 2D 3 Q1 1 2 Q2 2 14 3 DS Q3 3 4 Q4 4 5 Q5 5 6 Q6 6 7 Q7 7 MR OE 9 10 13 mna552 mna553 Fig 2. Logic symbol Fig 3. IEC logic symbol STAGE 0 STAGES 1 TO 6 STAGE 7 DS D Q D Q D Q Q7S FF0 FF7 CP CP R R SHCP MR D Q D Q LATCH LATCH CP CP STCP OE mna555 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Fig 4. Logic diagram 74AHC_AHCT595 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved Product data sheet Rev. 5 — 4 July 2012 3 of 22

74AHC595; 74AHCT595 Nexperia 8-bit serial-in/serial-out or parallel-out shift register with output latches 6. Pinning information 6.1 Pinning 74AHC595 74AHCT595 terminal 1 1 CC index area Q V 74AHC595 74AHCT595 1 16 Q2 2 15 Q0 Q3 3 14 DS Q1 1 16 VCC Q2 2 15 Q0 Q4 4 13 OE Q3 3 14 DS Q5 5 12 STCP Q4 4 13 OE Q6 6 GND(1) 11 SHCP Q5 5 12 STCP Q7 7 10 MR Q6 6 11 SHCP 8 9 Q7 7 10 MR D S GND 8 9 Q7S GN Q7 001aae483 001aae538 Transparent top view (1) This is not a supply pin. The substrate is attached to this pad using conductive die attach material. There is no electrical or mechanical requirement to solder this pad. However, if it is soldered, the solder land should remain floating or be connected to GND. Fig 5. Pin configuration SO16 and TSSOP16 Fig 6. Pin configuration DHVQFN16 6.2 Pin description Table 2. Pin descripti on Symbol Pin Description Q1 1 parallel data output 1 Q2 2 parallel data output 2 Q3 3 parallel data output 3 Q4 4 parallel data output 4 Q5 5 parallel data output 5 Q6 6 parallel data output 6 Q7 7 parallel data output 7 GND 8 ground (0 V) Q7S 9 serial data output MR 10 master reset (active LOW) SHCP 11 shift register clock input STCP 12 storage register clock input OE 13 output enable input (active LOW) DS 14 serial data input Q0 15 parallel data output 0 V 16 supply voltage CC 74AHC_AHCT595 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved Product data sheet Rev. 5 — 4 July 2012 4 of 22

74AHC595; 74AHCT595 Nexperia 8-bit serial-in/serial-out or parallel-out shift register with output latches 7. Functional description Table 3. Function tab le[1] Control Input Output Function SHCP STCP OE MR DS Q7S Qn X X L L X L NC a LOW-level on MR only affects the shift registers X  L L X L L empty shift register loaded into storage register X X H L X L Z shift register clear; parallel outputs in high-impedance OFF-state  X L H H Q6S NC logic HIGH-level shifted into shift register stage 0. Contents of all shift register stages shifted through, e.g. previous state of stage 6 (internal Q6S) appears on the serial output (Q7S). X  L H X NC QnS contents of shift register stages (internal QnS) are transferred to the storage register and parallel output stages  L H X Q6S QnS contents of shift register shifted through; previous contents of the shift register is transferred to the storage register and the parallel output stages [1] H=HIGH voltage state; L=LOW voltage state; =LOW-to-HIGH transition; X=don’t care; NC=no change; Z=high-impedance OFF-state. DS STCP MR OE Z-state Q0 Z-state Q1 Z-state Q6 Z-state Q7 Q7S Fig 7. Timing diagram 74AHC_AHCT595 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved Product data sheet Rev. 5 — 4 July 2012 5 of 22

74AHC595; 74AHCT595 Nexperia 8-bit serial-in/serial-out or parallel-out shift register with output latches 8. Limiting values Table 4. Limiting valu es In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0V). Symbol Parameter Conditions Min Max Unit V supply voltage 0.5 +7.0 V CC V input voltage 0.5 +7.0 V I I input clamping current V <0.5V [1] 20 - mA IK I I output clamping current V <0.5V or V >V +0.5V [1] 20 +20 mA OK O O CC I output current V =0.5V to (V +0.5V) 25 +25 mA O O CC I supply current - +75 mA CC I ground current 75 - mA GND T storage temperature 65 +150 C stg P total power dissipation T =40C to +125C [2] - 500 mW tot amb [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] For SO16 packages: above 70C the value of Ptotderates linearly at 8mW/K. For TSSOP16 packages: above 60C the value of Ptotderates linearly at 5.5mW/K. For DHVQFN16 packages: above 60C the value of Ptotderates linearly at 4.5mW/K. 9. Recommended operating conditions Table 5. Operating co nditions Symbol Parameter Conditions Min Typ Max Unit 74AHC595 V supply voltage 2.0 5.0 5.5 V CC V input voltage 0 - 5.5 V I V output voltage 0 - V V O CC T ambient temperature 40 +25 +125 C amb t/V input transition rise and fall rate V =3.0 V to 3.6V - - 100 ns/V CC V =4.5 V to 5.5V - - 20 ns/V CC 74AHCT595 V supply voltage 4.5 5.0 5.5 V CC V input voltage 0 - 5.5 V I V output voltage 0 - V V O CC T ambient temperature 40 +25 +125 C amb t/V input transition rise and fall rate V =4.5 V to 5.5V - - 20 ns/V CC 74AHC_AHCT595 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved Product data sheet Rev. 5 — 4 July 2012 6 of 22

74AHC595; 74AHCT595 Nexperia 8-bit serial-in/serial-out or parallel-out shift register with output latches 10. Static characteristics Table 6. Static charac teristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 25 C 40C to+85 C 40C to+125 C Unit Min Typ Max Min Max Min Max 74AHC595 V HIGH-level V = 2.0 V 1.5 - - 1.5 - 1.5 - V IH CC input voltage V = 3.0 V 2.1 - - 2.1 - 2.1 - V CC V = 5.5 V 3.85 - - 3.85 - 3.85 - V CC V LOW-level V = 2.0 V - - 0.5 - 0.5 - 0.5 V IL CC input voltage V = 3.0 V - - 0.9 - 0.9 - 0.9 V CC V = 5.5 V - - 1.65 - 1.65 - 1.65 V CC V HIGH-level V = V or V OH I IH IL output voltage I = 50A; V =2.0 V 1.9 2.0 - 1.9 - 1.9 - V O CC I = 50A; V =3.0 V 2.9 3.0 - 2.9 - 2.9 - V O CC I = 50A; V =4.5 V 4.4 4.5 - 4.4 - 4.4 - V O CC I = 4.0mA; V =3.0 V 2.58 - - 2.48 - 2.40 - V O CC I = 8.0mA; V =4.5 V 3.94 - - 3.80 - 3.70 - V O CC V LOW-level V = V or V OL I IH IL output voltage I = 50A; V =2.0 V - 0 0.1 - 0.1 - 0.1 V O CC I = 50A; V =3.0 V - 0 0.1 - 0.1 - 0.1 V O CC I = 50A; V =4.5 V - 0 0.1 - 0.1 - 0.1 V O CC I = 4.0mA; V =3.0 V - - 0.36 - 0.44 - 0.55 V O CC I = 8.0mA; V =4.5 V - - 0.36 - 0.44 - 0.55 V O CC I input leakage V =5.5 VorGND; - - 0.1 - 1.0 - 2.0 A I I current V =0Vto5.5V CC I OFF-state V =V orV ; - - 0.25 - 2.5 - 10 A OZ I IH IL output current V =V orGND; V =5.5V O CC CC I supply current V =V orGND; I = 0 A; - - 4.0 - 40 - 80 A CC I CC O V =5.5V CC C input - 3 10 - 10 - 10 pF I capacitance 74AHCT595 V HIGH-level V = 4.5 V to 5.5 V 2.0 - - 2.0 - 2.0 - V IH CC input voltage V LOW-level V = 4.5 V to 5.5 V - - 0.8 - 0.8 - 0.8 V IL CC input voltage V HIGH-level V = V or V ; V =4.5 V OH I IH IL CC output voltage I = 50A 4.4 4.5 - 4.4 - 4.4 - V O I = 8.0mA 3.94 - - 3.80 - 3.70 - V O V LOW-level V = V or V ; V =4.5 V OL I IH IL CC output voltage I = 50A - 0 0.1 - 0.1 - 0.1 V O I = 8.0mA - - 0.36 - 0.44 - 0.55 V O 74AHC_AHCT595 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved Product data sheet Rev. 5 — 4 July 2012 7 of 22

74AHC595; 74AHCT595 Nexperia 8-bit serial-in/serial-out or parallel-out shift register with output latches Table 6. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 25 C 40C to+85 C 40C to+125 C Unit Min Typ Max Min Max Min Max I input leakage V =5.5 VorGND; - - 0.1 - 1.0 - 2.0 A I I current V =0Vto5.5V CC I OFF-state V =V orV ; - - 0.25 - 2.5 - 10 A OZ I IH IL output current V =V orGNDper input pin; O CC other inputs at V orGND; CC I =0 A; V =5.5V O CC I supply current V =V orGND; I = 0 A; - - 4.0 - 40 - 80 A CC I CC O V =5.5V CC I additional per input pin; V =V 2.1V; - - 1.35 - 1.5 - 1.5 mA CC I CC supply current otherinputsatV or GND; CC I =0 A; V =4.5Vto5.5V O CC C input - 3 10 - 10 - 10 pF I capacitance 74AHC_AHCT595 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved Product data sheet Rev. 5 — 4 July 2012 8 of 22

74AHC595; 74AHCT595 Nexperia 8-bit serial-in/serial-out or parallel-out shift register with output latches 11. Dynamic characteristics Table 7. Dynamic cha racteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure13. Symbol Parameter Conditions 25 C 40C to+85 C 40C to+125 C Unit Min Typ[1] Max Min Max Min Max 74AHC595 t propagation SHCPtoQ7S; see Figure8 [2] pd delay V = 3.0 V to 3.6 V CC C =15pF - 5.7 13.0 1.0 15.0 1.0 16.5 ns L C =50pF - 7.7 16.5 1.0 18.5 1.0 20.1 ns L V = 4.5 V to 5.5 V CC C =15pF - 4.0 8.2 1.0 9.4 1.0 10.5 ns L C =50pF - 5.4 10.0 1.0 11.4 1.0 12.5 ns L STCPtoQn; see Figure9 [2] V = 3.0 V to 3.6 V CC C =15pF - 5.9 11.9 1.0 13.5 1.0 15.0 ns L C =50pF - 7.7 15.4 1.0 17.0 1.0 18.5 ns L V = 4.5 V to 5.5 V CC C =15pF - 4.2 7.4 1.0 8.5 1.0 9.5 ns L C =50pF - 5.5 9.0 1.0 10.5 1.0 11.5 ns L MRtoQ7S; see Figure11 [3] V = 3.0 V to 3.6 V CC C =15pF - 5.9 12.8 1.0 13.7 1.0 15.0 ns L C =50pF - 7.4 16.3 1.0 17.2 1.0 18.7 ns L V = 4.5 V to 5.5 V CC C =15pF - 4.4 8.0 1.0 9.1 1.0 10.0 ns L C =50pF - 5.6 10.0 1.0 11.1 1.0 12.0 ns L t enable time OE to Qn; see Figure12 [4] en V = 3.0 V to 3.6 V CC C =15pF - 5.6 11.5 1.0 13.5 1.0 15.0 ns L C =50pF - 7.4 15.0 1.0 17.0 1.0 18.5 ns L V = 4.5 V to 5.5 V CC C =15pF - 4.0 8.6 1.0 10.0 1.0 11.0 ns L C =50pF - 5.3 10.6 1.0 12.0 1.0 13.0 ns L t disable time OE to Qn; see Figure12 [5] dis V = 3.0 V to 3.6 V CC C =15pF - 5.4 11.0 1.0 13.0 1.0 14.5 ns L C =50pF - 8.7 15.7 1.0 16.2 1.0 17.5 ns L V = 4.5 V to 5.5 V CC C =15pF - 3.8 8.0 1.0 9.5 1.0 10.5 ns L C =50pF - 5.8 10.3 1.0 11.0 1.0 12.0 ns L 74AHC_AHCT595 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved Product data sheet Rev. 5 — 4 July 2012 9 of 22

74AHC595; 74AHCT595 Nexperia 8-bit serial-in/serial-out or parallel-out shift register with output latches Table 7. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure13. Symbol Parameter Conditions 25 C 40C to+85 C 40C to+125 C Unit Min Typ[1] Max Min Max Min Max f maximum SHCP or STCP; max frequency seeFigure8 and 9 V = 3.0 V to 3.6 V 80 125 - 60 - 40 - MHz CC V = 4.5 V to 5.5 V 130 170 - 110 - 90 - MHz CC t pulse width SHCP HIGH or LOW; W seeFigure8 V = 3.0 V to 3.6 V 5.0 - - 5.0 - 5.0 - ns CC V = 4.5 V to 5.5 V 5.0 - - 5.0 - 5.0 - ns CC STCP HIGH or LOW; seeFigure9 V = 3.0 V to 3.6 V 5.0 - - 5.0 - 5.0 - ns CC V = 4.5 V to 5.5 V 5.0 - - 5.0 - 5.0 - ns CC MR LOW; seeFigure11 V = 3.0 V to 3.6 V 5.0 - - 5.0 - 5.0 - ns CC V = 4.5 V to 5.5 V 5.0 - - 5.0 - 5.0 - ns CC t set-up time DS to SHCP; seeFigure9 su V = 3.0 V to 3.6 V 3.5 - - 3.5 - 3.5 - ns CC V = 4.5 V to 5.5 V 3.0 - - 3.0 - 3.0 - ns CC SHCP to STCP; seeFigure10 V = 3.0 V to 3.6 V 8.5 - - 8.5 - 8.5 - ns CC V = 4.5 V to 5.5 V 5.0 - - 5.0 - 5.0 - ns CC t hold time DS to SHCP; seeFigure10 h V = 3.0 V to 3.6 V 1.5 - - 1.5 - 1.5 - ns CC V = 4.5 V to 5.5 V 2.0 - - 2.0 - 2.0 - ns CC t recovery MR to SHCP; see Figure11 rec time V = 3.0 V to 3.6 V 3.0 - - 3.0 - 3.0 - ns CC V = 4.5 V to 5.5 V 2.5 - - 2.5 - 2.5 - ns CC C power f = 1 MHz; V =GNDtoV [6] - 180 - - - - - pF PD i I CC dissipation [7] capacitance 74AHCT595; V = 4.5 V to 5.5 V CC t propagation SHCPtoQ7S; see Figure8 [2] pd delay C =15pF - 3.8 8.2 1.0 9.0 1.0 10.0 ns L C =50pF - 5.2 10.0 1.0 11.0 1.0 12.0 ns L STCPtoQn; see Figure9 [2] C =15pF - 4.0 7.4 1.0 8.5 1.0 9.5 ns L C =50pF - 5.3 9.0 1.0 10.5 1.0 11.5 ns L MRtoQ7S; see Figure11 [3] C =15pF - 4.6 8.2 1.0 9.5 1.0 10.5 ns L C =50pF - 5.8 10.5 1.0 11.5 1.0 12.5 ns L 74AHC_AHCT595 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved Product data sheet Rev. 5 — 4 July 2012 10 of 22

74AHC595; 74AHCT595 Nexperia 8-bit serial-in/serial-out or parallel-out shift register with output latches Table 7. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure13. Symbol Parameter Conditions 25 C 40C to+85 C 40C to+125 C Unit Min Typ[1] Max Min Max Min Max t enable time OE to Qn; see Figure12 [4] en C =15pF - 4.8 9.0 1.0 11.0 1.0 12.0 ns L C =50pF - 6.2 11.6 1.0 13.0 1.0 14.5 ns L t disable time OE to Qn; see Figure12 [5] dis C =15pF - 3.6 6.9 1.0 8.0 1.0 9.0 ns L C =50pF - 5.8 10.3 1.0 11.0 1.0 12.0 ns L f maximum SHCP and STCP; 130 170 - 110 - 90 - MHz max frequency seeFigure8 and 9 t pulse width SHCP HIGH or LOW; 5.0 - - 5.0 - 5.0 - ns W seeFigure8 STCP HIGH or LOW; 5.0 - - 5.0 - 5.0 - ns seeFigure9 MR LOW; seeFigure11 5.0 - - 5.0 - 5.0 - ns t set-up time DS to SHCP; seeFigure9 3.0 - - 3.0 - 3.0 - ns su SHCP to STCP; 5.0 - - 5.0 - 5.0 - ns seeFigure10 t hold time DS to SHCP; seeFigure10 2.0 - - 2.0 - 2.0 - ns h t recovery MR to SHCP; see Figure11 3.0 - - 3.0 - 3.0 - ns rec time C power f = 1 MHz; V =GNDtoV [6] - 190 - - - - - pF PD i I CC dissipation [7] capacitance [1] Typical values are measured at nominal supply voltage. [2] t is the same as t and t . pd PHL PLH [3] t is the same as t only. pd PHL [4] t is the same as t and t . en PZL PZH [5] t is the same as t and t . dis PLZ PHZ [6] CPDis used to determine the dynamic power dissipation (PDinW). PD=CPDVCC2fi+(CLVCC2fo)where: f =input frequency inMHz; i f =output frequency inMHz; o (CLVCC2fo)=sum of outputs; C =output load capacitance inpF; L V =supply voltage inV. CC [7] All 9outputs switching. 74AHC_AHCT595 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved Product data sheet Rev. 5 — 4 July 2012 11 of 22

74AHC595; 74AHCT595 Nexperia 8-bit serial-in/serial-out or parallel-out shift register with output latches 12. Waveforms 1/fmax VI SHCP input VM GND tW tPLH tPHL VOH Q7S output VM VOL mna557 Measurement points are given in Table8. VOL and VOH are typical output voltage levels that occur with the output load. Fig 8. Shift clock pulse, maximum frequency and input to output propagation delays VI SHCP input VM GND tsu 1/fmax VI STCP input VM GND tW tPLH tPHL VOH Qn output VM VOL mna558 Measurement points are given in Table8. V and V are typical output voltage levels that occur with the output load. OL OH Fig 9. Storage clock to output propagation delays 74AHC_AHCT595 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved Product data sheet Rev. 5 — 4 July 2012 12 of 22

74AHC595; 74AHCT595 Nexperia 8-bit serial-in/serial-out or parallel-out shift register with output latches VI SHCP input VM GND tsu tsu th th VI DS input VM GND VOH Q7S output VM VOL mna560 Measurement points are given in Table8. The shaded areas indicate when the input is permitted to change for predictable output performance. VOL and VOH are typical output voltage levels that occur with the output load. Fig 10. Data set-up and hold times VI MR input VM GND tW trec VI SHCP input VM GND tPHL VOH Q7S output VM VOL mna561 Measurement points are given in Table8. VOL and VOH are typical output voltage levels that occur with the output load. Fig 11. Master reset to output propagation delays 74AHC_AHCT595 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved Product data sheet Rev. 5 — 4 July 2012 13 of 22

74AHC595; 74AHCT595 Nexperia 8-bit serial-in/serial-out or parallel-out shift register with output latches VI OE input VM GND tPLZ tPZL VCC output LOW-to-OFF VM OFF-to-LOW VOL VOL + 0.3 V tPHZ tPZH output VOH VOH − 0.3 V HIGH-to-OFF VM OFF-to-HIGH GND outputs outputs outputs enabled disabled enabled mna450 Measurement points are given in Table8. VOL and VOH are typical output voltage levels that occur with the output load. Fig 12. Enable and disable times Table 8. Measuremen t points Type Input Output V V M M 74AHC595 0.5V 0.5V CC CC 74AHCT595 1.5 V 0.5V CC 74AHC_AHCT595 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved Product data sheet Rev. 5 — 4 July 2012 14 of 22

74AHC595; 74AHCT595 Nexperia 8-bit serial-in/serial-out or parallel-out shift register with output latches tW VI 90 % negative pulse VM VM 10 % 0 V tf tr tr tf VI 90 % positive pulse VM VM 10 % 0 V tW VCC VCC VI VO RL S1 G DUT open RT CL 001aad983 Test data is given in Table9. Definitions for test circuit: CL = load capacitance including jig and probe capacitance. RL = load resistance. R = termination resistance should be equal to the output impedance Z of the pulse generator. T o S1 = test selection switch. Fig 13. Load circuitry for switching times Table 9. Test data Type Input Load S1 position V t, t C R t , t t , t t , t I r f L L PHL PLH PZH PHZ PZL PLZ 74AHC595 V 3.0ns 15pF, 50pF 1k open GND V CC CC 74AHCT595 3.0V 3.0ns 15pF, 50pF 1k open GND V CC 74AHC_AHCT595 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved Product data sheet Rev. 5 — 4 July 2012 15 of 22

74AHC595; 74AHCT595 Nexperia 8-bit serial-in/serial-out or parallel-out shift register with output latches 13. Package outline SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE v M A Z 16 9 Q A2 A1 (A 3 ) A pin 1 index θ Lp 1 8 L e w M detail X bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. A1 A2 A3 bp c D(1) E(1) e HE L Lp Q v w y Z(1) θ 0.25 1.45 0.49 0.25 10.0 4.0 6.2 1.0 0.7 0.7 mm 1.75 0.25 1.27 1.05 0.25 0.25 0.1 0.10 1.25 0.36 0.19 9.8 3.8 5.8 0.4 0.6 0.3 8o 0.010 0.057 0.019 0.0100 0.39 0.16 0.244 0.039 0.028 0.028 0o inches 0.069 0.01 0.05 0.041 0.01 0.01 0.004 0.004 0.049 0.014 0.0075 0.38 0.15 0.228 0.016 0.020 0.012 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE REFERENCES EUROPEAN ISSUE DATE VERSION IEC JEDEC JEITA PROJECTION 99-12-27 SOT109-1 076E07 MS-012 03-02-19 Fig 14. Package outline SOT109-1 (SO16) 74AHC_AHCT595 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved Product data sheet Rev. 5 — 4 July 2012 16 of 22

74AHC595; 74AHCT595 Nexperia 8-bit serial-in/serial-out or parallel-out shift register with output latches TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 D E A X c y HE v M A Z 16 9 Q A2 (A 3 ) A pin 1 index A1 θ Lp L 1 8 detail X w M e bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT mAax. A1 A2 A3 bp c D(1) E(2) e HE L Lp Q v w y Z(1) θ mm 1.1 00..1055 00..9850 0.25 00..3109 00..21 54..19 44..53 0.65 66..62 1 00..7550 00..43 0.2 0.13 0.1 00..4006 80oo Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE REFERENCES EUROPEAN ISSUE DATE VERSION IEC JEDEC JEITA PROJECTION 99-12-27 SOT403-1 MO-153 03-02-18 Fig 15. Package outline SOT403-1 (TSSOP16) 74AHC_AHCT595 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved Product data sheet Rev. 5 — 4 July 2012 17 of 22

74AHC595; 74AHCT595 Nexperia 8-bit serial-in/serial-out or parallel-out shift register with output latches DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 16 terminals; body 2.5 x 3.5 x 0.85 mm SOT763-1 D B A A A1 E c terminal 1 detail X index area terminal 1 e1 C index area e b v M C A B y1 C y w M C 2 7 L 1 8 Eh e 16 9 15 10 Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) A(1) UNIT max. A1 b c D(1) Dh E(1) Eh e e1 L v w y y1 0.05 0.30 3.6 2.15 2.6 1.15 0.5 mm 1 0.2 0.5 2.5 0.1 0.05 0.05 0.1 0.00 0.18 3.4 1.85 2.4 0.85 0.3 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE REFERENCES EUROPEAN ISSUE DATE VERSION IEC JEDEC JEITA PROJECTION 02-10-17 SOT763-1 - - - MO-241 - - - 03-01-27 Fig 16. Package outline SOT763-1 (DHVQFN16) 74AHC_AHCT595 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved Product data sheet Rev. 5 — 4 July 2012 18 of 22

74AHC595; 74AHCT595 Nexperia 8-bit serial-in/serial-out or parallel-out shift register with output latches 14. Abbreviations Table 10. Abbreviation s Acronym Description CDM Charged Device Model CMOS Complementary Metal-Oxide Semiconductor ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 15. Revision history T able 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74AHC_AHCT595 v.5 20120704 Product data sheet - 74AHC_AHCT595 v.4 Modifications: • Added GND in the pin configuration drawing DHVQFN16 (errata) 74AHC_AHCT595 v.4 20090811 Product data sheet - 74AHC_AHCT595 v.3 74AHC_AHCT595 v.3 20080425 Product data sheet - 74AHC_AHCT595 v.2 74AHC_AHCT595 v.2 20060323 Product data sheet - 74AHC_AHCT595 v.1 74AHC_AHCT595 v.1 20000315 Product specification - - 74AHC_AHCT595 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved Product data sheet Rev. 5 — 4 July 2012 19 of 22

74AHC595; 74AHCT595 Nexperia 8-bit serial-in/serial-out or parallel-out shift register with output latches 16. Legal information 16.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URLhttp://www.nexperia.com. 16.2 Definitions Suitability for use — Nexperia products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or Draft — The document is a draft version only. The content is still under malfunction of a Nexperia product can reasonably be expected internal review and subject to formal approval, which may result in to result in personal injury, death or severe property or environmental modifications or additions. Nexperia does not give any damage. Nexperia and its suppliers accept no liability for representations or warranties as to the accuracy or completeness of inclusion and/or use of Nexperia products in such equipment or information included herein and shall have no liability for the consequences of applications and therefore such inclusion and/or use is at the customer’s own use of such information. risk. Short data sheet — A short data sheet is an extract from a full data sheet Applications — Applications that are described herein for any of these with the same product type number(s) and title. A short data sheet is intended products are for illustrative purposes only. Nexperia makes no for quick reference only and should not be relied upon to contain detailed and representation or warranty that such applications will be suitable for the full information. For detailed and full information see the relevant full data specified use without further testing or modification. sheet, which is available on request via the local Nexperia sales office. In case of any inconsistency or conflict with the short data sheet, the Customers are responsible for the design and operation of their applications full data sheet shall prevail. and products using Nexperia products, and Nexperia accepts no liability for any assistance with applications or customer product Product specification — The information and data provided in a Product design. It is customer’s sole responsibility to determine whether the Nexperia data sheet shall define the specification of the product as agreed between product is suitable and fit for the customer’s applications and Nexperia and its customer, unless Nexperia and products planned, as well as for the planned application and use of customer have explicitly agreed otherwise in writing. In no event however, customer’s third party customer(s). Customers should provide appropriate shall an agreement be valid in which the Nexperia product is design and operating safeguards to minimize the risks associated with their deemed to offer functions and qualities beyond those described in the applications and products. Product data sheet. Nexperia does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the 16.3 Disclaimers customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using Nexperia Limited warranty and liability — Information in this document is believed to products in order to avoid a default of the applications and be accurate and reliable. However, Nexperia does not give any the products or of the application or use by customer’s third party representations or warranties, expressed or implied, as to the accuracy or customer(s). Nexperia does not accept any liability in this respect. completeness of such information and shall have no liability for the consequences of use of such information. Nexperia takes no Limiting values — Stress above one or more limiting values (as defined in responsibility for the content in this document if provided by an information the Absolute Maximum Ratings System of IEC60134) will cause permanent source outside of Nexperia. damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in In no event shall Nexperia be liable for any indirect, incidental, the Recommended operating conditions section (if present) or the punitive, special or consequential damages (including - without limitation - lost Characteristics sections of this document is not warranted. Constant or profits, lost savings, business interruption, costs related to the removal or repeated exposure to limiting values will permanently and irreversibly affect replacement of any products or rework charges) whether or not such the quality and reliability of the device. damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Terms and conditions of commercial sale — Nexperia products are sold subject to the general terms and conditions of commercial Notwithstanding any damages that customer might incur for any reason whatsoever, Nexperia’s aggregate and cumulative liability towards sale, as published at http://www.nexperia.com/profile/terms, unless otherwise customer for the products described herein shall be limited in accordance agreed in a valid written individual agreement. In case an individual with the Terms and conditions of commercial sale of Nexperia. agreement is concluded only the terms and conditions of the respective agreement shall apply. Nexperia hereby expressly objects to Right to make changes — Nexperia reserves the right to make applying the customer’s general terms and conditions with regard to the changes to information published in this document, including without purchase of Nexperia products by customer. limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior No offer to sell or license — Nothing in this document may be interpreted or to the publication hereof. construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 74AHC_AHCT595 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved Product data sheet Rev. 5 — 4 July 2012 20 of 22

74AHC595; 74AHCT595 Nexperia 8-bit serial-in/serial-out or parallel-out shift register with output latches Export control — This document as well as the item(s) described herein Nexperia’s specifications such use shall be solely at customer’s may be subject to export control regulations. Export might require a prior own risk, and (c) customer fully indemnifies Nexperia for any authorization from competent authorities. liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond Nexperia’s Non-automotive qualified products — Unless this data sheet expressly standard warranty and Nexperia’s product specifications. states that this specific Nexperia product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested Translations — A non-English (translated) version of a document is for in accordance with automotive testing or application requirements. Nexperia reference only. The English version shall prevail in case of any discrepancy accepts no liability for inclusion and/or use of between the translated and English versions. non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in 16.4 Trademarks automotive applications to automotive specifications and standards, customer (a) shall use the product without Nexperia’s warranty of the Notice: All referenced brands, product names, service names and trademarks product for such automotive applications, use and specifications, and (b) are the property of their respective owners. whenever customer uses the product for automotive applications beyond 17. Contact information For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com 74AHC_AHCT595 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved Product data sheet Rev. 5 — 4 July 2012 21 of 22

74AHC595; 74AHCT595 Nexperia 8-bit serial-in/serial-out or parallel-out shift register with output latches 18. Contents 1 General description. . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 Ordering information. . . . . . . . . . . . . . . . . . . . . 2 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 Functional description . . . . . . . . . . . . . . . . . . . 5 8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6 9 Recommended operating conditions. . . . . . . . 6 10 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7 11 Dynamic characteristics. . . . . . . . . . . . . . . . . . 9 12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 13 Package outline. . . . . . . . . . . . . . . . . . . . . . . . 16 14 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 19 15 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 19 16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 20 16.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 20 16.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 16.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 20 16.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 21 17 Contact information. . . . . . . . . . . . . . . . . . . . . 21 18 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 © Nexperia B.V. 2017. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 04 July 2012