74AHC30; 74AHCT30 8-input NAND gate Rev. 5 — 6 May 2020 Product data sheet 1. General description The 74AHC30; 74AHCT30 is a high-speed Si-gate CMOS device and is pin compatible with Low- power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A. The 74AHC30; 74AHCT30 provides an 8-input NAND function. 2. Features and benefits • Balanced propagation delays • All inputs have Schmitt-trigger actions • Inputs accept voltages higher than V CC • Input levels: • For 74AHC30: CMOS level • For 74AHCT30: TTL level • ESD protection: • HBM JESD22-A114E exceeds 2000 V • MM JESD22-A115-A exceeds 200 V • CDM JESD22-C101C exceeds 1000 V • Multiple package options • Specified from -40 °C to +85 °C and -40 °C to +125 °C 3. Ordering information Table 1. Ordering information Type number Package Temperature Name Description Version range 74AHC30D -40 °C to +125 °C SO14 plastic small outline package; 14 leads; SOT108-1 body width 3.9 mm 74AHCT30D 74AHC30PW -40 °C to +125 °C TSSOP14 plastic thin shrink small outline package; 14 leads; SOT402-1 body width 4.4 mm 74AHCT30PW 74AHC30BQ -40 °C to +125 °C DHVQFN14 plastic dual in-line compatible thermal SOT762-1 enhanced very thin quad flat package; no leads; 74AHCT30BQ 14 terminals; body 2.5 × 3 × 0.85 mm 74AHC30GU12 -40 °C to +125 °C XQFN12 plastic, extremely thin quad flat package; no leads; SOT1174-1 12 terminals; body 1.70 × 2.0 × 0.50 mm

Nexperia 74AHC30; 74AHCT30 8-input NAND gate 4. Marking Table 2. Marking codes Type number Marking 74AHC30D 74AHC30D 74AHCT30D 74AHCT30D 74AHC30PW AHC30 74AHCT30PW AHCT30 74AHC30BQ AHC30 74AHCT30BQ AHT30 74AHC30GU12 A3 [1] [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram 1 A 1 & 2 B 2 3 C 3 4 D Y 8 4 5 E 8 5 6 F 6 11 G 11 12 H 12 mna488 mna489 Pin numbers are shown for SO14, TSSOP14 and Pin numbers are shown for SO14, TSSOP14 and DHVQFN14 packages only DHVQFN14 packages only Fig. 1. Logic symbol Fig. 2. IEC logic symbol A B C D Y E mna490 F G H Fig. 3. Logic diagram 74AHC_AHCT30 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2020. All rights reserved Product data sheet Rev. 5 — 6 May 2020 2 / 16

Nexperia 74AHC30; 74AHCT30 8-input NAND gate 6. Pinning information 6.1. Pinning 74AHC30 74AHCT30 C terminal 1 C A V index area 1 14 B 2 13 n.c. C 3 12 H 74AHC30 D 4 11 G 74AHCT30 E 5 GND(1) 10 n.c. A 1 14 VCC F 6 9 n.c. 7 8 B 2 13 n.c. D Y C 3 12 H GN 001aak237 D 4 11 G Transparent top view E 5 10 n.c. (1) This is not a ground pin. There is no electrical or F 6 9 n.c. mechanical requirement to solder the pad. In case GND 7 8 Y soldered, the solder land should remain floating or 001aai162 connected to GND Fig. 4. Pin configuration SO14 and TSSOP14 Fig. 5. Pin configuration DHVQFN14 74AHC30 C terminal 1 C index area V 2 A 1 1 11 n.c. B 2 10 H C 3 9 G D 4 8 Y E 5 7 F 6 D aaa-016961 N G Transparent top view Fig. 6. Pin configuration XQFN12 (SOT1174-1) 74AHC_AHCT30 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2020. All rights reserved Product data sheet Rev. 5 — 6 May 2020 3 / 16

Nexperia 74AHC30; 74AHCT30 8-input NAND gate 6.2. Pin description Table 3. Pin description Symbol Pin Description SO14, TSSOP14 and DHVQFN14 XQFN12 A 1 1 data input B 2 2 data input C 3 3 data input D 4 4 data input E 5 5 data input F 6 7 data input GND 7 6 ground (0 V) Y 8 8 data output n.c. 9 - not connected n.c. 10 - not connected G 11 9 data input H 12 10 data input n.c. 13 11 not connected V 14 12 supply voltage CC 7. Functional description Table 4. Function table H = HIGH voltage level; L = LOW voltage level; X = don’t care. Input Output A B C D E F G H Y L X X X X X X X H X L X X X X X X H X X L X X X X X H X X X L X X X X H X X X X L X X X H X X X X X L X X H X X X X X X L X H X X X X X X X L H H H H H H H H H L 74AHC_AHCT30 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2020. All rights reserved Product data sheet Rev. 5 — 6 May 2020 4 / 16

Nexperia 74AHC30; 74AHCT30 8-input NAND gate 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit V supply voltage -0.5 +7.0 V CC V input voltage -0.5 +7.0 V I I input clamping current V < -0.5 V [1] -20 - mA IK I I output clamping current V < -0.5 V or V > V + 0.5 V [1] -20 +20 mA OK O O CC I output current V = -0.5 V to (V + 0.5 V) -25 +25 mA O O CC I supply current - +75 mA CC I ground current -75 - mA GND T storage temperature -65 +150 °C stg P total power dissipation T = -40 °C to +125 °C tot amb SO14, TSSOP14 and DHVQFN14 [2] - 500 mW XQFN12 - 250 mW [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] For SOT108-1 (SO14) package: Ptot derates linearly with 10.1 mW/K above 100 °C. For SOT402-1 (TSSOP14) package: Ptot derates linearly with 7.3 mW/K above 81 °C. For SOT762-1 (DHVQFN14) package: Ptot derates linearly with 9.6 mW/K above 98 °C. 9. Recommended operating conditions Table 6. Recommended operating conditions Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 74AHC30 74AHCT30 Unit Min Typ Max Min Typ Max V supply voltage 2.0 5.0 5.5 4.5 5.0 5.5 V CC V input voltage 0 - 5.5 0 - 5.5 V I V output voltage 0 - V 0 - V V O CC CC T ambient temperature -40 +25 +125 -40 +25 +125 °C amb Δt/ΔV input transition rise V = 3.3 V ± 0.3 V - - 100 - - - ns/V CC and fall rate V = 5.0 V ± 0.5 V - - 20 - - 20 ns/V CC 74AHC_AHCT30 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2020. All rights reserved Product data sheet Rev. 5 — 6 May 2020 5 / 16

Nexperia 74AHC30; 74AHCT30 8-input NAND gate 10. Static characteristics Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 25 °C -40 °C to +85 °C -40 °C to +125 °C Unit Min Typ Max Min Max Min Max 74AHC30 V HIGH-level V = 2.0 V 1.5 - - 1.5 - 1.5 - V IH CC input voltage V = 3.0 V 2.1 - - 2.1 - 2.1 - V CC V = 5.5 V 3.85 - - 3.85 - 3.85 - V CC V LOW-level V = 2.0 V - - 0.5 - 0.5 - 0.5 V IL CC input voltage V = 3.0 V - - 0.9 - 0.9 - 0.9 V CC V = 5.5 V - - 1.65 - 1.65 - 1.65 V CC V HIGH-level V = V or V OH I IH IL output voltage I = -50 μA; V = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V O CC I = -50 μA; V = 3.0 V 2.9 3.0 - 2.9 - 2.9 - V O CC I = -50 μA; V = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V O CC I = -4.0 mA; V = 3.0 V 2.58 - - 2.48 - 2.40 - V O CC I = -8.0 mA; V = 4.5 V 3.94 - - 3.80 - 3.70 - V O CC V LOW-level V = V or V OL I IH IL output voltage I = 50 μA; V = 2.0 V - 0 0.1 - 0.1 - 0.1 V O CC I = 50 μA; V = 3.0 V - 0 0.1 - 0.1 - 0.1 V O CC I = 50 μA; V = 4.5 V - 0 0.1 - 0.1 - 0.1 V O CC I = 4.0 mA; V = 3.0 V - - 0.36 - 0.44 - 0.55 V O CC I = 8.0 mA; V = 4.5 V - - 0.36 - 0.44 - 0.55 V O CC I input leakage V = 5.5 V or GND; - - 0.1 - 1.0 - 2.0 μA I I current V = 0 V to 5.5 V CC I supply current V = V or GND; I = 0 A; - - 2.0 - 20 - 40 μA CC I CC O V = 5.5 V CC C input V = V or GND - 3 10 - 10 - 10 pF I I CC capacitance C output - 4 - - - - - pF O capacitance 74AHC_AHCT30 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2020. All rights reserved Product data sheet Rev. 5 — 6 May 2020 6 / 16

Nexperia 74AHC30; 74AHCT30 8-input NAND gate Symbol Parameter Conditions 25 °C -40 °C to +85 °C -40 °C to +125 °C Unit Min Typ Max Min Max Min Max 74AHCT30 V HIGH-level V = 4.5 V to 5.5 V 2.0 - - 2.0 - 2.0 - V IH CC input voltage V LOW-level V = 4.5 V to 5.5 V - - 0.8 - 0.8 - 0.8 V IL CC input voltage V HIGH-level V = V or V ; V = 4.5 V OH I IH IL CC output voltage I = -50 μA 4.4 4.5 - 4.4 - 4.4 - V O I = -8.0 mA 3.94 - - 3.80 - 3.70 - V O V LOW-level V = V or V ; V = 4.5 V OL I IH IL CC output voltage I = 50 μA - 0 0.1 - 0.1 - 0.1 V O I = 8.0 mA - - 0.36 - 0.44 - 0.55 V O I input leakage V = 5.5 V or GND; - - 0.1 - 1.0 - 2.0 μA I I current V = 0 V to 5.5 V CC I supply current V = V or GND; I = 0 A; - - 2.0 - 20 - 40 μA CC I CC O V = 5.5 V CC ΔI additional per input pin; - - 1.35 - 1.5 - 1.5 mA CC supply current V = V - 2.1 V; other pins I CC at V or GND; I = 0 A; CC O V = 4.5 V to 5.5 V CC C input V = V or GND - 3 10 - 10 - 10 pF I I CC capacitance C output - 4 - - - - - pF O capacitance 74AHC_AHCT30 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2020. All rights reserved Product data sheet Rev. 5 — 6 May 2020 7 / 16

Nexperia 74AHC30; 74AHCT30 8-input NAND gate 11. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 8. Symbol Parameter Conditions 25 °C -40 °C to +85 °C -40 °C to +125 °C Unit Min Typ[1] Max Min Max Min Max 74AHC30 t propagation A, B, C, D, E, F, G, H to Y; see Fig. 7 and Fig. 8 [2] pd delay V = 3.0 V to 3.6 V CC C = 15 pF - 5.0 9.5 1.0 11.0 1.0 12.0 ns L C = 50 pF - 6.7 12.0 1.0 14.5 1.0 15.5 ns L V = 4.5 V to 5.5 V CC C = 15 pF - 3.6 6.5 1.0 7.5 1.0 8.0 ns L C = 50 pF - 4.9 8.0 1.0 9.5 1.0 10.5 ns L C power f = 1 MHz; [3] - 10 - - - - - pF PD i dissipation V = GND to V I CC capacitance 74AHCT30; V = 4.5 V to 5.5 V CC t propagation A, B, C, D, E, F, G, H to Y; see Fig. 7 and Fig. 8 [2] pd delay C = 15 pF - 3.3 6.5 1.0 7.5 1.0 8.0 ns L C = 50 pF - 4.7 8.5 1.0 9.5 1.0 10.5 ns L C power f = 1 MHz; [3] - 12 - - - - - pF PD i dissipation V = GND to V I CC capacitance [1] Typical values are measured at nominal supply voltage (VCC = 3.3 V and VCC = 5.0 V). [2] tpd is the same as tPLH and tPHL. [3] CPD is used to determine the dynamic power dissipation (PD in μW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; Σ(CL × VCC2 × fo) = sum of the outputs. 74AHC_AHCT30 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2020. All rights reserved Product data sheet Rev. 5 — 6 May 2020 8 / 16

Nexperia 74AHC30; 74AHCT30 8-input NAND gate 11.1. Waveforms VI A, B, C, D, E, F, G, H VM input GND tPHL tPLH VOH Y output VM VOL mna491 Measurement points are given in Table 9. V and V are typical voltage output levels that occur with the output load. OL OH Fig. 7. Input to output propagation delays Table 9. Measurement points Type Input Output V V M M 74AHC30 0.5 × V 0.5 × V CC CC 74AHCT30 1.5 V 0.5 × V CC VI tW 90 % negative pulse VM VM 10 % GND tf tr tr tf VI 90 % positive pulse VM VM 10 % GND tW VCC VI VO G DUT RT CL 001aah768 Test data is given in Table 10. Definitions for test circuit: R = termination resistance should be equal to the output impedance Z of the pulse generator. T o C = load capacitance including jig and probe capacitance. L Fig. 8. Test circuit for measuring switching times Table 10. Test data Type Input Load Test V t, t C I r f L 74AHC30 V ≤ 3.0 ns 15 pF, 50 pF t , t CC PLH PHL 74AHCT30 3.0 V ≤ 3.0 ns 15 pF, 50 pF t , t PLH PHL 74AHC_AHCT30 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2020. All rights reserved Product data sheet Rev. 5 — 6 May 2020 9 / 16

Nexperia 74AHC30; 74AHCT30 8-input NAND gate 12. Package outline SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y H E v M A Z 14 8 Q A 2 A 1 (A 3 ) A pin 1 index θ L p 1 7 L e w M detail X b p 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mAax . A 1 A 2 A 3 b p c D (1) E (1) e H E L L p Q v w y Z (1) θ 0.25 1.45 0.49 0.25 8.75 4.0 6.2 1.0 0.7 0.7 mm 1.75 0.25 1.27 1.05 0.25 0.25 0.1 0.10 1.25 0.36 0.19 8.55 3.8 5.8 0.4 0.6 0.3 8 o 0.010 0.057 0.019 0.0100 0.35 0.16 0.244 0.039 0.028 0.028 0 o inches 0.069 0.01 0.05 0.041 0.01 0.01 0.004 0.004 0.049 0.014 0.0075 0.34 0.15 0.228 0.016 0.024 0.012 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE REFERENCES EUROPEAN ISSUE DATE VERSION IEC JEDEC JEITA PROJECTION 99-12-27 SOT108-1 076E06 MS-012 03-02-19 Fig. 9. Package outline SOT108-1 (SO14) 74AHC_AHCT30 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2020. All rights reserved Product data sheet Rev. 5 — 6 May 2020 10 / 16

Nexperia 74AHC30; 74AHCT30 8-input NAND gate TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 D E A X c y H E v M A Z 14 8 Q A 2 (A 3 ) A pin 1 index A 1 θ L p L 1 7 detail X w M e b p 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT mAax . A 1 A 2 A 3 b p c D (1) E (2) e H E L L p Q v w y Z (1) θ 0.15 0.95 0.30 0.2 5.1 4.5 6.6 0.75 0.4 0.72 8 o mm 1.1 0.05 0.80 0.25 0.19 0.1 4.9 4.3 0.65 6.2 1 0.50 0.3 0.2 0.13 0.1 0.38 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE REFERENCES EUROPEAN ISSUE DATE VERSION IEC JEDEC JEITA PROJECTION 99-12-27 SOT402-1 MO-153 03-02-18 Fig. 10. Package outline SOT402-1 (TSSOP14) 74AHC_AHCT30 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2020. All rights reserved Product data sheet Rev. 5 — 6 May 2020 11 / 16

Nexperia 74AHC30; 74AHCT30 8-input NAND gate DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.5 x 3 x 0.85 mm SOT762-1 D B A A A1 E c terminal 1 detail X index area terminal 1 C e1 index area e b v C A B y1C y w C 2 6 L 1 7 Eh e 14 8 k 13 9 Dh X k 0 2 4 mm scale Dimensions (mm are the original dimensions) Unit A(1) A1 b c D(1) Dh E(1) Eh e e1 k L v w y y1 max 1 0.05 0.30 3.1 1.65 2.6 1.15 0.5 mm nom 0.02 0.25 0.2 3.0 1.50 2.5 1.00 0.5 2 0.4 0.1 0.05 0.05 0.1 min 0.00 0.18 2.9 1.35 2.4 0.85 0.2 0.3 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. sot762-1_po Outline References European Issue date version IEC JEDEC JEITA projection 15-04-10 SOT762-1 MO-241 15-05-05 Fig. 11. Package outline SOT762-1 (DHVQFN14) 74AHC_AHCT30 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2020. All rights reserved Product data sheet Rev. 5 — 6 May 2020 12 / 16

Nexperia 74AHC30; 74AHCT30 8-input NAND gate XQFN12: plastic, extremely thin quad flat package; no leads; 12 terminals; body 1.70 x 2.00 x 0.50 mm SOT1174-1 X D B A terminal 1 index area E A A1 A3 detail X C ∅ v C A B b ∅ w C y1C y 5 7 e1 e 1 11 terminal 1 index area L1 L 0 1 2 mm scale Dimensions Unit(1) A A1 A3 b D E e e1 L L1 v w y y1 max 0.5 0.05 0.25 1.8 2.1 0.55 mm nom 0.127 0.20 1.7 2.0 0.4 1.6 0.50 0.15 0.1 0.05 0.05 0.05 min 0.00 0.15 1.6 1.9 0.45 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. sot1174-1_po Outline References European Issue date version IEC JEDEC JEITA projection 10-04-07 SOT1174-1 - - - MO-288 - - - 10-04-21 Fig. 12. Package outline SOT1174-1 (XQFN12) 74AHC_AHCT30 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2020. All rights reserved Product data sheet Rev. 5 — 6 May 2020 13 / 16

Nexperia 74AHC30; 74AHCT30 8-input NAND gate 13. Abbreviations Table 11. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model LSTTL Low-power Schottky Transistor-Transistor Logic MM Machine Model 14. Revision history Table 12. Revision history Document ID Release date Data sheet status Change notice Supersedes 74AHC_AHCT30 v.5 20200506 Product data sheet - 74AHC_AHCT30 v.4 Modifications: • The format of this data sheet has been redesigned to comply with the identity guidelines of Nexperia. • Legal texts have been adapted to the new company name where appropriate. • Table 5: Derating values for P total power dissipation have been updated. tot 74AHC_AHCT30 v.4 20150722 Product data sheet - 74AHC_AHCT30 v.3 Modifications: • Added type number 74AHC30GU12. 74AHC_AHCT30 v.3 20090626 Product data sheet - 74AHC_AHCT30 v.2 Modifications: • Section 3: DHVQFN14 package added. • Section 8: derating values added for DHVQFN14 package. • Section 12: outline drawing added for DHVQFN14 package. 74AHC_AHCT30 v.2 20080530 Product data sheet - 74AHC_AHCT30 v.1 74AHC_AHCT30 v.1 19991130 Product specification - - 74AHC_AHCT30 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2020. All rights reserved Product data sheet Rev. 5 — 6 May 2020 14 / 16

Nexperia 74AHC30; 74AHCT30 8-input NAND gate injury, death or severe property or environmental damage. Nexperia and its 15. Legal information suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Quick reference data — The Quick reference data is an extract of the Data sheet status product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Document status Product Definition Applications — Applications that are described herein for any of these [1][2] status [3] products are for illustrative purposes only. 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Nexperia 74AHC30; 74AHCT30 8-input NAND gate Contents 1. General description......................................................1 2. Features and benefits..................................................1 3. Ordering information....................................................1 4. Marking..........................................................................2 5. Functional diagram.......................................................2 6. Pinning information......................................................3 6.1. Pinning.........................................................................3 6.2. Pin description.............................................................4 7. Functional description.................................................4 8. Limiting values.............................................................5 9. Recommended operating conditions..........................5 10. Static characteristics..................................................6 11. Dynamic characteristics.............................................8 11.1. Waveforms.................................................................9 12. Package outline........................................................10 13. Abbreviations............................................................14 14. Revision history........................................................14 15. Legal information......................................................15 © Nexperia B.V. 2020. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 6 May 2020 74AHC_AHCT30 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2020. All rights reserved Product data sheet Rev. 5 — 6 May 2020 16 / 16