74AHC02; 74AHCT02 Quad 2-input NOR gate Rev. 5 — 11 May 2020 Product data sheet 1. General description The 74AHC02; 74AHCT02 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A. The 74AHC02; 74AHCT02 provides a quad 2-input NOR function. 2. Features and benefits • Balanced propagation delays • All inputs have a Schmitt-trigger action • Inputs accept voltages higher than V CC • Input levels: • For 74AHC02: CMOS level • For 74AHCT02: TTL level • ESD protection: • HBM EIA/JESD22-A114E exceeds 2000 V • MM EIA/JESD22-A115-A exceeds 200 V • CDM EIA/JESD22-C101C exceeds 1000 V • Multiple package options • Specified from -40 °C to +85 °C and from -40 °C to +125 °C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AHC02D -40 °C to +125 °C SO14 plastic small outline package; 14 leads; SOT108-1 body width 3.9 mm 74AHCT02D 74AHC02PW -40 °C to +125 °C TSSOP14 plastic thin shrink small outline package; 14 leads; SOT402-1 body width 4.4 mm 74AHCT02PW 74AHC02BQ -40 °C to +125 °C DHVQFN14 plastic dual in-line compatible thermal enhanced SOT762-1 very thin quad flat package; no leads; 14 terminals; 74AHCT02BQ body 2.5 × 3 × 0.85 mm

Nexperia 74AHC02; 74AHCT02 Quad 2-input NOR gate 4. Functional diagram 2 2 1A 1Y 1 3 ≥1 1 3 1B 5 2A 5 2Y 4 ≥1 4 6 2B 6 8 3A 8 9 3B 3Y 10 9 ≥1 10 A 11 4A 4Y 13 11 Y 12 4B ≥1 13 12 B mna216 001aah084 mna215 Fig. 1. Logic symbol Fig. 2. IEC logic symbol Fig. 3. Logic diagram (one gate) 5. Pinning information 5.1. Pinning C terminal 1 Y C 1 V index area 1 14 1A 2 13 4Y 1B 3 12 4B 2Y 4 02 11 4A 2A 5 GND(1) 10 3Y 1Y 1 14 VCC 2B 6 9 3B 1A 2 13 4Y 7 8 1B 3 12 4B D A 2Y 4 02 11 4A GN 3 001aac920 2A 5 10 3Y Transparent top view 2B 6 9 3B (1) This is not a ground pin. There is no electrical or GND 7 8 3A mechanical requirement to solder the pad. In case 001aac919 soldered, the solder land should remain floating or connected to GND. Fig. 4. Pin configuration SOT108-1 (SO14) and SOT402-1 (TSSOP14) Fig. 5. Pin configuration SOT762-1 (DHVQFN14) 5.2. Pin description Table 2. Pin description Symbol Pin Description 1Y, 2Y, 3Y, 4Y 1, 4, 10, 13 data output 1A, 2A, 3A, 4A 2, 5, 8, 11 data input 1B, 2B, 3B, 4B 3, 6, 9, 12 data input GND 7 ground (0 V) V 14 supply voltage CC 74AHC_AHCT02 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2020. All rights reserved Product data sheet Rev. 5 — 11 May 2020 2 / 12

Nexperia 74AHC02; 74AHCT02 Quad 2-input NOR gate 6. Functional description Table 3. Function table H = HIGH voltage level; L = LOW voltage level; X = don’t care. Input Output nA nB nY L L H X H L H X L 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit V supply voltage -0.5 +7.0 V CC V input voltage -0.5 +7.0 V I I input clamping current V < -0.5 V [1] -20 - mA IK I I output clamping current V < -0.5 V or V > V + 0.5 V [1] -20 +20 mA OK O O CC I output current V = -0.5 V to (V + 0.5 V) -25 +25 mA O O CC I supply current - +75 mA CC I ground current -75 - mA GND T storage temperature -65 +150 °C stg P total power dissipation T = -40 °C to +125 °C [2] - 500 mW tot amb [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] For SOT108-1 (SO14) package: Ptot derates linearly with 10.1 mW/K above 100 °C. For SOT402-1 (TSSOP14) package: Ptot derates linearly with 7.3 mW/K above 81 °C. For SOT762-1 (DHVQFN14) package: Ptot derates linearly with 9.6 mW/K above 98 °C. 8. Recommended operating conditions Table 5. Operating conditions Symbol Parameter Conditions 74AHC02 74AHCT02 Unit Min Typ Max Min Typ Max V supply voltage 2.0 5.0 5.5 4.5 5.0 5.5 V CC V input voltage 0 - 5.5 0 - 5.5 V I V output voltage 0 - V 0 - V V O CC CC T ambient temperature -40 +25 +125 -40 +25 +125 °C amb Δt/ΔV input transition rise and fall rate V = 3.0 V to 3.6 V - - 100 - - - ns/V CC V = 4.5 V to 5.5 V - - 20 - - 20 ns/V CC 74AHC_AHCT02 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2020. All rights reserved Product data sheet Rev. 5 — 11 May 2020 3 / 12

Nexperia 74AHC02; 74AHCT02 Quad 2-input NOR gate 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 25 °C -40 °C to -40 °C to Unit +85 °C +125 °C Min Typ Max Min Max Min Max 74AHC02 V HIGH-level V = 2.0 V 1.5 - - 1.5 - 1.5 - V IH CC input voltage V = 3.0 V 2.1 - - 2.1 - 2.1 - V CC V = 5.5 V 3.85 - - 3.85 - 3.85 - V CC V LOW-level V = 2.0 V - - 0.5 - 0.5 - 0.5 V IL CC input voltage V = 3.0 V - - 0.9 - 0.9 - 0.9 V CC V = 5.5 V - - 1.65 - 1.65 - 1.65 V CC V HIGH-level V = V or V OH I IH IL output voltage I = -50 μA; V = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V O CC I = -50 μA; V = 3.0 V 2.9 3.0 - 2.9 - 2.9 - V O CC I = -50 μA; V = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V O CC I = -4.0 mA; V = 3.0 V 2.58 - - 2.48 - 2.40 - V O CC I = -8.0 mA; V = 4.5 V 3.94 - - 3.80 - 3.70 - V O CC V LOW-level V = V or V OL I IH IL output voltage I = 50 μA; V = 2.0 V - 0 0.1 - 0.1 - 0.1 V O CC I = 50 μA; V = 3.0 V - 0 0.1 - 0.1 - 0.1 V O CC I = 50 μA; V = 4.5 V - 0 0.1 - 0.1 - 0.1 V O CC I = 4.0 mA; V = 3.0 V - - 0.36 - 0.44 - 0.55 V O CC I = 8.0 mA; V = 4.5 V - - 0.36 - 0.44 - 0.55 V O CC I input leakage V = 5.5 V or GND; - - 0.1 - 1.0 - 2.0 μA I I current V = 0 V to 5.5 V CC I supply current V = V or GND; I = 0 A; - - 2.0 - 20 - 40 μA CC I CC O V = 5.5 V CC C input - 3 10 - 10 - 10 pF I capacitance 74AHCT02 V HIGH-level V = 4.5 V to 5.5 V 2.0 - - 2.0 - 2.0 - V IH CC input voltage V LOW-level V = 4.5 V to 5.5 V - - 0.8 - 0.8 - 0.8 V IL CC input voltage V HIGH-level V = V or V ; V = 4.5 V OH I IH IL CC output voltage I = -50 μA 4.4 4.5 - 4.4 - 4.4 - V O I = -8.0 mA 3.94 - - 3.80 - 3.70 - V O V LOW-level V = V or V ; V = 4.5 V OL I IH IL CC output voltage I = 50 μA - 0 0.1 - 0.1 - 0.1 V O I = 8.0 mA - - 0.36 - 0.44 - 0.55 V O 74AHC_AHCT02 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2020. All rights reserved Product data sheet Rev. 5 — 11 May 2020 4 / 12

Nexperia 74AHC02; 74AHCT02 Quad 2-input NOR gate Symbol Parameter Conditions 25 °C -40 °C to -40 °C to Unit +85 °C +125 °C Min Typ Max Min Max Min Max I input leakage V = 5.5 V or GND; - - 0.1 - 1.0 - 2.0 μA I I current V = 0 V to 5.5 V CC I supply current V = V or GND; I = 0 A; - - 2.0 - 20 - 40 μA CC I CC O V = 5.5 V CC ΔI additional per input pin; V = V - 2.1 V; - - 1.35 - 1.5 - 1.5 mA CC I CC supply current other pins at V or GND; CC I = 0 A; V = 4.5 V to 5.5 V O CC C input - 3 10 - 10 - 10 pF I capacitance 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 7. Symbol Parameter Conditions 25 °C -40 °C to -40 °C to Unit +85 °C +125 °C Min Typ[1] Max Min Max Min Max 74AHC02 t propagation nA, nB to nY; see Fig. 6 [2] pd delay V = 3.0 V to 3.6 V; C = 15 pF - 3.9 7.9 1.0 9.5 1.0 10.0 ns CC L V = 3.0 V to 3.6 V; C = 50 pF - 5.5 11.4 1.0 13 1.0 14.5 ns CC L V = 4.5 V to 5.5 V; C = 15 pF - 2.9 5.5 1.0 6.5 1.0 7.0 ns CC L V = 4.5 V to 5.5 V; C = 50 pF - 4.2 7.5 1.0 8.5 1.0 9.5 ns CC L C power C = 50 pF; f = 1 MHz; [3] - 7.0 - - - - - pF PD L i dissipation V = GND to V I CC capacitance 74AHCT02 t propagation nA, nB to nY; see Fig. 6 [2] pd delay V = 4.5 V to 5.5 V; C = 15 pF - 3.8 5.5 1.0 6.5 1.0 7.0 ns CC L V = 4.5 V to 5.5 V; C = 50 pF - 5.1 7.5 1.0 8.5 1.0 9.5 ns CC L C power C = 50 pF; f = 1 MHz; [3] - 8.0 - - - - - pF PD L i dissipation V = GND to V I CC capacitance [1] Typical values are measured at nominal supply voltage (VCC = 3.3 V and VCC = 5.0 V). [2] tpd is the same as tPLH and tPHL. [3] CPD is used to determine the dynamic power dissipation (PD in μW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; Σ(CL × VCC2 × fo) = sum of the outputs. 74AHC_AHCT02 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2020. All rights reserved Product data sheet Rev. 5 — 11 May 2020 5 / 12

Nexperia 74AHC02; 74AHCT02 Quad 2-input NOR gate 10.1. Waveforms VI nA, nB input VM GND tPLH tPHL VOH nY output VM VOL 001aah085 Measurement points are given in Table 8. V and V are typical voltage output levels that occur with the output load. OL OH Fig. 6. Input to output propagation delays Table 8. Measurement points Type Input Output V V M M 74AHC02 0.5 × V 0.5 × V CC CC 74AHCT02 1.5 V 0.5 × V CC VI tW 90 % negative pulse VM VM 10 % GND tf tr tr tf VI 90 % positive pulse VM VM 10 % GND tW VCC VI VO G DUT RT CL 001aah768 Test data is given in Table 9. Definitions test circuit: R = termination resistance should be equal to output impedance Z of the pulse generator. T o C = load capacitance including jig and probe capacitance. L Fig. 7. Test circuit for measuring switching times Table 9. Test data Type Input Load Test V t, t C I r f L 74AHC02 V ≤ 3.0 ns 15 pF, 50 pF t , t CC PLH PHL 74AHCT02 3.0 V ≤ 3.0 ns 15 pF, 50 pF t , t PLH PHL 74AHC_AHCT02 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2020. All rights reserved Product data sheet Rev. 5 — 11 May 2020 6 / 12

Nexperia 74AHC02; 74AHCT02 Quad 2-input NOR gate 11. Package outline SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y H E v M A Z 14 8 Q A 2 A 1 (A 3 ) A pin 1 index θ L p 1 7 L e w M detail X b p 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mAax . A 1 A 2 A 3 b p c D (1) E (1) e H E L L p Q v w y Z (1) θ 0.25 1.45 0.49 0.25 8.75 4.0 6.2 1.0 0.7 0.7 mm 1.75 0.25 1.27 1.05 0.25 0.25 0.1 0.10 1.25 0.36 0.19 8.55 3.8 5.8 0.4 0.6 0.3 8 o 0.010 0.057 0.019 0.0100 0.35 0.16 0.244 0.039 0.028 0.028 0 o inches 0.069 0.01 0.05 0.041 0.01 0.01 0.004 0.004 0.049 0.014 0.0075 0.34 0.15 0.228 0.016 0.024 0.012 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE REFERENCES EUROPEAN ISSUE DATE VERSION IEC JEDEC JEITA PROJECTION 99-12-27 SOT108-1 076E06 MS-012 03-02-19 Fig. 8. Package outline SOT108-1 (SO14) 74AHC_AHCT02 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2020. All rights reserved Product data sheet Rev. 5 — 11 May 2020 7 / 12

Nexperia 74AHC02; 74AHCT02 Quad 2-input NOR gate TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 D E A X c y H E v M A Z 14 8 Q A 2 (A 3 ) A pin 1 index A 1 θ L p L 1 7 detail X w M e b p 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT mAax . A 1 A 2 A 3 b p c D (1) E (2) e H E L L p Q v w y Z (1) θ 0.15 0.95 0.30 0.2 5.1 4.5 6.6 0.75 0.4 0.72 8 o mm 1.1 0.05 0.80 0.25 0.19 0.1 4.9 4.3 0.65 6.2 1 0.50 0.3 0.2 0.13 0.1 0.38 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE REFERENCES EUROPEAN ISSUE DATE VERSION IEC JEDEC JEITA PROJECTION 99-12-27 SOT402-1 MO-153 03-02-18 Fig. 9. Package outline SOT402-1 (TSSOP14) 74AHC_AHCT02 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2020. All rights reserved Product data sheet Rev. 5 — 11 May 2020 8 / 12

Nexperia 74AHC02; 74AHCT02 Quad 2-input NOR gate DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.5 x 3 x 0.85 mm SOT762-1 D B A A A1 E c terminal 1 detail X index area terminal 1 C e1 index area e b v C A B y1C y w C 2 6 L 1 7 Eh e 14 8 k 13 9 Dh X k 0 2 4 mm scale Dimensions (mm are the original dimensions) Unit A(1) A1 b c D(1) Dh E(1) Eh e e1 k L v w y y1 max 1 0.05 0.30 3.1 1.65 2.6 1.15 0.5 mm nom 0.02 0.25 0.2 3.0 1.50 2.5 1.00 0.5 2 0.4 0.1 0.05 0.05 0.1 min 0.00 0.18 2.9 1.35 2.4 0.85 0.2 0.3 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. sot762-1_po Outline References European Issue date version IEC JEDEC JEITA projection 15-04-10 SOT762-1 MO-241 15-05-05 Fig. 10. Package outline SOT762-1 (DHVQFN14) 74AHC_AHCT02 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2020. All rights reserved Product data sheet Rev. 5 — 11 May 2020 9 / 12

Nexperia 74AHC02; 74AHCT02 Quad 2-input NOR gate 12. Abbreviations Table 10. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model LSTTL Low-power Schottky Transistor-Transistor Logic MM Machine Model TTL Transistor-Transistor Logic 13. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74AHC_AHCT02_5 20200511 Product data sheet - 74AHC_AHCT02_4 Modifications: • The format of this data sheet has been redesigned to comply with the identity guidelines of Nexperia. • Legal texts have been adapted to the new company name where appropriate. • Table 4: Derating values for P total power dissipation updated. tot • Package outline drawing SOT762-1 (DHVQFN14) updated. 74AHC_AHCT02_4 20080521 Product data sheet - 74AHC_AHCT02_3 Modifications: • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Table 6: the conditions for input leakage current have been changed. 74AHC_AHCT02_3 20080107 Product data sheet - 74AHC_AHCT02_2 74AHC_AHCT02_2 19990923 Product specification - 74AHC_AHCT02_1 74AHC_AHCT02_1 19981218 Product specification - - 74AHC_AHCT02 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2020. All rights reserved Product data sheet Rev. 5 — 11 May 2020 10 / 12

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Nexperia 74AHC02; 74AHCT02 Quad 2-input NOR gate Contents 1. General description......................................................1 2. Features and benefits..................................................1 3. Ordering information....................................................1 4. Functional diagram.......................................................2 5. Pinning information......................................................2 5.1. Pinning.........................................................................2 5.2. Pin description.............................................................2 6. Functional description.................................................3 7. Limiting values.............................................................3 8. Recommended operating conditions..........................3 9. Static characteristics....................................................4 10. Dynamic characteristics............................................5 10.1. Waveforms.................................................................6 11. Package outline..........................................................7 12. Abbreviations............................................................10 13. Revision history........................................................10 14. Legal information......................................................11 © Nexperia B.V. 2020. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 11 May 2020 74AHC_AHCT02 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2020. All rights reserved Product data sheet Rev. 5 — 11 May 2020 12 / 12