SN54ACT16244, 74ACT16244 16-BIT BUFFERS/LINE DRIVERS WITH 3-STATE OUTPUTS SCAS116B – MARCH 1990 – REVISED APRIL 1996 (cid:1) Members of the Texas Instruments SN54ACT16244...WD PACKAGE Widebus Family 74ACT16244...DGG OR DL PACKAGE (cid:1) (TOP VIEW) Inputs Are TTL-Voltage Compatible (cid:1) 3-State Outputs Drive Bus Lines or Buffer 1OE 1 48 2OE Memory Address Registers 1Y1 2 47 1A1 (cid:1) Flow-Through Architecture Optimizes 1Y2 3 46 1A2 PCB Layout GND 4 45 GND (cid:1) Distributed V and GND Pin 1Y3 5 44 1A3 CC Configurations Minimize High-Speed 1Y4 6 43 1A4 Switching Noise VCC 7 42 VCC (cid:1) EPIC (Enhanced-Performance Implanted 2Y1 8 41 2A1 2Y2 9 40 2A2 CMOS) 1-(cid:1)m Process (cid:1) GND 10 39 GND 500-mA Typical Latch-Up Immunity at 2Y3 11 38 2A3 125°C 2Y4 12 37 2A4 (cid:1) Package Options Include Plastic Shrink 3Y1 13 36 3A1 Small-Outline (DL) and Thin Shrink 3Y2 14 35 3A2 Small-Outline (DGG) Packages, and 380-mil GND 15 34 GND Fine-Pitch Ceramic Flat (WD) Packages 3Y3 16 33 3A3 Using 25-mil Center-to-Center Pin Spacings 3Y4 17 32 3A4 description VCC 18 31 VCC 4Y1 19 30 4A1 The SN54ACT16244 and 74ACT16244 are 16-bit 4Y2 20 29 4A2 buffers/line drivers designed specifically to GND 21 28 GND improve both the performance and density of 4Y3 22 27 4A3 3-state memory address drivers, clock drivers, 4Y4 23 26 4A4 and bus-oriented receivers and transmitters. 4OE 24 25 3OE They can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. The devices provide true outputs and symmetrical OE (active-low) output-enable inputs. The 74ACT16244 is packaged in TI’s shrink small-outline package, which provides twice the I/O pin count and functionality of standard small-outline packages in the same printed-circuit-board area. The SN54ACT16244 is characterized for operation over the full military temperature range of –55°C to 125°C. The 74ACT16244 is characterized for operation from –40°C to 85°C. FUNCTION TABLE (each driver) INPUTS OUTPUT OE A Y L H H L L L H X Z Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC and Widebus are trademarks of Texas Instruments Incorporated. PRODUCTION DATA information is current as of publication date. Copyright  1996, Texas Instruments Incorporated Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

SN54ACT16244, 74ACT16244 16-BIT BUFFERS/LINE DRIVERS WITH 3-STATE OUTPUTS SCAS116B – MARCH 1990 – REVISED APRIL 1996 logic symbol† 1 1OE EN1 48 2OE EN2 25 3OE EN3 24 4OE EN4 47 2 1A1 1 1 1Y1 46 3 1A2 1Y2 44 5 1A3 1Y3 43 6 1A4 1Y4 41 8 2A1 1 2 2Y1 40 9 2A2 2Y2 38 11 2A3 2Y3 37 12 2A4 2Y4 36 13 3A1 1 3 3Y1 35 14 3A2 3Y2 33 16 3A3 3Y3 32 17 3A4 3Y4 30 19 4A1 1 4 4Y1 29 20 4A2 4Y2 27 22 4A3 4Y3 26 23 4A4 4Y4 †This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54ACT16244, 74ACT16244 16-BIT BUFFERS/LINE DRIVERS WITH 3-STATE OUTPUTS SCAS116B – MARCH 1990 – REVISED APRIL 1996 logic diagram (positive logic) 1 25 1OE 3OE 47 2 36 13 1A1 1Y1 3A1 3Y1 46 3 35 14 1A2 1Y2 3A2 3Y2 44 5 33 16 1A3 1Y3 3A3 3Y3 43 6 32 17 1A4 1Y4 3A4 3Y4 48 24 2OE 4OE 41 8 30 19 2A1 2Y1 4A1 4Y1 40 9 29 20 2A2 2Y2 4A2 4Y2 38 11 27 22 2A3 2Y3 4A3 4Y3 37 12 26 23 2A4 2Y4 4A4 4Y4 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V CC Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through V or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±400 mA CC Maximum power dissipation at T = 55°C (in still air) (see Note 2):DGG package . . . . . . . . . . . . . . . . 0.85 W A DL package . . . . . . . . . . . . . . . . . . . 1.2 W Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C stg †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. (cid:1) 2. The maximum package power dissipation is calculated using a junction temperature of 150 C and a board trace length of 750 mils. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

SN54ACT16244, 74ACT16244 16-BIT BUFFERS/LINE DRIVERS WITH 3-STATE OUTPUTS SCAS116B – MARCH 1990 – REVISED APRIL 1996 recommended operating conditions (see Note 3) SN54ACT16244 74ACT16244 UUNNIITT MIN MAX MIN MAX VCC Supply voltage (see Note 4) 4.5 5.5 4.5 5.5 V VIH High-level input voltage 2 2 V VIL Low-level input voltage 0.8 0.8 V VI Input voltage 0 VCC 0 VCC V VO Output voltage 0 VCC 0 VCC V IOH High-level output current –24 –24 mA IOL Low-level output current 24 24 mA D t/D v Input transition rise or fall rate 0 10 0 10 ns/V TA Operating free-air temperature –55 125 –40 85 °C NOTES: 3. Unused inputs should be tied to VCC through a pullup resistor of approximately 5 k(cid:1) or greater to prevent them from floating. 4. All VCC and GND pins must be connected to the proper voltage supply. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TA = 25°C SN54ACT16244 74ACT16244 PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS VVCCCC UUNNIITT MIN TYP MAX MIN MAX MIN MAX 4.5 V 4.4 4.4 4.4 IIOOHH == –5500 (cid:2)(cid:2)AA 5.5 V 5.4 5.4 5.4 4.5 V 3.94 3.7 3.8 VVOOHH IIOOHH == –2244 mmAA VV 5.5 V 4.94 4.7 4.8 IOH = –50 mA(cid:1) 5.5 V 3.85 IOH = –75 mA(cid:1) 5.5 V 3.85 4.5 V 0.1 0.1 0.1 IIOOLL == 5500 (cid:2)(cid:2)AA 5.5 V 0.1 0.1 0.1 4.5 V 0.36 0.5 0.44 VVOOLL IIOOLL == 2244 mmAA VV 5.5 V 0.36 0.5 0.44 IOL = 50 mA(cid:1) 5.5 V 1.65 IOL = 75 mA(cid:1) 5.5 V 1.65 II VI = VCC or GND 5.5 V ±0.1 ±1 ±1 (cid:2)A IOZ VO = VCC or GND 5.5 V ±0.5 ±10 ±5 (cid:2)A ICC VI = VCC or GND, IO = 0 5.5 V 8 160 80 (cid:2)A D ICC(cid:2) OOnthee irn ipnuptu atst 3a.t4 G VN,D or VCC 5.5 V 0.9 1 1 mA Ci VI = VCC or GND 5 V 4.5 pF Co VO = VCC or GND 5 V 13.5 pF †Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms. ‡This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54ACT16244, 74ACT16244 16-BIT BUFFERS/LINE DRIVERS WITH 3-STATE OUTPUTS SCAS116B – MARCH 1990 – REVISED APRIL 1996 switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1) SN54ACT16244 FFRROOMM TTOO PARAMETER TA = 25°C UNIT ((IINNPPUUTT)) ((OOUUTTPPUUTT)) MMIINN MMAAXX MIN TYP MAX tPLH 4 6.5 8.5 3 10.3 AA YY nnss tPHL 3.4 6.3 8.7 3.4 10.1 tPZH 3 5.8 8.1 3 10.5 OOEE YY nnss tPZL 3.7 6.7 9.3 3.7 11 tPHZ 5.4 8.1 11.5 5.4 13 OOEE YY nnss tPLZ 5 7.5 9.5 5 10.9 switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1) 74ACT16244 FFRROOMM TTOO PARAMETER TA = 25°C UNIT ((IINNPPUUTT)) ((OOUUTTPPUUTT)) MMIINN MMAAXX MIN TYP MAX tPLH 4 6.5 8.5 4 9.4 AA YY nnss tPHL 3.4 6.3 8.7 3.4 9.5 tPZH 3 5.8 8.1 3 8.9 OOEE YY nnss tPZL 3.7 6.7 9.3 3.7 10.3 tPHZ 5.4 8.1 10.3 5.4 11.3 OOEE YY nnss tPLZ 5 7.5 9.5 5 10.3 operating characteristics, VCC = 5 V, TA = 25°C PARAMETER TEST CONDITIONS TYP UNIT Outputs enabled 39 CCpdd PPoowweerr ddiissssiippaattiioonn ccaappaacciittaannccee CCLL == 5500 ppFF, ff == 11 MMHHzz ppFF Outputs disabled 11 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

SN54ACT16244, 74ACT16244 16-BIT BUFFERS/LINE DRIVERS WITH 3-STATE OUTPUTS SCAS116B – MARCH 1990 – REVISED APRIL 1996 PARAMETER MEASUREMENT INFORMATION 2 × VCC TEST S1 500 W S1 Open tPLH/tPHL Open From Output tPLZ/tPZL 2 × VCC Under Test GND tPHZ/tPZH GND CL = 50 pF 500 W (see Note A) LOAD CIRCUIT Output 3 V Control 1.5 V 1.5 V (low-level 0 V enabling) tPZL 3 V tPLZ Input 1.5 V 1.5 V WaveOfourtmpu 1t 50% VCC (cid:1) VCC 0 V S1 at 2 × VCC 20% VCC VOL tPLH tPHL (see Note B) tPHZ tPZH VOH Output VOH Output 50% VCC 50% VCC WSa1v eafto GrmN D2 50% VCC 80% VCC VOL (see Note B) (cid:1) 0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 W , tr =3 ns, tf = 3 ns. D. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) 5962-9202201MXA ACTIVE CFP WD 48 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-9202201MX A SNJ54ACT16244W D 74ACT16244DGG ACTIVE TSSOP DGG 48 40 Green (RoHS NIPDAU Level-1-260C-UNLIM ACT16244 & no Sb/Br) 74ACT16244DGGR ACTIVE TSSOP DGG 48 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 ACT16244 & no Sb/Br) 74ACT16244DGGRG4 ACTIVE TSSOP DGG 48 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 ACT16244 & no Sb/Br) 74ACT16244DL ACTIVE SSOP DL 48 25 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 ACT16244 & no Sb/Br) 74ACT16244DLG4 ACTIVE SSOP DL 48 25 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 ACT16244 & no Sb/Br) 74ACT16244DLR ACTIVE SSOP DL 48 1000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 ACT16244 & no Sb/Br) 74ACT16244DLRG4 ACTIVE SSOP DL 48 1000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 ACT16244 & no Sb/Br) SNJ54ACT16244WD ACTIVE CFP WD 48 1 TBD Call TI N / A for Pkg Type 5962-9202201MX A SNJ54ACT16244W D (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2017 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) 74ACT16244DGGR TSSOP DGG 48 2000 330.0 24.4 8.6 13.0 1.8 12.0 24.0 Q1 74ACT16244DLR SSOP DL 48 1000 330.0 32.4 11.35 16.2 3.1 16.0 32.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2017 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) 74ACT16244DGGR TSSOP DGG 48 2000 367.0 367.0 45.0 74ACT16244DLR SSOP DL 48 1000 367.0 367.0 55.0 PackMaterials-Page2

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MECHANICAL DATA MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,50 0,08 M 0,17 48 25 6,20 8,30 6,00 7,90 0,15 NOM Gage Plane 0,25 1 24 0°–8° A 0,75 0,50 Seating Plane 0,15 1,20 MAX 0,10 0,05 PINS ** 48 56 64 DIM A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 4040078/F 12/97 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold protrusion not to exceed 0,15. D. Falls within JEDEC MO-153 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265

MECHANICAL DATA MCFP010B – JANUARY 1995 – REVISED NOVEMBER 1997 WD (R-GDFP-F**) CERAMIC DUAL FLATPACK 48 LEADS SHOWN 0.120 (3,05) 0.009 (0,23) 0.075 (1,91) 0.004 (0,10) 1.130 (28,70) 0.870 (22,10) 0.370 (9,40) 0.390 (9,91) 0.370 (9,40) 0.250 (6,35) 0.370 (9,40) 0.250 (6,35) 1 48 0.025 (0,635) A 0.014 (0,36) 0.008 (0,20) 24 25 NO. OF 48 56 LEADS** 0.640 0.740 A MAX (16,26) (18,80) 0.610 0.710 A MIN (15,49) (18,03) 4040176/D 10/97 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a ceramic lid using glass frit. D. Index point is provided on cap for terminal identification only E. Falls within MIL STD 1835: GDFP1-F48 and JEDEC MO-146AA GDFP1-F56 and JEDEC MO-146AB • POST OFFICE BOX 655303 DALLAS, TEXAS 75265

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