54AC16374, 74AC16374 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS SCAS123B – MARCH 1990 – REVISED APRIL 1996 (cid:1) Members of the Texas Instruments 54AC16374...WD PACKAGE Widebus Family 74AC16374...DL PACKAGE (cid:1) (TOP VIEW) 3-State True Outputs (cid:1) Full Parallel Access for Loading 1OE 1 48 1CLK (cid:1) Flow-Through Architecture Optimizes 1Q1 2 47 1D1 PCB Layout 1Q2 3 46 1D2 (cid:1) Distributed V and GND Pin Configuration GND 4 45 GND CC Minimizes High-Speed Switching Noise 1Q3 5 44 1D3 (cid:1) EPIC (Enhanced-Performance Implanted 1Q4 6 43 1D4 CMOS) 1-m m Process VCC 7 42 VCC (cid:1) 1Q5 8 41 1D5 500-mA Typical Latch-Up Immunity at 125°C 1Q6GN9D 40 1D6 (cid:1) 1Q7 10 39 GND Package Options Include Plastic 300-mil 1Q8 11 38 1D7 Shrink Small-Outline (DL) Packages Using 2Q1 12 37 1D8 25-mil Center-to-Center Pin Spacings and 2Q2 13 36 2D1 380-mil Fine-Pitch Ceramic Flat (WD) GND 14 35 2D2 Packages Using 25-mil Center-to-Center 2Q3 15 34 GND Pin Spacings 2Q4 16 33 2D3 V 17 32 2D4 description 18 31 V CC CC The ’AC16374 are 16-bit edge-triggered D-type 2Q5 19 30 2D5 flip-flops with 3-state outputs designed 2Q6 20 29 2D6 specifically for driving highly capacitive or GND 21 28 GND relatively low-impedance loads. They are 2Q7 22 27 2D7 particularly suitable for implementing buffer 2Q8 23 26 2D8 registers, I/O ports, bidirectional bus drivers, and 2OE 24 25 2CLK working registers. The ’AC16374 can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock (CLK) input, the Q outputs of the flip-flop take on the logic levels set up at the data (D) inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. OE does not affect the internal operations of the flip-flop. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. The 74AC16374 is packaged in TI’s shrink small-outline package, which provides twice the I/O pin count and functionality of standard small-outline packages in the same printed-circuit-board area. The 54AC16374 is characterized for operation over the full military temperature range of –55°C to 125°C. The 74AC16374 is characterized for operation from –40°C to 85°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC and Widebus are trademarks of Texas Instruments Incorporated. UNLESS OTHERWISE NOTED this document contains PRODUCTION Copyright  1996, Texas Instruments Incorporated DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

54AC16374, 74AC16374 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS SCAS123B – MARCH 1990 – REVISED APRIL 1996 FUNCTION TABLE INPUTS OUTPUT OE CLK D Q L ↑ H H L ↑ L L L X X Q0 L ↓ X Q0 H X X Z logic symbol† 1 1OE 1EN 48 1CLK C1 24 2OE 2EN 25 2CLK C2 47 2 1D1 1D 1 1Q1 46 3 1D2 1Q2 44 5 1D3 1Q3 43 6 1D4 1Q4 41 8 1D5 1Q5 40 9 1D6 1Q6 38 11 1D7 1Q7 37 12 1D8 1Q8 36 13 2D1 2D 2 2Q1 35 14 2D2 2Q2 33 16 2D3 2Q3 32 17 2D4 2Q4 30 19 2D5 2Q5 29 20 2D6 2Q6 27 22 2D7 2Q7 26 23 2D8 2Q8 †This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

54AC16374, 74AC16374 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS SCAS123B – MARCH 1990 – REVISED APRIL 1996 logic diagram (positive logic) 1 24 1OE 2OE 48 25 1CLK 2CLK C1 2 C1 13 47 1Q1 36 2Q1 1D1 1D 2D1 1D To Seven Other Channels To Seven Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V CC Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V + 0.5 V I CC Output voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V + 0.5 V O CC Input clamp current, I (V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA IK I I CC Output clamp current, I (V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA OK O O CC Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA O O CC Continuous current through V or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±400 mA CC Maximum power package dissipation at T = 55°C (in still air)(see Note 2): DL package . . . . . . . . . . . 1.2 W A Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C stg †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

54AC16374, 74AC16374 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS SCAS123B – MARCH 1990 – REVISED APRIL 1996 recommended operating conditions (see Note 3) 54AC16374 74AC16374 UUNNIITT MIN NOM MAX MIN NOM MAX VCC Supply voltage 3 5 5.5 3 5 5.5 V VCC = 3 V 2.1 2.1 VIH High-level input voltage VCC = 4.5 V 3.15 3.15 V VCC = 5.5 V 3.85 3.85 VCC = 3 V 0.9 0.9 VIL Low-level input voltage VCC = 4.5 V 1.35 1.35 V VCC = 5.5 V 1.65 1.65 VI Input voltage 0 VCC 0 VCC V VO Output voltage 0 VCC 0 VCC V VCC = 3 V –4 –4 IOH High-level output current VCC = 4.5 V –24 –24 mA VCC = 5.5 V –24 –24 VCC = 3 V 12 12 IOL Low-level output current VCC = 4.5 V 24 24 mA VCC = 5.5 V 24 24 D t/D v Input transition rise or fall rate 0 10 0 10 ns/V TA Operating free-air temperature –55 125 –40 85 °C NOTE 3: Unused inputs must be held high or low to prevent them from floating. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TA = 25°C 54AC16374 74AC16374 PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS VVCCCC UUNNIITT MIN TYP MAX MIN MAX MIN MAX 3 V 2.9 2.9 2.9 IOH = –50 m A 4.5 V 4.4 4.4 4.4 5.5 V 5.4 5.4 5.4 VOH IOH = –4 mA 3 V 2.58 2.48 2.48 V 4.5 V 3.94 3.8 3.8 IIOL = –2244 mAA 5.5 V 4.94 4.8 4.8 IOH = –75 mA† 5.5 V 3.85 3.85 3 V 0.1 0.1 0.1 IOL = 50 m A 4.5 V 0.1 0.1 0.1 5.5 V 0.1 0.1 0.1 VOL IOL = 12 mA 3 V 0.36 0.44 0.44 V 4.5 V 0.36 0.44 0.44 IIOOLL == 2244 mmAA 5.5 V 0.36 0.44 0.44 IOL = 75 mA† 5.5 V 1.65 1.65 II VI = VCC or GND 5.5 V ±0.1 ±1 ±1 m A IOZ VO = VCC or GND 5.5 V ±0.5 ±5 ±5 m A ICC VI = VCC or GND, IO = 0 5.5 V 8 80 80 m A Ci VI = VCC or GND 5 V 3 pF Co VO = VCC or GND 5 V 11 pF †Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

54AC16374, 74AC16374 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS SCAS123B – MARCH 1990 – REVISED APRIL 1996 timing requirements over recommended operating free-air temperature range ± V = 3.3 V 0.3 V (unless otherwise noted) (see Figure 1) CC TA = 25°C 54AC16374 74AC16374 UUNNIITT MIN MAX MIN MAX MIN MAX fclock Clock frequency 0 60 0 60 0 60 MHz tw Pulse duration CLK high or low 8.3 8.3 8.3 ns tsu Setup time, data before CLK↑ 7.5 7.5 7.5 ns th Hold time, data after CLK↑ 0 0 0 ns timing requirements over recommended operating free-air temperature range ± V = 5 V 0.5 V (unless otherwise noted) (see Figure 1) CC TA = 25°C 54AC16374 74AC16374 UUNNIITT MIN MAX MIN MAX MIN MAX fclock Clock frequency 0 100 0 100 0 100 MHz tw Pulse duration CLK high or low 5 5 5 ns tsu Setup time, data before CLK↑ 5 5 5 ns th Hold time, data after CLK↑ 0 0 0 ns switching characteristics over recommended operating free-air temperature range ± V = 3.3 V 0.3 V (unless otherwise noted) (see Figure 1) CC FROM TO TA = 25°C 54AC16374 74AC16374 PPAARRAAMMEETTEERR UUNNIITT (INPUT) (OUTPUT) MIN TYP MAX MIN MAX MIN MAX fmax 60 60 60 MHz tPLH 4.9 12.2 15 4.9 17 4.9 17 CCLLKK QQ nnss tPHL 4.8 11.9 14.3 4.8 15.7 4.8 15.7 tPZH 4.3 11.9 14.7 4.3 16.8 4.3 16.8 OOEE QQ nnss tPZL 5.3 15.5 18.7 5.3 21.2 5.3 21.2 tPHZ 4 7.3 9 4 9.8 4 9.8 OOEE QQ nnss tPLZ 3.8 7.1 8.8 3.8 9.4 3.8 9.4 switching characteristics over recommended operating free-air temperature range ± V = 5 V 0.5 V (unless otherwise noted) (see Figure 1) CC FROM TO TA = 25°C 54AC16374 74AC16374 PPAARRAAMMEETTEERR UUNNIITT (INPUT) (OUTPUT) MIN TYP MAX MIN MAX MIN MAX fmax 100 100 100 MHz tPLH 3.8 7.6 9.5 3.8 10.8 3.8 10.8 CCLLKK QQ nnss tPHL 3.8 7.6 9.5 3.8 10.6 3.8 10.6 tPZH 3.2 7.2 9 3.2 10.2 3.2 10.2 OOEE QQ nnss tPZL 3.8 8.7 10.7 3.8 12.1 3.8 12.1 tPHZ 3.7 6 7.5 3.7 8.2 3.7 8.2 OOEE QQ nnss tPLZ 3.5 5.8 7.3 3.5 7.9 3.5 7.9 operating characteristics, V = 5 V, T = 25°C CC A PARAMETER TEST CONDITIONS TYP UNIT Outputs enabled 49 CCpdd PPoowweerr ddiissssiippaattiioonn ccaappaacciittaannccee ppeerr fflliipp-fflloopp CCLL == 5500 ppFF, ff == 11 MMHHzz ppFF Outputs disabled 32 PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

54AC16374, 74AC16374 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS SCAS123B – MARCH 1990 – REVISED APRIL 1996 PARAMETER MEASUREMENT INFORMATION 2 × VCC TEST S1 From Output 500 W S1 Open tPLH/tPHL Open Under Test tPLZ/tPZL 2 × VCC GND tPHZ/tPZH GND CL = 50 pF 500 W (see Note A) LOAD CIRCUIT VCC Timing Input 50% tw 0 V th VCC tsu VCC Input 50% 50% Data Input 50% 50% 0 V 0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS Output VCC VCC Control Input 50% 50% 50% 50% (low-level 0 V 0 V enabling) tPZL tPLH tPHL tPLZ VOH Output (cid:1) VCC InO-Puhtapsuet 50% VCC 50% VCVCOL S1W aatv 2e f×o VrmC C1 50% VCC 20% VCC VOL (see Note B) tPHL tPLH tPZH tPHZ Output VOH VOH Out-ofO-Puhtapsuet 50% VCC 50% VCC WSa1v eafto GrmN D2 50% VCC 80% VCC VOL (see Note B) (cid:1) 0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 W , tr =3 ns, tf = 3 ns. D. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM www.ti.com 24-Feb-2006 PACKAGING INFORMATION OrderableDevice Status(1) Package Package Pins Package EcoPlan(2) Lead/BallFinish MSLPeakTemp(3) Type Drawing Qty 74AC16374DL ACTIVE SSOP DL 48 25 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) 74AC16374DLG4 ACTIVE SSOP DL 48 25 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) 74AC16374DLR ACTIVE SSOP DL 48 1000 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) 74AC16374DLRG4 ACTIVE SSOP DL 48 1000 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) (1)Themarketingstatusvaluesaredefinedasfollows: ACTIVE:Productdevicerecommendedfornewdesigns. LIFEBUY:TIhasannouncedthatthedevicewillbediscontinued,andalifetime-buyperiodisineffect. NRND:Notrecommendedfornewdesigns.Deviceisinproductiontosupportexistingcustomers,butTIdoesnotrecommendusingthispartin anewdesign. PREVIEW:Devicehasbeenannouncedbutisnotinproduction.Samplesmayormaynotbeavailable. OBSOLETE:TIhasdiscontinuedtheproductionofthedevice. (2)EcoPlan-Theplannedeco-friendlyclassification:Pb-Free(RoHS),Pb-Free(RoHSExempt),orGreen(RoHS&noSb/Br)-pleasecheck http://www.ti.com/productcontentforthelatestavailabilityinformationandadditionalproductcontentdetails. TBD:ThePb-Free/Greenconversionplanhasnotbeendefined. Pb-Free(RoHS):TI'sterms"Lead-Free"or"Pb-Free"meansemiconductorproductsthatarecompatiblewiththecurrentRoHSrequirements forall6substances,includingtherequirementthatleadnotexceed0.1%byweightinhomogeneousmaterials.Wheredesignedtobesoldered athightemperatures,TIPb-Freeproductsaresuitableforuseinspecifiedlead-freeprocesses. Pb-Free(RoHSExempt):ThiscomponenthasaRoHSexemptionforeither1)lead-basedflip-chipsolderbumpsusedbetweenthedieand package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible)asdefinedabove. Green(RoHS&noSb/Br):TIdefines"Green"tomeanPb-Free(RoHScompatible),andfreeofBromine(Br)andAntimony(Sb)basedflame retardants(BrorSbdonotexceed0.1%byweightinhomogeneousmaterial) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incomingmaterialsandchemicals.TIandTIsuppliersconsidercertaininformationtobeproprietary,andthusCASnumbersandotherlimited informationmaynotbeavailableforrelease. InnoeventshallTI'sliabilityarisingoutofsuchinformationexceedthetotalpurchasepriceoftheTIpart(s)atissueinthisdocumentsoldbyTI toCustomeronanannualbasis. Addendum-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0(mm) B0(mm) K0(mm) P1 W Pin1 Type Drawing Diameter Width (mm) (mm) Quadrant (mm) W1(mm) 74AC16374DLR SSOP DL 48 1000 330.0 32.4 11.35 16.2 3.1 16.0 32.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) 74AC16374DLR SSOP DL 48 1000 346.0 346.0 49.0 PackMaterials-Page2

MECHANICAL DATA MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001 DL (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0.025 (0,635) 0.0135 (0,343) 0.005 (0,13) M 0.008 (0,203) 48 25 0.010 (0,25) 0.005 (0,13) 0.299 (7,59) 0.291 (7,39) 0.420 (10,67) 0.395 (10,03) Gage Plane 0.010 (0,25) 1 24 0°–(cid:1)8° 0.040 (1,02) A 0.020 (0,51) Seating Plane 0.004 (0,10) 0.110 (2,79) MAX 0.008 (0,20) MIN PINS ** 28 48 56 DIM 0.380 0.630 0.730 A MAX (9,65) (16,00) (18,54) 0.370 0.620 0.720 A MIN (9,40) (15,75) (18,29) 4040048/E 12/01 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). D. Falls within JEDEC MO-118 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265

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