74AC11004 HEX INVERTER SCAS033B − JANUARY 1988 − REVISED APRIL 1996 (cid:2) Flow-Through Architecture Optimizes DB, DW, OR N PACKAGE PCB Layout (TOP VIEW) (cid:2) Center-Pin V and GND Configuration CC 1Y 1 20 1A Minimizes High-Speed Switching Noise (cid:2) EPIC™ (Enhanced-Performance Implanted 2Y 2 19 2A 3Y 3 18 3A CMOS) 1-μm Process GND 4 17 NC (cid:2) 500-mA Typical Latch-Up Immunity at GND 5 16 VCC 125°C GND 6 15 VCC (cid:2) Package Options Include Plastic GND 7 14 NC Small-Outline (DW) and Shrink 4Y 8 13 4A Small-Outline (DB) Packages, and Standard 5Y 9 12 5A Plastic 300-mil DIPs (N) 6Y 10 11 6A NC − No internal connection description This device contains six independent inverters. It performs the Boolean function Y = A. The 74AC11004 is characterized for operation from −40°C to 85°C. FUNCTION TABLE (each inverter) INPUT OUTPUT A Y H L L H logic symbol† 20 1 1A 1 1Y 19 2 2A 2Y 18 3 3A 3Y 13 8 4A 4Y 12 9 5A 5Y 11 10 6A 6Y †This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments Incorporated. PRODUCTION DATA information is current as of publication date. Copyright © 1996, Texas Instruments Incorporated Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

74AC11004 HEX INVERTER SCAS033B − JANUARY 1988 − REVISED APRIL 1996 logic diagram (positive logic) 20 1 1A 1Y 19 2 2A 2Y 18 3 3A 3Y 13 8 4A 4Y 12 9 5A 5Y 11 10 6A 6Y absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V CC Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V + 0.5 V I CC Output voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V + 0.5 V O CC Input clamp current, I (V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA IK I I CC Output clamp current, I (V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA OK O O CC Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA O O CC Continuous current through V or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA CC Maximum power dissipation at T = 55°C (in still air) (see Note 2):DW package . . . . . . . . . . . . . . . . . . 1.6 W A DB package . . . . . . . . . . . . . . . . . . . 0.6 W N package . . . . . . . . . . . . . . . . . . . . 1.3 W Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C stg †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The maximum package power dissipation is calculated using a junction temperature of 150(cid:3)C and a board trace length of 750 mils, except for the N package, which has a trace length of zero. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

74AC11004 HEX INVERTER SCAS033B − JANUARY 1988 − REVISED APRIL 1996 recommended operating conditions MIN NOM MAX UNIT VCC Supply voltage 3 5 5.5 V VCC = 3 V 2.1 VVIIHH HHiigghh-lleevveell iinnppuutt vvoollttaaggee VCC = 4.5 V 3.15 VV VCC = 5.5 V 3.85 VCC = 3 V 0.9 VVIILL LLooww-lleevveell iinnppuutt vvoollttaaggee VCC = 4.5 V 1.35 VV VCC = 5.5 V 1.65 VI Input voltage 0 VCC V VO Output voltage 0 VCC V VCC = 3 V −4 IIOOHH HHiigghh-lleevveell oouuttppuutt ccuurrrreenntt VCC = 4.5 V −24 mmAA VCC = 5.5 V −24 VCC = 3 V 12 IIOOLL LLooww-lleevveell oouuttppuutt ccuurrrreenntt VCC = 4.5 V 24 mmAA VCC = 5.5 V 24 Δt/Δv Input transition rise or fall rate 0 10 ns/V TA Operating free-air temperature −40 85 °C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TA = 25°C PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS VVCC MIN TYP MAX MMIINN MMAAXX UUNNIITT 3 V 2.9 2.9 IIOOHH = −5500 μμAA 4.5 V 4.4 4.4 5.5 V 5.4 5.4 VVOOHH IOH = −4 mA 3 V 2.58 2.48 VV 4.5 V 3.94 3.8 IIOH = −2244 mAA 5.5 V 4.94 4.8 IOH = −75 mA† 5.5 V 3.85 3 V 0.1 0.1 IIOOLL = 5500 μμAA 4.5 V 0.1 0.1 5.5 V 0.1 0.1 VVOOLL IOL = 12 mA 3 V 0.36 0.44 VV 4.5 V 0.36 0.44 IIOL = 2244 mmAA 5.5 V 0.36 0.44 IOL = 75 mA† 5.5 V 1.65 II VI = VCC or GND 5.5 V ±0.1 ±1 μA ICC VI = VCC or GND, IO = 0 5.5 V 4 40 μA Ci VI = VCC or GND 5 V 3.5 pF †Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

74AC11004 HEX INVERTER SCAS033B − JANUARY 1988 − REVISED APRIL 1996 switching characteristics over recommended operating free-air temperature range, ± V = 3.3 V 0.3 V (unless otherwise noted) (see Figure 1) CC FFRROOMM TTOO TA = 25°C PPAARRAAMMEETTEERR MMIINN MMAAXX UUNNIITT (INPUT) (OUTPUT) MIN TYP MAX tPLH 1.5 6.1 9 1.5 10 AA YY nnss tPHL 1.5 5.2 7.4 1.5 8.2 switching characteristics over recommended operating free-air temperature range, V = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) CC FFRROOMM TTOO TA = 25°C PPAARRAAMMEETTEERR MMIINN MMAAXX UUNNIITT (INPUT) (OUTPUT) MIN TYP MAX tPLH 1.5 4.2 6.3 1.5 7.1 AA YY nnss tPHL 1.5 3.8 5.5 1.5 6 operating characteristics, V = 5 V, T = 25°C CC A PARAMETER TEST CONDITIONS TYP UNIT Cpd Power dissipation capacitance per inverter CL = 50 pF, f = 1 MHz 29 pF PARAMETER MEASUREMENT INFORMATION Input VCC From Output (see Note B) 50% 50% Under Test 0 V CL = 50 pF 500 Ω tPHL tPLH (see Note A) VOH Output 50% VCC 50% VCC VOL LOAD CIRCUIT VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. Input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns. C. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) 74AC11004DW ACTIVE SOIC DW 20 25 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 AC11004 & no Sb/Br) 74AC11004DWE4 ACTIVE SOIC DW 20 25 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 AC11004 & no Sb/Br) 74AC11004DWR ACTIVE SOIC DW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 AC11004 & no Sb/Br) 74AC11004N ACTIVE PDIP N 20 20 Pb-Free NIPDAU N / A for Pkg Type -40 to 85 74AC11004N (RoHS) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) 74AC11004DWR SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) 74AC11004DWR SOIC DW 20 2000 367.0 367.0 45.0 PackMaterials-Page2

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PACKAGE OUTLINE DW0020A SOIC - 2.65 mm max height SCALE 1.200 SOIC C 10.63 SEATING PLANE TYP 9.97 A PIN 1 ID 0.1 C AREA 18X 1.27 20 1 13.0 2X 12.6 11.43 NOTE 3 10 11 0.51 20X 7.6 0.31 2.65 MAX B 7.4 0.25 C A B NOTE 4 0.33 TYP 0.10 0.25 SEE DETAIL A GAGE PLANE 0.3 1.27 0 - 8 0.1 0.40 DETAIL A TYPICAL 4220724/A 05/2016 NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side. 5. Reference JEDEC registration MS-013. www.ti.com

EXAMPLE BOARD LAYOUT DW0020A SOIC - 2.65 mm max height SOIC 20X (2) SYMM 1 20 20X (0.6) 18X (1.27) SYMM (R0.05) TYP 10 11 (9.3) LAND PATTERN EXAMPLE SCALE:6X SOOPLEDNEINRG MASK METAL MSOELTDAEL RU NMDAESRK SOOPLEDNEINRG MASK 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4220724/A 05/2016 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DW0020A SOIC - 2.65 mm max height SOIC 20X (2) SYMM 1 20 20X (0.6) 18X (1.27) SYMM 10 11 (9.3) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:6X 4220724/A 05/2016 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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