Si500D DIFFERENTIAL OUTPUT SILICON OSCILLATOR Features  Quartz-free, MEMS-free, and PLL-free all-silicon  Footprint compatible with industry- oscillator standard 3.2x5.0mm XOs  Any output frequencies from 0.9 to 200MHz  CMOS, SSTL, LVPECL, LVDS, and HCSL  Short lead times versions available  Excellent temperature stability (±20ppm)  Driver stopped, tri-state, or powerdown  Highly reliable startup and operation operation  High immunity to shock and vibration  RoHS compliant  Low jitter: <1.5ps rms  1.8, 2.5, or 3.3V options  0 to 85°C operation includes 10-year aging in hot  Low power environments  More than 10x better fit rate than competing crystal solutions Specifications Parameters Condition Min Typ Max Units Frequency Range 0.9 — 200 MHz Temperature stability, — ±10 — ppm 0 to +70°C Temperature stability, — ±20 — ppm 0 to +85°C Frequency Stability Total stability, — — ±150 ppm 0 to +70°C operation1 Total stability, — — ±250 ppm 0 to +85°C operation2 Commercial 0 — 70 °C Operating Temperature Extended commercial 0 — 85 °C Storage Temperature –55 — +125 °C 1.8V option 1.71 — 1.98 V Supply Voltage 2.5V option 2.25 — 2.75 V 3.3V option 2.97 — 3.63 V Notes: 1. Inclusive of 25°C initial frequency accuracy, operating temperature range, supply voltage change, output load change, first-year aging at 25°C, shock, vibration, and one solder reflow. 2. Inclusive of 25°C initial frequency accuracy, operating temperature range, supply voltage change, output load change, ten-year aging at 85°C, shock, vibration, and one solder reflow. 3. See “AN409: Output Termination Options for the Si500S and Si500D Silicon Oscillators” for further details regarding output clock termination recommendations. 4. V = .5 x V . TT DD 5. V = .45 x V . TT DD Rev. 1.1 10/11 Copyright © 2011 by Silicon Laboratories Si500D

Si500D Parameters Condition Min Typ Max Units LVPECL — 34.0 36.0 mA Low Power LVPECL — 19.3 22.2 mA LVDS — 14.9 16.5 mA HCSL — 25.3 29.3 mA Differential CMOS(3.3V option, — 33 36 mA 10pF on each output, 200MHz) Supply Current Differential CMOS(3.3V option, — 16 — mA 1pFon each output, 40MHz) Differential SSTL-3.3 — 24.5 27.7 mA Differential SSTL-2.5 — 24.3 26.7 mA Differential SSTL-1.8 — 22.2 25 mA Tri-State — 9.7 10.7 mA Powerdown — 1.0 1.9 mA Output Symmetry V =0 46 – 13ns/T — 54 + 13ns/T % DIFF CLK CLK LVPECL/LVDS — — 460 ps Rise and Fall Times (20/80%)3 HCSL/Differential SSTL — — 800 ps Differential CMOS, 15pF, >80MHz — 1.1 1.6 ns LVPECL Output Option Mid-level VDD – 1.5 — VDD – 1.34 V (DC coupling, 50 to VDD – 2.0V)3 Diff swing .720 — .880 VPK Low Power LVPECL Output Option Mid-level — N/A — V (AC coupling, 100 Differential Load)3 Diff swing .68 — .95 VPK LVDS Output Option (2.5/3.3V) Mid-level 1.15 — 1.26 V (RTERM=100 diff)3 Diff swing 0.25 — 0.45 VPK LVDS Output Option (1.8V) Mid-level 0.85 — 0.96 V (RTERM=100 diff)3 Diff swing 0.25 — 0.45 VPK Mid-level 0.35 — 0.425 V HCSL Output Option3 Diff swing 0.65 — 0.82 V PK DC termination per pad 45 — 55  V , sourcing 9mA V –0.6 — — V CMOS Output Voltage3 OH DD V , sinking 9mA — — 0.6 V OL V V + 0.375 — — SSTL-1.8 Output Voltage4 OH TT V V — — V – 0.375 OL TT V V + 0.48 — — SSTL-2.5 Output Voltage4 OH TT V V — — V – 0.48 OL TT V V + 0.48 — — SSTL-3.3 Output Voltage5 OH TT V V — — V – 0.48 OL TT From time V crosses min spec Powerup Time DD — — 2 ms supply OE Deassertion to Clk Stop — — 250 + 3xT ns CLK Return from Output Driver Stopped — — 250 + 3xT ns Mode CLK Return From Tri-State Time — — 12 + 3xT µs CLK Notes: 1. Inclusive of 25°C initial frequency accuracy, operating temperature range, supply voltage change, output load change, first-year aging at 25°C, shock, vibration, and one solder reflow. 2. Inclusive of 25°C initial frequency accuracy, operating temperature range, supply voltage change, output load change, ten-year aging at 85°C, shock, vibration, and one solder reflow. 3. See “AN409: Output Termination Options for the Si500S and Si500D Silicon Oscillators” for further details regarding output clock termination recommendations. 4. V = .5 x V . TT DD 5. V = .45 x V . TT DD 2 Rev. 1.1

Si500D Parameters Condition Min Typ Max Units Return From Powerdown Time — — 2 ms ps Non-CMOS — 1 2 RMS Period Jitter (1-sigma) ps CMOS, C =7pF — 1 3 L RMS 1.0MHz – min(20MHz, ps — 0.6 1 0.4xF ),non-CMOS RMS Integrated Phase Jitter OUT 1.0MHz – min(20MHz, ps — 0.7 1.5 0.4xF ),CMOS format RMS OUT Notes: 1. Inclusive of 25°C initial frequency accuracy, operating temperature range, supply voltage change, output load change, first-year aging at 25°C, shock, vibration, and one solder reflow. 2. Inclusive of 25°C initial frequency accuracy, operating temperature range, supply voltage change, output load change, ten-year aging at 85°C, shock, vibration, and one solder reflow. 3. See “AN409: Output Termination Options for the Si500S and Si500D Silicon Oscillators” for further details regarding output clock termination recommendations. 4. V = .5 x V . TT DD 5. V = .45 x V . TT DD Rev. 1.1 3

Si500D Package Specifications Table 1. Package Diagram Dimensions (mm) Dimension Min Nom Max Dimension Min Nom Max A 0.80 0.85 0.90 L1 0.00 0.05 0.10 A1 0.00 0.03 0.05 aaa — — 0.10 b 0.59 0.64 0.69 bbb — — 0.10 D 3.20 BSC. ccc — — 0.08 e 1.27 BSC. ddd — — 0.10 E 4.00 BSC. eee — — 0.05 L 0.95 1.00 1.05 Table 2. Pad Connections Table 3. Tri-State/Powerdown/Driver Stopped Function on OE (3rd Option Code) 1 OE NC—Make no external A B C D E F 2 connection to this pin Open Active Active Active Active Active Active 3 GND 1 Tri- Power- Driver Active Active Active Level State down Stopped 4 Output 5 Complementary Output 0 Tri- Active Power- Active Driver Active Level State down Stopped 6 VDD 0 C CC CC T T T T T T Dimension (mm) C1 2.70 E 1.27 Y YWW X1 0.75 Y1 1.55 0 = Si500 CCCCC = mark code TTTTTT = assembly manufacturing code YY = year WW = work week Figure 1. Recommended Land Pattern Figure 2. Top Mark 4 Rev. 1.1

Si500D Environmental Compliance Parameter Conditions/Test Method Mechanical Shock MIL-STD-883, Method 2002.4 Mechanical Vibration MIL-STD-883, Method 2007.3 A Resistance to Soldering Heat MIL-STD-202, 260C° for 8 seconds Solderability MIL-STD-883, Method 2003.8 Damp Heat IEC 68-2-3 Moisture Sensitivity Level J-STD-020, MSL 3 Ordering Information The Si500D supports a variety of options including frequency, output format, supply voltage, and tri- state/powerdown. Specific device configurations are programmed into the Si500D at time of shipment. Configurations are specified using the figure below. Silicon Labs provides a web-based part number utility that can be used to simplify part number configuration. Refer to www.silabs.com/SiliconXOPartnumber to access this tool. The Si500D XO series is supplied in a ROHS-compliant, Pb-free, 6-pad, 3.2 x 4.0mm package. Tape and reel packaging is available as an ordering option. 500D X X X XXMXXXX A C X R Si500 Frequency R = Tape & Reel Differential xMxxxxx: f < 10 MHz Blank = Cut-Tape Oscillator OUT xxMxxxx: 10 MHz < f < 100 MHz OUT xxxMxxx: f > 100 MHz OUT 1st Option Code V Format DD 3rd Option Code Oper. Temp Range A 3.3 LVPECL Tri-State/Powerdown/ F 0 to 70 °C B 3.3 Low Power LVPECL Output Driver Stopped *H 0 to 85 °C C 3.3 LVDS A OE active high/tristate D 3.3 HCSL B OE active low/tristate E 3.3 Dual Output CMOS C OE active high/powerdown F 3.3 Differential CMOS D OE active low/powerdown Product Revision = C G 3.3 Dual Output SSTL E OE active high/driver stopped H 3.3 Differential SSTL F OE active low/driver stopped J 2.5 LVPECL K 2.5 Low Power LVPECL 2nd Option Code Package L 2.5 LVDS M 2.5 HCSL Stability (ppm, max) A 3.2 x 4.0 mm SMD N 2.5 Dual Output CMOS A ±150 P 2.5 Differential CMOS B ±250 Q 2.5 Dual Output SSTL R 2.5 Differential SSTL S 1.8 LVDS T 1.8 HCSL U 1.8 Dual Output CMOS V 1.8 Differential CMOS *Note: Only +250 ppm is supported. W 1.8 Dual Output SSTL X 1.8 Differential SSTL Rev. 1.1 5

Si500D DOCUMENT CHANGE LIST Revision 0.2 to Revision 0.3  Revision B to Revision C updated in Ordering Information  0 to 85C° Operating Temperature Range option added Revision 0.3 to Revision 1.0  Clarified SSTL specifications.  Revised Differential CMOS supply current values.  Clarified Differential CMOS supply current loading conditions. Revision 1.0 to Revision 1.1  Updated Ordering information for ±250ppm from 0 to +85°C.  Updated jitter from 1.5ps to 1.5ps rms.  Updated operating temperature to include extended commercial at 0 to +85°C.  Updated features to include LVPECL, LVDS, and HCSL. 6 Rev. 1.1

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