25AA320/25LC320/25C320 32K SPI™ Bus Serial EEPROM Device Selection Table Description: The Microchip Technology Inc. 25AA320/25LC320/ Part VCC Max. Clock Temp. 25C320 (25XX320*) are 32 Kbit serial Electrically Number Range Frequency Ranges Erasable PROMs. The memory is accessed via a 25AA320 1.8-5.5V 1MHz I simple Serial Peripheral Interface (SPI™) compatible 25LC320 2.5-5.5V 2MHz I,E serial bus. The bus signals required are a clock input (SCK) plus separate data in (SI) and data out (SO) 25C320 4.5-5.5V 3MHz I,E lines. Access to the device is controlled through a Chip Select (CS) input. Features: Communication to the device can be paused via the • Low-power CMOS technology: hold pin (HOLD). While the device is paused, - Write current: 3mA maximum transitions on its inputs will be ignored, with the - Read current: 500µA typical exception of Chip Select, allowing the host to service higher priority interrupts. - Standby current: 500nA typical (cid:127) 4096 x 8 bit organization Block Diagram (cid:127) 32 byte page (cid:127) Write cycle time: 5ms maximum Status HV Generator Register (cid:127) Self-timed erase and write cycles (cid:127) Block write protection: - Protect none, 1/4, 1/2 or all of array (cid:127) Built-in write protection: - Power on/off data protection circuitry Memory EEPROM I/O Control Array - Write enable latch Logic Control XDEC Logic - Write-protect pin (cid:127) Sequential read Page Latches (cid:127) High reliability: - Endurance: 1M E/W cycles SI - Data retention: > 200 years SO Y Decoder - ESD protection: > 4000V CS (cid:127) 8-pin PDIP, SOIC and TSSOP packages SCK (cid:127) 14-lead TSSOP package Sense Amp. HOLD (cid:127) Temperature ranges supported: R/W Control WP - Industrial (I): -40°C to +85°C VCC - Automotive (E): -40°C to +125°C VSS Package Types PDIP, SOIC TSSOP TSSOP CS 1 8 VCC HOLD 1 8 SCK SCOS 12 1143 VHCOCLD SO 2 25XX 7 HOLD VCC 2 25XX 7 SI NNCC 34 25XX 1112 NNCC WP 3 32 6 SCK CS 3 32 6 VSS NC 5 32 10 NC VSS 4 0 5 SI SO 4 0 5 WP WP 6 0 9 SCK VSS 7 8 SI *25XX320 is used in this document as a generic part number for the 25AA320/25LC320/25C320 devices.  2004 Microchip Technology Inc. DS21227E-page 1

25AA320/25LC320/25C320 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings(†) VCC.............................................................................................................................................................................7.0V All inputs and outputs w.r.t. VSS........................................................................................................-0.6V to VCC + 1.0V Storage temperature.................................................................................................................................-65°C to 150°C Ambient temperature under bias...............................................................................................................-40°C to 125°C ESD protection on all pins..........................................................................................................................................4 kV † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an extended period of time may affect device reliability. TABLE 1-1: DC CHARACTERISTICS Industrial (I): TA = -40°C to +85°C VCC = 1.8V to 5.5V DC CHARACTERISTICS Automotive (E):TA = -40°C to +125°C VCC = 2.5V to 5.5V Param. Sym. Characteristics Min. Max. Units Conditions No. D1 VIH1 High-level input 2.0 VCC+1 V VCC ≥ 2.7V (Note) D2 VIH2 voltage 0.7 VCC VCC+1 V VCC< 2.7V (Note) D3 VIL1 Low-level input -0.3 0.8 V VCC ≥ 2.7V (Note) D4 VIL2 voltage -0.3 0.3 VCC V VCC < 2.7V (Note) D5 VOL Low-level output — 0.2 V IOL = 1.0mA, VCC < 2.5V voltage D6 VOH High-level output VCC -0.5 — V IOH = -400µA voltage D7 ILI Input leakage current — ±1 µA CS = VCC, VIN = VSS TO VCC D8 ILO Output leakage — ±1 µA CS = VCC, VOUT = VSS TO VCC current D9 CINT Internal Capacitance — 7 pF TA = 25°C, CLK = 1.0MHz, (all inputs and VCC = 5.0V (Note) outputs) D10 ICC Read Operating Current — 1 mA VCC = 5.5V; FCLK = 3.0MHz; — 500 µA SO = Open VCC = 2.5V; FCLK = 2.0MHz; SO = Open D11 ICC Write — 5 mA VCC = 5.5V — 3 mA VCC = 2.5V D12 ICCS Standby Current — 5 µA CS = VCC = 5.5V, Inputs tied to VCC or — 1 µA VSS CS = VCC = 2.5V, Inputs tied to VCC or VSS Note: This parameter is periodically sampled and not 100% tested. DS21227E-page 2  2004 Microchip Technology Inc.

25AA320/25LC320/25C320 TABLE 1-2: AC CHARACTERISTICS Industrial (I): TA = -40°C to +85°C VCC = 1.8V to 5.5V AC CHARACTERISTICS Automotive (E): TA = -40°C to +125°C VCC = 2.5V to 5.5V Param. Sym. Characteristic Min. Max. Units Conditions No. 1 FCLK Clock Frequency — 3 MHz VCC = 4.5V to 5.5V — 2 MHz VCC = 2.5V to 5.5V — 1 MHz VCC = 1.8V to 5.5V 2 TCSS CS Setup Time 100 — ns VCC = 4.5V to 5.5V 250 — ns VCC = 2.5V to 5.5V 500 — ns VCC = 1.8V to 5.5V 3 TCSH CS Hold Time 150 — ns VCC = 4.5V to 5.5V 250 — ns VCC = 2.5V to 5.5V 475 — ns VCC = 1.8V to 5.5V 4 TCSD CS Disable Time 500 — ns — 5 TSU Data Setup Time 30 — ns VCC = 4.5V to 5.5V 50 — ns VCC = 2.5V to 5.5V 50 — ns VCC = 1.8V to 5.5V 6 THD Data Hold Time 50 — ns VCC = 4.5V to 5.5V 100 — ns VCC = 2.5V to 5.5V 100 — ns VCC = 1.8V to 5.5V 7 TR CLK Rise Time — 2 µs (Note1) 8 TF CLK Fall Time — 2 µs (Note1) 9 THI Clock High Time 150 — ns VCC = 4.5V to 5.5V 230 — ns VCC = 2.5V to 5.5V 475 — ns VCC = 1.8V to 5.5V 10 TLO Clock Low Time 150 — ns VCC = 4.5V to 5.5V 230 — ns VCC = 2.5V to 5.5V 475 — ns VCC = 1.8V to 5.5V 11 TCLD Clock Delay Time 50 — ns — 12 TCLE Clock Enable Time 50 — ns — 13 TV Output Valid from — 150 ns VCC = 4.5V to 5.5V Clock Low — 230 ns VCC = 2.5V to 5.5V — — ns VCC = 1.8V to 5.5V 14 THO Output Hold Time 0 — ns (Note1) 15 TDIS Output Disable Time — 200 ns VCC = 4.5V to 5.5V (Note1) — 250 ns VCC = 2.5V to 5.5V (Note1) — — ns VCC = 1.8V to 5.5V 16 THS HOLD Setup Time 100 — ns VCC = 4.5V to 5.5V 100 — ns VCC = 2.5V to 5.5V 200 — ns VCC = 1.8V to 5.5V 17 THH HOLD Hold Time 100 — ns VCC = 4.5V to 5.5V 100 — ns VCC = 2.5V to 5.5V 200 — ns VCC = 1.8V to 5.5V 18 THZ HOLD Low to Output 100 — ns VCC = 4.5V to 5.5V (Note1) High-Z 150 — ns VCC = 2.5V to 5.5V (Note1) 200 — ns VCC = 1.8V to 5.5V 19 THV HOLD High to Output 100 — ns VCC = 4.5V to 5.5V Valid 150 — ns VCC = 2.5V to 5.5V 200 — ns VCC = 1.8V to 5.5V 20 TWC Internal Write Cycle — 5 ms — Time 21 — Endurance 1M — E/W (Note2) Cycles Note 1: This parameter is periodically sampled and not 100% tested. 2: This parameter is not tested but established by characterization. For endurance estimates in a specific application, please consult the Total Endurance™ Model which can be obtained from Microchip’s web site at: www.microchip.com.  2004 Microchip Technology Inc. DS21227E-page 3

25AA320/25LC320/25C320 FIGURE 1-1: HOLD TIMING CS 16 17 16 17 SCK 18 19 High-impedance SO n+2 n+1 n n n-1 5 don’t care SI n+2 n+1 n n n-1 HOLD FIGURE 1-2: SERIAL INPUT TIMING 4 CS 12 2 11 7 Mode 1,1 8 3 SCK Mode 0,0 5 6 SI MSB in LSB in High-impedance SO FIGURE 1-3: SERIAL OUTPUT TIMING CS 9 10 3 Mode 1,1 SCK Mode 0,0 13 15 14 SO MSB out ISB out don’t care SI DS21227E-page 4  2004 Microchip Technology Inc.

25AA320/25LC320/25C320 TABLE 1-3: AC TEST CONDITIONS FIGURE 1-4: AC TEST CIRCUIT AC Waveform: VCC VLO = 0.2V — VHI = VCC - 0.2V (Note1) VHI = 4.0V (Note2) 2.25 KΩ Timing Measurement Reference Level SO Input 0.5 VCC Output 0.5 VCC 1.8 KΩ 100 pF Note1: For VCC ≤ 4.0V 2: For VCC > 4.0V  2004 Microchip Technology Inc. DS21227E-page 5

25AA320/25LC320/25C320 2.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table2-1. TABLE 2-1: PIN FUNCTION TABLE 8-pin 14-lead Name PDIP SOIC Description TSSOP TSSOP CS 1 1 3 1 Chip Select Input SO 2 2 4 2 Serial Data Output NC — — — 3,4,5 Not Connected WP 3 3 5 6 Write-Protect Pin Vss 4 4 6 7 Ground SI 5 5 7 8 Serial Data Input SCK 6 6 8 9 Serial Clock Input NC — — — 10,11,12 Not Connected HOLD 7 7 1 13 Hold Input Vcc 8 8 2 14 Supply Voltage 2.1 Chip Select (CS) The WP pin function is blocked when the WPEN bit in the Status register is low. This allows the user to install A low level on this pin selects the device. A high level the 25XX320 in a system with WP pin grounded and deselects the device and forces it into Standby mode. still be able to write to the Status register. The WP pin However, a programming cycle which is already functions will be enabled when the WPEN bit is set initiated or in progress will be completed, regardless of high. the CS input signal. If CS is brought high during a program cycle, the device will go into Standby mode as 2.4 Serial Input (SI) soon as the programming cycle is complete. When the The SI pin is used to transfer data into the device. It device is deselected, SO goes to the high-impedance receives instructions, addresses, and data. Data is state, allowing multiple parts to share the same SPI latched on the rising edge of the serial clock. bus. A low-to-high transition on CS after a valid write sequence initiates an internal write cycle. After power- 2.5 Serial Clock (SCK) up, a low level on CS is required prior to any sequence being initiated. The SCK is used to synchronize the communication between a master and the 25XX320. Instructions, 2.2 Serial Output (SO) addresses, or data present on the SI pin are latched on the rising edge of the clock input, while data on the SO The SO pin is used to transfer data out of the 25XX320. pin is updated after the falling edge of the clock input. During a read cycle, data is shifted out on this pin after the falling edge of the serial clock. 2.6 Hold (HOLD) 2.3 Write-Protect (WP) The HOLD pin is used to suspend transmission to the 25XX320 while in the middle of a serial sequence with- This pin is used in conjunction with the WPEN bit in the out having to re-transmit the entire sequence again. It Status register to prohibit writes to the nonvolatile bits must be held high any time this function is not being in the Status register. When WP is low and WPEN is used. Once the device is selected and a serial high, writing to the nonvolatile bits in the Status register sequence is underway, the HOLD pin may be pulled is disabled. All other operations function normally. low to pause further serial communication without When WP is high, all functions, including writes to the resetting the serial sequence. The HOLD pin must be nonvolatile bits in the Status register operate normally. brought low while SCK is low, otherwise the HOLD If the WPEN bit is set, WP low during a Status register function will not be invoked until the next SCK high-to- write sequence will disable writing to the Status low transition. The 25XX320 must remain selected dur- register. If an internal write cycle has already begun, ing this sequence. The SI, SCK, and SO pins are in a WP going low will have no effect on the write. high-impedance state during the time the device is paused and transitions on these pins will be ignored. To resume serial communication, HOLD must be brought high while the SCK pin is low, otherwise serial communication will not resume. Lowering the HOLD line at any time will tri-state the SO line. DS21227E-page 6  2004 Microchip Technology Inc.

25AA320/25LC320/25C320 3.0 FUNCTIONAL DESCRIPTION 3.3 Write Sequence Prior to any attempt to write data to the 25XX320, the 3.1 Principles Of Operation write enable latch must be set by issuing the WREN The 25XX320 are 4096 byte Serial EEPROMs instruction (Figure3-4). This is done by setting CS low designed to interface directly with the Serial Peripheral and then clocking out the proper instruction into the Interface (SPI) port of many of today’s popular 25XX320. After all eight bits of the instruction are microcontroller families, including Microchip’s transmitted, the CS must be brought high to set the PIC16C6X/7X microcontrollers. It may also interface write enable latch. If the write operation is initiated with microcontrollers that do not have a built-in SPI port immediately after the WREN instruction without CS by using discrete I/O lines programmed properly with being brought high, the data will not be written to the the software. array because the write enable latch will not have been properly set. The 25XX320 contains an 8-bit instruction register. The device is accessed via the SI pin, with data being Once the write enable latch is set, the user may clocked in on the rising edge of SCK. The CS pin must proceed by setting the CS low, issuing a WRITE be low and the HOLD pin must be high for the entire instruction, followed by the 16-bit address, with the four operation. MSBs of the address being don’t care bits, and then the data to be written. Up to 32 bytes of data can be sent to Table3-1 contains a list of the possible instruction the 25XX320 before a write cycle is necessary. The bytes and format for device operation. All instructions, only restriction is that all of the bytes must reside in the addresses and data are transferred MSB first, LSB last. same page. A page address begins with xxxx xxxx Data is sampled on the first rising edge of SCK after CS xxx0 0000 and ends with xxxx xxxx xxx1 1111. goes low. If the clock line is shared with other If the internal address counter reaches xxxx xxxx peripheral devices on the SPI bus, the user can assert xxx1 1111 and the clock continues, the counter will the HOLD input and place the 25XX320 in ‘HOLD’ roll back to the first address of the page and overwrite mode. After releasing the HOLD pin, operation will any data in the page that may have been written. resume from the point when the HOLD was asserted. For the data to be actually written to the array, the CS 3.2 Read Sequence must be brought high after the least significant bit (D0) of the nth data byte has been clocked in. If CS is The device is selected by pulling CS low. The 8-bit brought high at any other time, the write operation will READ instruction is transmitted to the 25XX320 fol- not be completed. Refer to Figure3-2 and Figure3-3 lowed by the 16-bit address, with the four MSBs of the for more detailed illustrations on the byte write address being don’t care bits. After the correct READ sequence and the page write sequence respectively. instruction and address are sent, the data stored in the While the write is in progress, the Status register may memory at the selected address is shifted out on the be read to check the status of the WPEN, WIP, WEL, SO pin. The data stored in the memory at the next BP1 and BP0 bits (Figure3-6). A read attempt of a address can be read sequentially by continuing to pro- memory array location will not be possible during a vide clock pulses. The internal address pointer is auto- write cycle. When the write cycle is completed, the matically incremented to the next higher address after write enable latch is reset. each byte of data is shifted out. When the highest address is reached (0FFFh), the address counter rolls over to address 0000h allowing the read cycle to be continued indefinitely. The read operation is terminated by raising the CS pin (Figure3-1). TABLE 3-1: INSTRUCTION SET Instruction Name Instruction Format Description READ 0000 0011 Read data from memory array beginning at selected address WRITE 0000 0010 Write data to memory array beginning at selected address WRDI 0000 0100 Reset the write enable latch (disable write operations) WREN 0000 0110 Set the write enable latch (enable write operations) RDSR 0000 0101 Read Status register WRSR 0000 0001 Write Status register  2004 Microchip Technology Inc. DS21227E-page 7

25AA320/25LC320/25C320 FIGURE 3-1: READ SEQUENCE CS 0 1 2 3 4 5 6 7 8 9 10 11 21 22 23 24 25 26 27 28 29 30 31 SCK instruction 16-bit address SI 0 0 0 0 0 0 1 1 15 14 13 12 2 1 0 data out High-impedance SO 7 6 5 4 3 2 1 0 FIGURE 3-2: BYTE WRITE SEQUENCE CS Twc 0 1 2 3 4 5 6 7 8 9 10 11 21 22 23 24 25 26 27 28 29 30 31 SCK instruction 16-bit address data byte SI 0 0 0 0 0 0 1 0 15 14 13 12 2 1 0 7 6 5 4 3 2 1 0 High-impedance SO FIGURE 3-3: PAGE WRITE SEQUENCE CS 0 1 2 3 4 5 6 7 8 9 10 11 21 22 23 24 25 26 27 28 29 30 31 SCK instruction 16-bit address data byte 1 SI 0 0 0 0 0 0 1 0 15 14 13 12 2 1 0 7 6 5 4 3 2 1 0 CS 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCK data byte 2 data byte 3 data byte n (32 max) SI 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 DS21227E-page 8  2004 Microchip Technology Inc.

25AA320/25LC320/25C320 3.4 Write Enable (WREN) and Write The following is a list of conditions under which the Disable (WRDI) write enable latch will be reset: (cid:127) Power-up The 25XX320 contains a write enable latch. See (cid:127) WRDI instruction successfully executed Table3-3 for the Write-Protect Functionality Matrix. This latch must be set before any write operation will be (cid:127) WRSR instruction successfully executed completed internally. The WREN instruction will set the (cid:127) WRITE instruction successfully executed latch, and the WRDI will reset the latch. FIGURE 3-4: WRITE ENABLE SEQUENCE CS 0 1 2 3 4 5 6 7 SCK 0 0 0 0 0 1 1 0 SI High-impedance SO FIGURE 3-5: WRITE DISABLE SEQUENCE CS 0 1 2 3 4 5 6 7 SCK 0 0 0 0 0 1 10 0 SI High-impedance SO  2004 Microchip Technology Inc. DS21227E-page 9

25AA320/25LC320/25C320 3.5 Read Status Register Instruction The Write Enable Latch (WEL) bit indicates the status (RDSR) of the write enable latch. When set to a ‘1’, the latch allows writes to the array, when set to a ‘0’, the latch The Read Status Register instruction (RDSR) provides prohibits writes to the array. The state of this bit can access to the Status register. The Status register may always be updated via the WREN or WRDI commands be read at any time, even during a write cycle. The regardless of the state of write protection on the Status Status register is formatted as follows: register. This bit is read-only. 7 6 5 4 3 2 1 0 The Block Protection (BP0 and BP1) bits indicate which blocks are currently write-protected. These bits WPEN X X X BP1 BP0 WEL WIP are set by the user issuing the WRSR instruction. These The Write-In-Process (WIP) bit indicates whether the bits are nonvolatile. 25XX320 is busy with a write operation. When set to a See Figure3-6 for the RDSR timing sequence. ‘1’, a write is in progress; when set to a ‘0’, no write is in progress. This bit is read-only. FIGURE 3-6: READ STATUS REGISTER TIMING SEQUENCE CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCK instruction SI 0 0 0 0 0 1 0 1 data from Status register High-impedance SO 7 6 5 4 3 2 1 0 DS21227E-page 10  2004 Microchip Technology Inc.

25AA320/25LC320/25C320 3.6 Write Status Register Instruction When the chip is hardware write-protected, only writes (WRSR) to nonvolatile bits in the Status register are disabled. See Table 3-3 for a matrix of functionality on the WPEN The Write Status Register instruction (WRSR) allows the bit. user to select one of four levels of protection for the See Figure3-7 for the WRSR timing sequence. array by writing to the appropriate bits in the Status register. The array is divided up into four segments. TABLE 3-2: ARRAY PROTECTION The user has the ability to write-protect none, one, two, or all four of the segments of the array. The partitioning Array Addresses is controlled as shown in Table3-2. BP1 BP0 Write-Protected The Write-Protect Enable (WPEN) bit is a nonvolatile 0 0 none bit that is available as an enable bit for the WP pin. The Write-Protect (WP) pin and the Write-Protect Enable 0 1 upper 1/4 (WPEN) bit in the Status register control the program- (0C00h - 0FFFh) mable hardware write-protect feature. Hardware write 1 0 upper 1/2 protection is enabled when WP pin is low and the (0800h - 0FFFh) WPEN bit is high. Hardware write protection is disabled 1 1 all when either the WP pin is high or the WPEN bit is low. (0000h - 0FFFh) FIGURE 3-7: WRITE STATUS REGISTER TIMING SEQUENCE CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCK instruction data to Status register SI 0 0 0 0 0 0 0 1 7 6 5 4 3 2 1 0 High-impedance SO  2004 Microchip Technology Inc. DS21227E-page 11

25AA320/25LC320/25C320 3.7 Data Protection 3.8 Power-On State The following protection has been implemented to The 25XX320 powers on in the following state: prevent inadvertent writes to the array: (cid:127) The device is in low-power Standby mode (cid:127) The write enable latch is reset on power-up (CS=1) (cid:127) A WRITE ENABLE instruction must be issued to (cid:127) The write enable latch is reset set the write enable latch (cid:127) SO is in high-impedance state (cid:127) After a byte write, page write or Status register (cid:127) A low level on CS is required to enter active state write, the write enable latch is reset (cid:127) CS must be set high after the proper number of clock cycles to start an internal write cycle (cid:127) Access to the array during an internal write cycle is ignored and programming is continued . TABLE 3-3: WRITE-PROTECT FUNCTIONALITY MATRIX WPEN WP WEL Protected Blocks Unprotected Blocks Status Register x x 0 Protected Protected Protected 0 x 1 Protected Writable Writable 1 Low 1 Protected Writable Protected x High 1 Protected Writable Writable DS21227E-page 12  2004 Microchip Technology Inc.

25AA320/25LC320/25C320 4.0 PACKAGING INFORMATION 4.1 Package Marking Information 8-Lead PDIP (300 mil) Example: XXXXXXXX 25LC320 XXXXXNNN /PNNN YYWW YYWW 8-Lead SOIC (150 mil) Example: XXXXXXXX 25LC320 XXXXYYWW I/SNYYWW NNN NNN 8-Lead TSSOP Example: XXXX 5LBX XYWW IYWW NNN NNN 14-Lead TSSOP Example: XXXXXXXX 25L32 YYWW YYWW NNN NNN Legend: XX...X Customer specific information* Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. * Standard marking consists of Microchip part number, year code, week code, and traceability code. For device markings beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price.  2004 Microchip Technology Inc. DS21227E-page 13

25AA320/25LC320/25C320 8-Lead Plastic Dual In-line (P) – 300 mil (PDIP) E1 D 2 n 1 α E A A2 L c A1 β B1 p eB B Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 8 8 Pitch p .100 2.54 Top to Seating Plane A .140 .155 .170 3.56 3.94 4.32 Molded Package Thickness A2 .115 .130 .145 2.92 3.30 3.68 Base to Seating Plane A1 .015 0.38 Shoulder to Shoulder Width E .300 .313 .325 7.62 7.94 8.26 Molded Package Width E1 .240 .250 .260 6.10 6.35 6.60 Overall Length D .360 .373 .385 9.14 9.46 9.78 Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43 Lead Thickness c .008 .012 .015 0.20 0.29 0.38 Upper Lead Width B1 .045 .058 .070 1.14 1.46 1.78 Lower Lead Width B .014 .018 .022 0.36 0.46 0.56 Overall Row Spacing § eB .310 .370 .430 7.87 9.40 10.92 Mold Draft Angle Top α 5 10 15 5 10 15 Mold Draft Angle Bottom β 5 10 15 5 10 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-018 DS21227E-page 14  2004 Microchip Technology Inc.

25AA320/25LC320/25C320 8-Lead Plastic Small Outline (SN) –Narrow, 150 mil (SOIC) E E1 p D 2 B n 1 h α 45° c A A2 φ β L A1 Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 8 8 Pitch p .050 1.27 Overall Height A .053 .061 .069 1.35 1.55 1.75 Molded Package Thickness A2 .052 .056 .061 1.32 1.42 1.55 Standoff § A1 .004 .007 .010 0.10 0.18 0.25 Overall Width E .228 .237 .244 5.79 6.02 6.20 Molded Package Width E1 .146 .154 .157 3.71 3.91 3.99 Overall Length D .189 .193 .197 4.80 4.90 5.00 Chamfer Distance h .010 .015 .020 0.25 0.38 0.51 Foot Length L .019 .025 .030 0.48 0.62 0.76 Foot Angle φ 0 4 8 0 4 8 Lead Thickness c .008 .009 .010 0.20 0.23 0.25 Lead Width B .013 .017 .020 0.33 0.42 0.51 Mold Draft Angle Top α 0 12 15 0 12 15 Mold Draft Angle Bottom β 0 12 15 0 12 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-057  2004 Microchip Technology Inc. DS21227E-page 15

25AA320/25LC320/25C320 8-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP) E E1 p D 2 1 n B α A c φ A1 A2 β L Units INCHES MILLIMETERS* Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 8 8 Pitch p .026 0.65 Overall Height A .043 1.10 Molded Package Thickness A2 .033 .035 .037 0.85 0.90 0.95 Standoff § A1 .002 .004 .006 0.05 0.10 0.15 Overall Width E .246 .251 .256 6.25 6.38 6.50 Molded Package Width E1 .169 .173 .177 4.30 4.40 4.50 Molded Package Length D .114 .118 .122 2.90 3.00 3.10 Foot Length L .020 .024 .028 0.50 0.60 0.70 Foot Angle φ 0 4 8 0 4 8 Lead Thickness c .004 .006 .008 0.09 0.15 0.20 Lead Width B .007 .010 .012 0.19 0.25 0.30 Mold Draft Angle Top α 0 5 10 0 5 10 Mold Draft Angle Bottom β 0 5 10 0 5 10 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005” (0.127mm) per side. JEDEC Equivalent: MO-153 Drawing No. C04-086 DS21227E-page 16  2004 Microchip Technology Inc.

25AA320/25LC320/25C320 14-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP) E E1 p D 2 n 1 B α A c φ β A1 A2 L Units INCHES MILLIMETERS* Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 14 14 Pitch p .026 0.65 Overall Height A .043 1.10 Molded Package Thickness A2 .033 .035 .037 0.85 0.90 0.95 Standoff § A1 .002 .004 .006 0.05 0.10 0.15 Overall Width E .246 .251 .256 6.25 6.38 6.50 Molded Package Width E1 .169 .173 .177 4.30 4.40 4.50 Molded Package Length D .193 .197 .201 4.90 5.00 5.10 Foot Length L .020 .024 .028 0.50 0.60 0.70 Foot Angle φ 0 4 8 0 4 8 Lead Thickness c .004 .006 .008 0.09 0.15 0.20 Lead Width B .007 .010 .012 0.19 0.25 0.30 Mold Draft Angle Top α 0 5 10 0 5 10 Mold Draft Angle Bottom β 0 5 10 0 5 10 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005” (0.127mm) per side. JEDEC Equivalent: MO-153 Drawing No. C04-087  2004 Microchip Technology Inc. DS21227E-page 17

25AA320/25LC320/25C320 APPENDIX A: REVISION HISTORY Revision D Corrections to Section 1.0, Electrical Characteristics. Revision E Revise Endurance from 100K to 1M. DS21227E-page 18  2004 Microchip Technology Inc.

25AA320/25LC320/25C320 ON-LINE SUPPORT SYSTEMS INFORMATION AND UPGRADE HOT LINE Microchip provides on-line support on the Microchip World Wide Web site. The Systems Information and Upgrade Line provides The web site is used by Microchip as a means to make system users a listing of the latest versions of all of files and information easily available to customers. To Microchip's development systems software products. view the site, the user must have access to the Internet Plus, this line provides information on how customers and a web browser, such as Netscape® or Microsoft® can receive the most current upgrade kits. The Hot Line Internet Explorer. Files are also available for FTP Numbers are: download from our FTP site. 1-800-755-2345 for U.S. and most of Canada, and 1-480-792-7302 for the rest of the world. Connecting to the Microchip Internet Web Site 042003 The Microchip web site is available at the following URL: www.microchip.com The file transfer site is available by using an FTP service to connect to: ftp://ftp.microchip.com The web site and file transfer site provide a variety of services. Users may download files for the latest Development Tools, Data Sheets, Application Notes, User's Guides, Articles and Sample Programs. A vari- ety of Microchip specific business information is also available, including listings of Microchip sales offices, distributors and factory representatives. Other data available for consideration is: (cid:127) Latest Microchip Press Releases (cid:127) Technical Support Section with Frequently Asked Questions (cid:127) Design Tips (cid:127) Device Errata (cid:127) Job Postings (cid:127) Microchip Consultant Program Member Listing (cid:127) Links to other useful web sites related to Microchip Products (cid:127) Conferences for products, Development Systems, technical information and more (cid:127) Listing of seminars and events  2004 Microchip Technology Inc. DS21227E-page 19

25AA320/25LC320/25C320 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod- uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: Technical Publications Manager Total Pages Sent ________ RE: Reader Response From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y N Device: 25AA320/25LC320/25C320 Literature Number: DS21227E Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS21227E-page 20  2004 Microchip Technology Inc.

25AA320/25LC320/25C320 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX Examples: a) 25LC320-I/SN: Industrial Temp., Device Temperature Package SOIC package Range b) 25LC320T-I/SN: Tape and Reel, Industrial Temp., SOIC package Device: 25AA320: 32 Kbit 1.8V SPI Serial EEPROM c) 25LC320-E/SN: Extended Temp., 25AA320T: 32 Kbit 1.8V SPI Serial EEPROM SOIC package (Tape and Reel) 25AA320X 32-bit 1.8V SPI Serial EEPROM d) 25C320-I/SN: Industrial Temp., in alternate pinout (ST only) SOIC package 25AA320XT 32-bit 1.8V SPI Serial EEPROM e) 25C320T-I/SN: Tape and Reel, in alternate pinout Tape and Reel Industrial Temp., SOIC package (ST only) f) 25C320-I/ST: Industrial Temp., 25LC320: 32 Kbit 2.5V SPI Serial EEPROM TSSOP package 25LC320T: 32 Kbit 2.5V SPI Serial EEPROM g) 25C320-E/SN: Extended Temp., (Tape and Reel) SOIC package 25LC320X 32-bit 2.5V SPI Serial EEPROM in alternate pinout (ST only) 25LC320XT 32-bit 2.5V SPI Serial EEPROM in alternate pinout Tape and Reel (ST only) 25C320: 32 Kbit 5V SPI Serial EEPROM 25C320T: 32 Kbit 5V SPI Serial EEPROM (Tape and Reel) 25C320X 32-bit 5V SPI Serial EEPROM in alternate pinout (ST only) 25C320XT 32-bit 5V SPI Serial EEPROM in alternate pinout Tape and Reel (ST only) Temperature I = -40°C to +85°C Range: E = -40°C to +125°C Package: P = Plastic DIP (300 mil body), 8-lead SN = Plastic SOIC (150 mil body), 8-lead ST = Plastic TSSOP (4.4 mm body), 8-lead ST14 = Plastic TSSOP (4.4 mm body), 14-lead Sales and Support Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. Your local Microchip sales office 2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277 3. The Microchip Worldwide Site (www.microchip.com) Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products.  2004 Microchip Technology Inc. DS21227E-page 21

25AA320/25LC320/25C320 NOTES: DS21227E-page 22  2004 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices: (cid:127) Microchip products meet the specification contained in their particular Microchip Data Sheet. (cid:127) Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. (cid:127) There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. (cid:127) Microchip is willing to work with the customer who is concerned about the integrity of their code. (cid:127) Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is intended through suggestion only The Microchip name and logo, the Microchip logo, Accuron, and may be superseded by updates. It is your responsibility to dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART, ensure that your application meets with your specifications. PROMATE, PowerSmart, rfPIC, and SmartShunt are No representation or warranty is given and no liability is registered trademarks of Microchip Technology Incorporated assumed by Microchip Technology Incorporated with respect in the U.S.A. and other countries. to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such AmpLab, FilterLab, MXDEV, MXLAB, PICMASTER, SEEVAL, use or otherwise. Use of Microchip’s products as critical SmartSensor and The Embedded Control Solutions Company components in life support systems is not authorized except are registered trademarks of Microchip Technology with express written approval by Microchip. No licenses are Incorporated in the U.S.A. conveyed, implicitly or otherwise, under any intellectual Analog-for-the-Digital Age, Application Maestro, dsPICDEM, property rights. dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2004, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona and Mountain View, California in October 2003. The Company’s quality system processes and procedures are for its PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.  2004 Microchip Technology Inc. DS21227E-page 23

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Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: M icrochip: 25C320-I/SN 25AA320-I/P 25LC320X-I/ST 25LC320-E/P 25LC320-I/SN 25C320/P 25LC320T/SN 25C320-E/SN 25LC320/SN 25AA320XT-I/ST 25C320T-I/SN 25LC320T-E/SN 25LC320T-I/SN 25AA320T-I/SN 25AA320X-I/ST 25C320-I/P 25LC320-E/SN 25AA320-I/SN 25C320/SN 25C320-E/P 25C320T-E/SN 25LC320XT-I/ST 25LC320/P 25C320T/SN 25AA320AXT-I/ST