25AA256/25LC256 256K SPI Bus Serial EEPROM Device Selection Table Part Number VCC Range Page Size Temp. Ranges Packages 25LC256 2.5-5.5V 64 Byte I, E P, SN, SM, ST, MF 25AA256 1.8-5.5V 64 Byte I, E P, SN, SM, ST, MF Features Description • Max. Clock 10 MHz The Microchip Technology Inc. 25AA256/25LC256 • Low-Power CMOS Technology: (25XX256(1)) are 256 Kbit Serial Electrically Erasable PROMs. The memory is accessed via a simple Serial - Max. Write Current: 5 mA at 5.5V, 10 MHz Peripheral Interface (SPI) compatible serial bus. The - Read Current: 6 mA at 5.5V, 10 MHz bus signals required are a clock input (SCK) plus - Standby Current: 1 A at 5.5V separate data in (SI) and data out (SO) lines. Access to • 32,768 x 8-Bit Organization the device is controlled through a Chip Select (CS) • 64-Byte Page input. • Self-Timed Erase and Write Cycles (5 ms max.) Communication to the device can be paused via the • Block Write Protection: hold pin (HOLD). While the device is paused, - Protect none, 1/4, 1/2 or all of array transitions on its inputs will be ignored, with the exception of Chip Select, allowing the host to service • Built-In Write Protection: higher priority interrupts. - Power-on/off data protection circuitry The 25XX256 is available in standard packages includ- - Write enable latch ing 8-lead PDIP and SOIC, and advanced packaging - Write-protect pin including 8-lead DFN and 8-lead TSSOP. • Sequential Read Note1: 25XX256 is used in this document as a • High Reliability: generic part number for the 25AA256/ - Endurance: 1,000,000 erase/write cycles 25L256 devices. - Data retention: > 200 years - ESD protection: > 4000V Package Types (not to scale) • Temperature Ranges Supported: DFN PDIP/SOIC - Industrial (I): -40C to +85C (MF) (P, SN, SM) - Extended (E): -40°C to +125°C CS 1 8 VCC CS 1 8 VCC • RoHS Compliant SO 2 7 HOLD SO 2 7 HOLD • Automotive AEC-Q100 Qualified WP 3 6 SCK WP 3 6 SCK Pin Function Table VSS 4 5 SI VSS 4 5 SI Name Function Rotated TSSOP (ST) CS Chip Select Input HOLD 1 8 SCK SO Serial Data Output VCC 2 7 SI WP Write-Protect CS 3 6 VSS SO 4 5 WP VSS Ground SI Serial Data Input TSSOP (ST) SCK Serial Clock Input CS 1 8 VCC HOLD Hold Input SO 2 7 HOLD VCC Supply Voltage WP 3 6 SCK VSS 4 5 SI  2003-2019 Microchip Technology Inc. DS20001822H-page 1

25AA256/25LC256 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings (†) VCC.............................................................................................................................................................................6.5V All inputs and outputs w.r.t. VSS..........................................................................................................-0.6V to VCC +1.0V Storage temperature.................................................................................................................................-65°C to 150°C Ambient temperature under bias...............................................................................................................-40°C to 125°C ESD protection on all pins..........................................................................................................................................4kV † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an extended period of time may affect device reliability. TABLE 1-1: DC CHARACTERISTICS Industrial (I): TA = -40°C to +85°C VCC = 1.8V to 5.5V DC CHARACTERISTICS Extended (E): TA = -40°C to +125°C VCC = 1.8V to 5.5V Param. Sym. Characteristic Min. Typ.(2) Max. Units Test Conditions No. D001 VIH High-level input 0.7 VCC — VCC +1 V voltage D002 VIL Low-level input -0.3 — 0.3 VCC V VCC2.5V D003 VIL voltage -0.3 — 0.2 VCC V VCC < 2.5V D004 VOL Low-level output — — 0.4 V IOL = 2.1mA, VCC = 4.5V D005 VOL voltage — — 0.2 V IOL = 1.0mA, VCC = 2.5V D006 VOH High-level output VCC -0.5 — — V IOH = -400A voltage D007 ILI Input leakage current — — ±1 A CS = VCC, VIN = VSS OR VCC D008 ILO Output leakage — — ±1 A CS = VCC, VOUT = VSS OR VCC current D009 CINT Internal Capacitance — — 7 pF TA = 25°C, FCLK = 1.0MHz, (all inputs and VCC = 5.0V (Note 1) outputs) D010 ICC Read — 2.5 6 mA VCC = 5.5V; FCLK = 10.0MHz; SO = Open Operating Current — 0.5 2.5 mA VCC = 2.5V; FCLK = 5.0MHz; SO = Open D011 ICC Write — 0.6 5 mA VCC = 5.5V — 0.15 3 mA VCC = 2.5V D012 ICCS — 0.1 5 A CS = VCC = 5.5V, Inputs tied to VCC Standby Current or VSS, 125°C — 1 A CS = VCC = 5.5V, Inputs tied to VCC or VSS, 85°C Note 1: This parameter is periodically sampled and not 100% tested. 2: Typical measurements taken at room temperature (25°C).  2003-2019 Microchip Technology Inc. DS20001822H-page 2

25AA256/25LC256 TABLE 1-2: AC CHARACTERISTICS Industrial (I): TA = -40°C to +85°C VCC = 1.8V to 5.5V AC CHARACTERISTICS Extended (E): TA = -40°C to +125°C VCC = 1.8V to 5.5V Param. Sym. Characteristic Min. Max. Units Test Conditions No. 1 FCLK Clock Frequency — 10 MHz 4.5V Vcc  5.5V — 5 MHz 2.5V Vcc  4.5V — 3 MHz 1.8V Vcc  2.5V 2 TCSS CS Setup Time 50 — ns 4.5V Vcc  5.5V 100 — ns 2.5V Vcc  4.5V 150 — ns 1.8V Vcc  2.5V 3 TCSH CS Hold Time 100 — ns 4.5V Vcc  5.5V 200 — ns 2.5V Vcc  4.5V 250 — ns 1.8V Vcc  2.5V 4 TCSD CS Disable Time 50 — ns — 5 Tsu Data Setup Time 10 — ns 4.5V Vcc  5.5V 20 — ns 2.5V Vcc  4.5V 30 — ns 1.8V Vcc  2.5V 6 THD Data Hold Time 20 — ns 4.5V Vcc  5.5V 40 — ns 2.5V Vcc  4.5V 50 — ns 1.8V Vcc  2.5V 7 TR CLK Rise Time — 100 ns (Note1) 8 TF CLK Fall Time — 100 ns (Note1) 9 THI Clock High Time 50 — ns 4.5V Vcc  5.5V 100 — ns 2.5V Vcc  4.5V 150 — ns 1.8V Vcc  2.5V 10 TLO Clock Low Time 50 — ns 4.5V Vcc  5.5V 100 — ns 2.5V Vcc  4.5V 150 — ns 1.8V Vcc  2.5V 11 TCLD Clock Delay Time 50 — ns — 12 TCLE Clock Enable Time 50 — ns — 13 TV Output Valid from Clock — 50 ns 4.5V Vcc  5.5V Low — 100 ns 2.5V Vcc  4.5V — 160 ns 1.8V Vcc  2.5V 14 THO Output Hold Time 0 — ns (Note1) 15 TDIS Output Disable Time — 40 ns 4.5V Vcc  5.5V (Note1) — 80 ns 2.5V Vcc  4.5V (Note1) — 160 ns 1.8V Vcc  2.5V (Note1) 16 THS HOLD Setup Time 20 — ns 4.5V Vcc  5.5V 40 — ns 2.5V Vcc  4.5V 80 — ns 1.8V Vcc  2.5V 17 THH HOLD Hold Time 20 — ns 4.5V Vcc  5.5V 40 — ns 2.5V Vcc  4.5V 80 — ns 1.8V Vcc  2.5V Note1: This parameter is periodically sampled and not 100% tested. 2: TWC begins on the rising edge of CS after a valid write sequence and ends when the internal write cycle is complete. 3: This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total Endurance™ Model which can be obtained from Microchip’s website at www.microchip.com.  2003-2019 Microchip Technology Inc. DS20001822H-page 3

25AA256/25LC256 TABLE 1-2: AC CHARACTERISTICS (CONTINUED) Industrial (I): TA = -40°C to +85°C VCC = 1.8V to 5.5V AC CHARACTERISTICS Extended (E): TA = -40°C to +125°C VCC = 1.8V to 5.5V Param. Sym. Characteristic Min. Max. Units Test Conditions No. 18 THZ HOLD Low to Output — 30 ns 4.5V Vcc  5.5V (Note1) High-Z — 60 ns 2.5V Vcc  4.5V (Note1) — 160 ns 1.8V Vcc  2.5V (Note1) 19 THV HOLD High to Output — 30 ns 4.5V Vcc  5.5V Valid — 60 ns 2.5V Vcc  4.5V — 160 ns 1.8V Vcc  2.5V 20 TWC Internal Write Cycle — 5 ms (Note2) Time 21 — Endurance 1M — E/W 25°C, VCC = 5.5V (Note3) Cycles Note1: This parameter is periodically sampled and not 100% tested. 2: TWC begins on the rising edge of CS after a valid write sequence and ends when the internal write cycle is complete. 3: This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total Endurance™ Model which can be obtained from Microchip’s website at www.microchip.com. TABLE 1-3: AC TEST CONDITIONS AC Waveform: VLO = 0.2V — VHI = VCC – 0.2V (Note1) VHI = 4.0V (Note2) CL = 50 pF — Timing Measurement Reference Level Input 0.5 VCC Output 0.5 VCC Note1: For VCC  4.0V 2: For VCC > 4.0V  2003-2019 Microchip Technology Inc. DS20001822H-page 4

25AA256/25LC256 FIGURE 1-1: HOLD TIMING CS 17 17 16 16 SCK 18 19 High-Impedance SO n + 2 n + 1 n n n - 1 Don’t Care 5 SI n + 2 n + 1 n n n - 1 HOLD FIGURE 1-2: SERIAL INPUT TIMING 4 CS 12 2 11 7 Mode 1,1 8 3 SCK Mode 0,0 5 6 SI MSB in LSB in High-Impedance SO FIGURE 1-3: SERIAL OUTPUT TIMING CS 9 10 3 Mode 1,1 SCK Mode 0,0 13 15 14 SO MSB out ISB out Don’t Care SI  2003-2019 Microchip Technology Inc. DS20001822H-page 5

25AA256/25LC256 2.0 FUNCTIONAL DESCRIPTION 2.1 Principles of Operation 2.3 Write Sequence The 25XX256 is a 32,768-byte Serial EEPROM Prior to any attempt to write data to the 25XX256, the designed to interface directly with the Serial Peripheral write enable latch must be set by issuing the WREN Interface (SPI) port of many of today’s popular instruction (Figure2-4). This is done by setting CS low microcontroller families, including Microchip’s PIC® and then clocking out the proper instruction into the microcontrollers. It may also interface with microcon- 25XX256. After all eight bits of the instruction are trollers that do not have a built-in SPI port by using transmitted, the CS must be brought high to set the discrete I/O lines programmed properly in firmware to write enable latch. If the write operation is initiated match the SPI protocol. immediately after the WREN instruction without CS being brought high, the data will not be written to the The 25XX256 contains an 8-bit instruction register. The array because the write enable latch will not have been device is accessed via the SI pin, with data being properly set. clocked in on the rising edge of SCK. The CS pin must be low and the HOLD pin must be high for the entire Once the write enable latch is set, the user may operation. proceed by setting the CS low, issuing a WRITE instruction, followed by the 16-bit address, with the first Table2-1 contains a list of the possible instruction MSB of the address being a “don’t care” bit, and then bytes and format for device operation. All instructions, the data to be written. Up to 64 bytes of data can be addresses, and data are transferred MSB first, LSB sent to the device before a write cycle is necessary. last. The only restriction is that all of the bytes must reside Data (SI) is sampled on the first rising edge of SCK in the same page. after CS goes low. If the clock line is shared with other peripheral devices on the SPI bus, the user can assert Note: Page write operations are limited to the HOLD input and place the 25XX256 in ‘HOLD’ writing bytes within a single physical page, mode. After releasing the HOLD pin, operation will regardless of the number of bytes resume from the point when the HOLD was asserted. actually being written. Physical page boundaries start at addresses that are 2.2 Read Sequence integer multiples of the page buffer size (or ‘page size’) and, end at addresses that The device is selected by pulling CS low. The 8-bit are integer multiples of page size – 1. If a READ instruction is transmitted to the 25XX256 page write command attempts to write followed by the 16-bit address, with the first MSB of the across a physical page boundary, the address being a “don’t care” bit. After the correct READ result is that the data wraps around to the instruction and address are sent, the data stored in the beginning of the current page (overwriting memory at the selected address is shifted out on the data previously stored there), instead of SO pin. The data stored in the memory at the next being written to the next page as might be address can be read sequentially by continuing to expected. It is therefore necessary for the provide clock pulses. The internal Address Pointer is application software to prevent page write automatically incremented to the next higher address operations that would attempt to cross a after each byte of data is shifted out. When the highest page boundary. address is reached (7FFFh), the address counter rolls For the data to be actually written to the array, the CS over to address 0000h allowing the read cycle to be must be brought high after the Least Significant bit (D0) continued indefinitely. The read operation is terminated of the nth data byte has been clocked in. If CS is by raising the CS pin (Figure2-1). brought high at any other time, the write operation will not be completed. Refer to Figure2-2 and Figure2-3 for more detailed illustrations on the byte write sequence and the page write sequence, respectively. While the write is in progress, the STATUS register may be read to check the status of the Write-in-process (WIP) bit (Figure2-6). A read attempt of a memory array location will not be possible during a write cycle. When the write cycle is completed, the write enable latch is reset.  2003-2019 Microchip Technology Inc. DS20001822H-page 6

25AA256/25LC256 BLOCK DIAGRAM STATUS HV Generator Register EEPROM I/O Control Memory X Array Control Logic Logic Dec Page Latches SI SO Y Decoder CS SCK Sense Amp. HOLD R/W Control WP VCC VSS TABLE 2-1: INSTRUCTION SET Instruction Name Instruction Format Description READ 0000 0011 Read data from memory array beginning at selected address WRITE 0000 0010 Write data to memory array beginning at selected address WRDI 0000 0100 Reset the write enable latch (disable write operations) WREN 0000 0110 Set the write enable latch (enable write operations) RDSR 0000 0101 Read STATUS register WRSR 0000 0001 Write STATUS register FIGURE 2-1: READ SEQUENCE CS 0 1 2 3 4 5 6 7 8 9 10 11 21 22 23 24 25 26 27 28 29 30 31 SCK Instruction 16-bit Address SI 0 0 0 0 0 0 1 1 15 14 13 12 2 1 0 Data Out High-Impedance SO 7 6 5 4 3 2 1 0  2003-2019 Microchip Technology Inc. DS20001822H-page 7

25AA256/25LC256 FIGURE 2-2: BYTE WRITE SEQUENCE CS Twc 0 1 2 3 4 5 6 7 8 9 10 11 21 22 23 24 25 26 27 28 29 30 31 SCK Instruction 16-bit Address Data Byte SI 0 0 0 0 0 0 1 0 15 14 13 12 2 1 0 7 6 5 4 3 2 1 0 High-Impedance SO FIGURE 2-3: PAGE WRITE SEQUENCE CS 0 1 2 3 4 5 6 7 8 9 10 11 21 22 23 24 25 26 27 28 29 30 31 SCK Instruction 16-bit Address Data Byte 1 SI 0 0 0 0 0 0 1 0 15 14 13 12 2 1 0 7 6 5 4 3 2 1 0 CS 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCK Data Byte 2 Data Byte 3 Data Byte n (64 max) SI 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0  2003-2019 Microchip Technology Inc. DS20001822H-page 8

25AA256/25LC256 2.4 Write Enable (WREN) and Write The following is a list of conditions under which the Disable (WRDI) write enable latch will be reset: • Power-up The 25XX256 contains a write enable latch. See • WRDI instruction successfully executed Table2-1 for the Write-Protect Functionality Matrix. This latch must be set before any write operation will be • WRSR instruction successfully executed completed internally. The WREN instruction will set the • WRITE instruction successfully executed latch, and the WRDI will reset the latch. FIGURE 2-4: WRITE ENABLE SEQUENCE (WREN) CS 0 1 2 3 4 5 6 7 SCK SI 0 0 0 0 0 1 1 0 High-Impedance SO FIGURE 2-5: WRITE DISABLE SEQUENCE (WRDI) CS 0 1 2 3 4 5 6 7 SCK SI 0 0 0 0 0 1 10 0 High-Impedance SO  2003-2019 Microchip Technology Inc. DS20001822H-page 9

25AA256/25LC256 2.5 Read Status Register Instruction The Write Enable Latch (WEL) bit indicates the status (RDSR) of the write enable latch and is read-only. When set to a ‘1’, the latch allows writes to the array, when set to a The Read Status Register instruction (RDSR) provides ‘0’, the latch prohibits writes to the array. The state of access to the STATUS register. The STATUS register this bit can always be updated via the WREN or WRDI may be read at any time, even during a write cycle. The commands, regardless of the state of write protection STATUS register is formatted as follows: on the STATUS register. These commands are shown in Figure2-4 and Figure2-5. TABLE 2-2: STATUS REGISTER The Block Protection (BP0 and BP1) bits indicate 7 6 5 4 3 2 1 0 which blocks are currently write-protected. These bits are set by the user issuing the WRSR instruction. These W/R - - - W/R W/R R R bits are nonvolatile, and are shown in Table2-3. WPEN x x x BP1 BP0 WEL WIP See Figure2-6 for the RDSR timing sequence. W/R = writable/readable. R = read-only. The Write-In-Process (WIP) bit indicates whether the 25XX256 is busy with a write operation. When set to a ‘1’, a write is in progress, when set to a ‘0’, no write is in progress. This bit is read-only. FIGURE 2-6: READ STATUS REGISTER TIMING SEQUENCE (RDSR) CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCK Instruction SI 0 0 0 0 0 1 0 1 Data from STATUS Register High-Impedance SO 7 6 5 4 3 2 1 0 Note: Bits 7-1 of the status register are undetermined during a write cycle.  2003-2019 Microchip Technology Inc. DS20001822H-page 10

25AA256/25LC256 2.6 Write Status Register Instruction See Figure2-7 for the WRSR timing sequence. (WRSR) TABLE 2-3: ARRAY PROTECTION The Write Status Register instruction (WRSR) allows the user to write to the nonvolatile bits in the STATUS Array Addresses BP1 BP0 register as shown in Table2-2. The user is able to Write-Protected select one of four levels of protection for the array by 0 0 none writing to the appropriate bits in the STATUS register. The array is divided up into four segments. The user 0 1 upper 1/4 has the ability to write-protect none, one, two, or all four (6000h-7FFFh) of the segments of the array. The partitioning is 1 0 upper 1/2 controlled as shown in Table2-3. (4000h-7FFFh) The Write-Protect Enable (WPEN) bit is a nonvolatile 1 1 all bit that is available as an enable bit for the WP pin. The (0000h-7FFFh) Write-Protect (WP) pin and the Write-Protect Enable (WPEN) bit in the STATUS register control the programmable hardware write-protect feature. Hard- ware write protection is enabled when WP pin is low and the WPEN bit is high. Hardware write protection is disabled when either the WP pin is high or the WPEN bit is low. When the chip is hardware write-protected, only writes to nonvolatile bits in the STATUS register are disabled. See Table2-1 for a matrix of functionality on the WPEN bit. FIGURE 2-7: WRITE STATUS REGISTER TIMING SEQUENCE (WRSR) CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCK Instruction Data to STATUS Register SI 0 0 0 0 0 0 0 1 7 6 5 4 3 2 1 0 High-Impedance SO Note: An internal write cycle (TWC) is initiated on the rising edge of CS after a valid write STATUS register sequence.  2003-2019 Microchip Technology Inc. DS20001822H-page 11

25AA256/25LC256 2.7 Data Protection 2.8 Power-On State The following protection has been implemented to The 25XX256 powers on in the following state: prevent inadvertent writes to the array: • The device is in low-power Standby mode • The write enable latch is reset on power-up (CS=1) • A write enable instruction must be issued to set • The write enable latch is reset the write enable latch • SO is in high-impedance state • After a byte write, page write or STATUS register • A high-to-low-level transition on CS is required to write, the write enable latch is reset enter active state • CS must be set high after the proper number of clock cycles to start an internal write cycle • Access to the array during an internal write cycle is ignored and programming is continued TABLE 2-1: WRITE-PROTECT FUNCTIONALITY MATRIX WEL WPEN WP pin Protected Blocks Unprotected Blocks STATUS Register (SR bit 1) (SR bit 7) 0 x x Protected Protected Protected 1 0 x Protected Writable Writable 1 1 0 (low) Protected Writable Protected 1 1 1 (high) Protected Writable Writable x = don’t care  2003-2019 Microchip Technology Inc. DS20001822H-page 12

25AA256/25LC256 3.0 PIN DESCRIPTIONS The WP pin function is blocked when the WPEN bit in the STATUS register is low. This allows the user to The descriptions of the pins are listed in Table3-1. install the 25XX256 in a system with WP pin grounded and still be able to write to the STATUS register. The TABLE 3-1: PIN FUNCTION TABLE WP pin functions will be enabled when the WPEN bit is set high. PDIP/SOIC Rotated Name Function TSSOP/DFN TSSOP 3.4 Serial Input (SI) CS 1 3 Chip Select Input The SI pin is used to transfer data into the device. It SO 2 4 Serial Data Output receives instructions, addresses and data. Data is latched on the rising edge of the serial clock. WP 3 5 Write-Protect Pin VSS 4 6 Ground 3.5 Serial Clock (SCK) SI 5 7 Serial Data Input The SCK is used to synchronize the communication SCK 6 8 Serial Clock Input between a master and the 25XX256. Instructions, HOLD 7 1 Hold Input addresses or data present on the SI pin are latched on the rising edge of the clock input, while data on the SO VCC 8 2 Supply Voltage pin is updated after the falling edge of the clock input. 3.1 Chip Select (CS) 3.6 Hold (HOLD) A low level on this pin selects the device. A high level The HOLD pin is used to suspend transmission to the deselects the device and forces it into Standby mode. 25XX256 while in the middle of a serial sequence with- However, a programming cycle which is already out having to retransmit the entire sequence again. It initiated or in progress will be completed, regardless of must be held high any time this function is not being the CS input signal. If CS is brought high during a used. Once the device is selected and a serial program cycle, the device will go into Standby mode as sequence is underway, the HOLD pin may be pulled soon as the programming cycle is complete. When the low to pause further serial communication without device is deselected, SO goes to the high-impedance resetting the serial sequence. The HOLD pin must be state, allowing multiple parts to share the same SPI brought low while SCK is low, otherwise the HOLD bus. A low-to-high transition on CS after a valid write function will not be invoked until the next SCK high-to- sequence initiates an internal write cycle. After power- low transition. The 25XX256 must remain selected up, a low level on CS is required prior to any sequence during this sequence. The SI, SCK and SO pins are in being initiated. a high-impedance state during the time the device is paused and transitions on these pins will be ignored. To 3.2 Serial Output (SO) resume serial communication, HOLD must be brought The SO pin is used to transfer data out of the 25XX256. high while the SCK pin is low, otherwise serial During a read cycle, data is shifted out on this pin after communication will not resume. Lowering the HOLD the falling edge of the serial clock. line at any time will tri-state the SO line. 3.3 Write-Protect (WP) This pin is used in conjunction with the WPEN bit in the STATUS register to prohibit writes to the nonvolatile bits in the STATUS register. When WP is low and WPEN is high, writing to the nonvolatile bits in the STATUS register is disabled. All other operations function normally. When WP is high, all functions, including writes to the nonvolatile bits in the STATUS register, operate normally. If the WPEN bit is set, WP low during a STATUS register write sequence will disable writing to the STATUS register. If an internal write cycle has already begun, WP going low will have no effect on the write.  2003-2019 Microchip Technology Inc. DS20001822H-page 13

25AA256/25LC256 4.0 PACKAGING INFORMATION 4.1 Package Marking Information 8-Lead PDIP Example: XXXXXXXX 25LC256 T/XXXNNN I/P e 3 1L7 YYWW 1929 8-Lead SOIJ Example: 8-Lead SOIC Example: XXXXXXXX 25LC256 XXXXXXXT 25LC256I XXXXXXXX I/SM e3 XXXXYYWW SN e 3 1929 YYWWNNN 192913F NNN 13F 8-Lead TSSOP Example: TSSOP 1st Line Marking Codes XXXX 5LE Device Standard Rotated TYWW I929 NNN 13F 25AA256 5AE 5AEX 25LC256 5LE 5LEX 8-Lead DFN Example: XXXXXXX 25LC256 T/XXXXX I/MF e3 YYWW 1929 NNN 13F Legend: XX...X Part number or part number code T Temperature (I, E) Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code (2 characters for small packages) e3 RoHS-compliant JEDEC designator for Matte Tin (Sn) Note: For very small packages with no room for the RoHS-compliant JEDEC designator e 3 , the marking will only appear on the outer carton or reel label. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2003-2019 Microchip Technology Inc. DS20001822H-page 14

25AA256/25LC256 8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D A N B E1 NOTE 1 1 2 TOP VIEW E C A A2 PLANE L c A1 e eB 8X b1 8X b .010 C SIDE VIEW END VIEW Microchip Technology Drawing No. C04-018-P Rev E Sheet 1 of 2  2003-2019 Microchip Technology Inc. DS20001822H-page 15

25AA256/25LC256 8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging ALTERNATE LEAD DESIGN (NOTE 5) DATUM A DATUM A b b e e 2 2 e e Units INCHES Dimension Limits MIN NOM MAX Number of Pins N 8 Pitch e .100 BSC Top to Seating Plane A - - .210 Molded Package Thickness A2 .115 .130 .195 Base to Seating Plane A1 .015 - - Shoulder to Shoulder Width E .290 .310 .325 Molded Package Width E1 .240 .250 .280 Overall Length D .348 .365 .400 Tip to Seating Plane L .115 .130 .150 Lead Thickness c .008 .010 .015 Upper Lead Width b1 .040 .060 .070 Lower Lead Width b .014 .018 .022 Overall Row Spacing § eB - - .430 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side. 4. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. 5. Lead design above seating plane may vary, based on assembly vendor. Microchip Technology Drawing No. C04-018-P Rev E Sheet 2 of 2  2003-2019 Microchip Technology Inc. DS20001822H-page 16

25AA256/25LC256 (JEITA/EIAJ Standard, Formerly called SOIC) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2003-2019 Microchip Technology Inc. DS20001822H-page 17

25AA256/25LC256 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2003-2019 Microchip Technology Inc. DS20001822H-page 18

25AA256/25LC256 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2003-2019 Microchip Technology Inc. DS20001822H-page 19

25AA256/25LC256 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2X 0.10 C A–B D A D NOTE 5 N E 2 E1 2 E1 E NOTE 1 1 2 e NX b B 0.25 C A–B D NOTE 5 TOP VIEW 0.10 C C A A2 SEATING PLANE 8X 0.10 C A1 SIDE VIEW h R0.13 h R0.13 H 0.23 L SEE VIEW C (L1) VIEW A–A VIEW C Microchip Technology Drawing No. C04-057-SN Rev E Sheet 1 of 2  2003-2019 Microchip Technology Inc. DS20001822H-page 20

25AA256/25LC256 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Pins N 8 Pitch e 1.27 BSC Overall Height A - - 1.75 Molded Package Thickness A2 1.25 - - Standoff § A1 0.10 - 0.25 Overall Width E 6.00 BSC Molded Package Width E1 3.90 BSC Overall Length D 4.90 BSC Chamfer (Optional) h 0.25 - 0.50 Foot Length L 0.40 - 1.27 Footprint L1 1.04 REF Foot Angle 0° - 8° Lead Thickness c 0.17 - 0.25 Lead Width b 0.31 - 0.51 Mold Draft Angle Top 5° - 15° Mold Draft Angle Bottom 5° - 15° Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. 5. Datums A & B to be determined at Datum H. Microchip Technology Drawing No. C04-057-SN Rev E Sheet 2 of 2  2003-2019 Microchip Technology Inc. DS20001822H-page 21

25AA256/25LC256 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging SILK SCREEN C Y1 X1 E RECOMMENDED LAND PATTERN Units MILLIMETERS Dimension Limits MIN NOM MAX Contact Pitch E 1.27 BSC Contact Pad Spacing C 5.40 Contact Pad Width (X8) X1 0.60 Contact Pad Length (X8) Y1 1.55 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing C04-2057-SN Rev E  2003-2019 Microchip Technology Inc. DS20001822H-page 22

25AA256/25LC256 8-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm Body [TSSOP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D N E E1 NOTE 1 1 2 b e c φ A A2 A1 L1 L Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Pins N 8 Pitch e 0.65 BSC Overall Height A – – 1.20 Molded Package Thickness A2 0.80 1.00 1.05 Standoff A1 0.05 – 0.15 Overall Width E 6.40 BSC Molded Package Width E1 4.30 4.40 4.50 Molded Package Length D 2.90 3.00 3.10 Foot Length L 0.45 0.60 0.75 Footprint L1 1.00 REF Foot Angle φ 0° – 8° Lead Thickness c 0.09 – 0.20 Lead Width b 0.19 – 0.30 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side. 3. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. MicrochipTechnologyDrawingC04-086B  2003-2019 Microchip Technology Inc. DS20001822H-page 23

25AA256/25LC256 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2003-2019 Microchip Technology Inc. DS20001822H-page 24

25AA256/25LC256 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)(cid:15)(cid:16)(cid:6)(cid:10)(cid:8)(cid:17)(cid:10)(cid:6)(cid:12)(cid:18)(cid:8)(cid:19)(cid:20)(cid:8)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:6)(cid:14)(cid:21)(cid:6)(cid:22)(cid:5)(cid:8)(cid:23)(cid:24)(cid:17)(cid:25)(cid:8)(cid:26)(cid:8)(cid:27)(cid:28)(cid:29)(cid:8)(cid:30)(cid:30)(cid:8)(cid:31)(cid:20)(cid:7) (cid:8)!(cid:15)(cid:17)(cid:19)(cid:3)"# (cid:19)(cid:20)(cid:12)(cid:5)$ -(cid:23)(cid:18)(cid:2)(cid:17)(cid:26)(cid:14)(cid:2)(cid:19)(cid:23)(cid:9)(cid:17)(cid:2)(cid:24)(cid:10)(cid:18)(cid:18)(cid:14)(cid:7)(cid:17)(cid:2)(cid:30)(cid:11)(cid:24)(cid:28)(cid:11)(cid:29)(cid:14)(cid:2)(cid:13)(cid:18)(cid:11)(cid:25)(cid:6)(cid:7)(cid:29)(cid:9)(cid:21)(cid:2)(cid:30)(cid:12)(cid:14)(cid:11)(cid:9)(cid:14)(cid:2)(cid:9)(cid:14)(cid:14)(cid:2)(cid:17)(cid:26)(cid:14)(cid:2)$(cid:6)(cid:24)(cid:18)(cid:23)(cid:24)(cid:26)(cid:6)(cid:30)(cid:2)(cid:5)(cid:11)(cid:24)(cid:28)(cid:11)(cid:29)(cid:6)(cid:7)(cid:29)(cid:2)#(cid:30)(cid:14)(cid:24)(cid:6)(cid:16)(cid:6)(cid:24)(cid:11)(cid:17)(cid:6)(cid:23)(cid:7)(cid:2)(cid:12)(cid:23)(cid:24)(cid:11)(cid:17)(cid:14)(cid:13)(cid:2)(cid:11)(cid:17)(cid:2) (cid:26)(cid:17)(cid:17)(cid:30)*..(cid:25)(cid:25)(cid:25)(cid:4)(cid:19)(cid:6)(cid:24)(cid:18)(cid:23)(cid:24)(cid:26)(cid:6)(cid:30)(cid:4)(cid:24)(cid:23)(cid:19).(cid:30)(cid:11)(cid:24)(cid:28)(cid:11)(cid:29)(cid:6)(cid:7)(cid:29) (cid:2) e D L b N N K E E2 EXPOSEDPAD NOTE1 NOTE1 1 2 2 1 D2 TOPVIEW BOTTOMVIEW A A3 A1 NOTE2 /(cid:7)(cid:6)(cid:17)(cid:9) $0110$%+%,# !(cid:6)(cid:19)(cid:14)(cid:7)(cid:9)(cid:6)(cid:23)(cid:7)(cid:2)1(cid:6)(cid:19)(cid:6)(cid:17)(cid:9) $02 23$ $"4 2(cid:10)(cid:19)(cid:22)(cid:14)(cid:18)(cid:2)(cid:23)(cid:16)(cid:2)(cid:5)(cid:6)(cid:7)(cid:9) 2 5 (cid:5)(cid:6)(cid:17)(cid:24)(cid:26) (cid:14) (cid:3)(cid:4)(cid:27)6(cid:2)(#) 3(cid:8)(cid:14)(cid:18)(cid:11)(cid:12)(cid:12)(cid:2)7(cid:14)(cid:6)(cid:29)(cid:26)(cid:17) " 8(cid:4)58 8(cid:4)5’ (cid:3)(cid:4)88 #(cid:17)(cid:11)(cid:7)(cid:13)(cid:23)(cid:16)(cid:16)(cid:2) "(cid:3) 8(cid:4)88 8(cid:4)8(cid:3) 8(cid:4)8’ )(cid:23)(cid:7)(cid:17)(cid:11)(cid:24)(cid:17)(cid:2)+(cid:26)(cid:6)(cid:24)(cid:28)(cid:7)(cid:14)(cid:9)(cid:9) "(cid:31) 8(cid:4)(cid:27)8(cid:2),%- 3(cid:8)(cid:14)(cid:18)(cid:11)(cid:12)(cid:12)(cid:2)1(cid:14)(cid:7)(cid:29)(cid:17)(cid:26) ! ’(cid:4)88(cid:2)(#) 3(cid:8)(cid:14)(cid:18)(cid:11)(cid:12)(cid:12)(cid:2)9(cid:6)(cid:13)(cid:17)(cid:26) % :(cid:4)88(cid:2)(#) %(cid:15)(cid:30)(cid:23)(cid:9)(cid:14)(cid:13)(cid:2)(cid:5)(cid:11)(cid:13)(cid:2)1(cid:14)(cid:7)(cid:29)(cid:17)(cid:26) !(cid:27) (cid:31)(cid:4);8 (cid:4)88 (cid:4)(cid:3)8 %(cid:15)(cid:30)(cid:23)(cid:9)(cid:14)(cid:13)(cid:2)(cid:5)(cid:11)(cid:13)(cid:2)9(cid:6)(cid:13)(cid:17)(cid:26) %(cid:27) (cid:27)(cid:4)(cid:27)8 (cid:27)(cid:4)(cid:31)8 (cid:27)(cid:4) 8 )(cid:23)(cid:7)(cid:17)(cid:11)(cid:24)(cid:17)(cid:2)9(cid:6)(cid:13)(cid:17)(cid:26) (cid:22) 8(cid:4)(cid:31)’ 8(cid:4) 8 8(cid:4) 5 )(cid:23)(cid:7)(cid:17)(cid:11)(cid:24)(cid:17)(cid:2)1(cid:14)(cid:7)(cid:29)(cid:17)(cid:26) 1 8(cid:4)’8 8(cid:4):8 8(cid:4)6’ )(cid:23)(cid:7)(cid:17)(cid:11)(cid:24)(cid:17)<(cid:17)(cid:23)<%(cid:15)(cid:30)(cid:23)(cid:9)(cid:14)(cid:13)(cid:2)(cid:5)(cid:11)(cid:13) = 8(cid:4)(cid:27)8 > > (cid:19)(cid:20)(cid:12)(cid:5)(cid:11)$ (cid:3)(cid:4) (cid:5)(cid:6)(cid:7)(cid:2)(cid:3)(cid:2)(cid:8)(cid:6)(cid:9)(cid:10)(cid:11)(cid:12)(cid:2)(cid:6)(cid:7)(cid:13)(cid:14)(cid:15)(cid:2)(cid:16)(cid:14)(cid:11)(cid:17)(cid:10)(cid:18)(cid:14)(cid:2)(cid:19)(cid:11)(cid:20)(cid:2)(cid:8)(cid:11)(cid:18)(cid:20)(cid:21)(cid:2)(cid:22)(cid:10)(cid:17)(cid:2)(cid:19)(cid:10)(cid:9)(cid:17)(cid:2)(cid:22)(cid:14)(cid:2)(cid:12)(cid:23)(cid:24)(cid:11)(cid:17)(cid:14)(cid:13)(cid:2)(cid:25)(cid:6)(cid:17)(cid:26)(cid:6)(cid:7)(cid:2)(cid:17)(cid:26)(cid:14)(cid:2)(cid:26)(cid:11)(cid:17)(cid:24)(cid:26)(cid:14)(cid:13)(cid:2)(cid:11)(cid:18)(cid:14)(cid:11)(cid:4) (cid:27)(cid:4) (cid:5)(cid:11)(cid:24)(cid:28)(cid:11)(cid:29)(cid:14)(cid:2)(cid:19)(cid:11)(cid:20)(cid:2)(cid:26)(cid:11)(cid:8)(cid:14)(cid:2)(cid:23)(cid:7)(cid:14)(cid:2)(cid:23)(cid:18)(cid:2)(cid:19)(cid:23)(cid:18)(cid:14)(cid:2)(cid:14)(cid:15)(cid:30)(cid:23)(cid:9)(cid:14)(cid:13)(cid:2)(cid:17)(cid:6)(cid:14)(cid:2)(cid:22)(cid:11)(cid:18)(cid:9)(cid:2)(cid:11)(cid:17)(cid:2)(cid:14)(cid:7)(cid:13)(cid:9)(cid:4) (cid:31)(cid:4) (cid:5)(cid:11)(cid:24)(cid:28)(cid:11)(cid:29)(cid:14)(cid:2)(cid:6)(cid:9)(cid:2)(cid:9)(cid:11)(cid:25)(cid:2)(cid:9)(cid:6)(cid:7)(cid:29)(cid:10)(cid:12)(cid:11)(cid:17)(cid:14)(cid:13)(cid:4) (cid:4) !(cid:6)(cid:19)(cid:14)(cid:7)(cid:9)(cid:6)(cid:23)(cid:7)(cid:6)(cid:7)(cid:29)(cid:2)(cid:11)(cid:7)(cid:13)(cid:2)(cid:17)(cid:23)(cid:12)(cid:14)(cid:18)(cid:11)(cid:7)(cid:24)(cid:6)(cid:7)(cid:29)(cid:2)(cid:30)(cid:14)(cid:18)(cid:2)"#$%(cid:2)&(cid:3) (cid:4)’$(cid:4) (#)* ((cid:11)(cid:9)(cid:6)(cid:24)(cid:2)!(cid:6)(cid:19)(cid:14)(cid:7)(cid:9)(cid:6)(cid:23)(cid:7)(cid:4)(cid:2)+(cid:26)(cid:14)(cid:23)(cid:18)(cid:14)(cid:17)(cid:6)(cid:24)(cid:11)(cid:12)(cid:12)(cid:20)(cid:2)(cid:14)(cid:15)(cid:11)(cid:24)(cid:17)(cid:2)(cid:8)(cid:11)(cid:12)(cid:10)(cid:14)(cid:2)(cid:9)(cid:26)(cid:23)(cid:25)(cid:7)(cid:2)(cid:25)(cid:6)(cid:17)(cid:26)(cid:23)(cid:10)(cid:17)(cid:2)(cid:17)(cid:23)(cid:12)(cid:14)(cid:18)(cid:11)(cid:7)(cid:24)(cid:14)(cid:9)(cid:4) ,%-* ,(cid:14)(cid:16)(cid:14)(cid:18)(cid:14)(cid:7)(cid:24)(cid:14)(cid:2)!(cid:6)(cid:19)(cid:14)(cid:7)(cid:9)(cid:6)(cid:23)(cid:7)(cid:21)(cid:2)(cid:10)(cid:9)(cid:10)(cid:11)(cid:12)(cid:12)(cid:20)(cid:2)(cid:25)(cid:6)(cid:17)(cid:26)(cid:23)(cid:10)(cid:17)(cid:2)(cid:17)(cid:23)(cid:12)(cid:14)(cid:18)(cid:11)(cid:7)(cid:24)(cid:14)(cid:21)(cid:2)(cid:16)(cid:23)(cid:18)(cid:2)(cid:6)(cid:7)(cid:16)(cid:23)(cid:18)(cid:19)(cid:11)(cid:17)(cid:6)(cid:23)(cid:7)(cid:2)(cid:30)(cid:10)(cid:18)(cid:30)(cid:23)(cid:9)(cid:14)(cid:9)(cid:2)(cid:23)(cid:7)(cid:12)(cid:20)(cid:4) $(cid:6)(cid:24)(cid:18)(cid:23)(cid:24)(cid:26)(cid:6)(cid:30)+(cid:14)(cid:24)(cid:26)(cid:7)(cid:23)(cid:12)(cid:23)(cid:29)(cid:20)!(cid:18)(cid:11)(cid:25)(cid:6)(cid:7)(cid:29))8 <(cid:3)(cid:27)(cid:27)(  2003-2019 Microchip Technology Inc. DS20001822H-page 25

25AA256/25LC256 (cid:19)(cid:20)(cid:12)(cid:5)$ -(cid:23)(cid:18)(cid:2)(cid:17)(cid:26)(cid:14)(cid:2)(cid:19)(cid:23)(cid:9)(cid:17)(cid:2)(cid:24)(cid:10)(cid:18)(cid:18)(cid:14)(cid:7)(cid:17)(cid:2)(cid:30)(cid:11)(cid:24)(cid:28)(cid:11)(cid:29)(cid:14)(cid:2)(cid:13)(cid:18)(cid:11)(cid:25)(cid:6)(cid:7)(cid:29)(cid:9)(cid:21)(cid:2)(cid:30)(cid:12)(cid:14)(cid:11)(cid:9)(cid:14)(cid:2)(cid:9)(cid:14)(cid:14)(cid:2)(cid:17)(cid:26)(cid:14)(cid:2)$(cid:6)(cid:24)(cid:18)(cid:23)(cid:24)(cid:26)(cid:6)(cid:30)(cid:2)(cid:5)(cid:11)(cid:24)(cid:28)(cid:11)(cid:29)(cid:6)(cid:7)(cid:29)(cid:2)#(cid:30)(cid:14)(cid:24)(cid:6)(cid:16)(cid:6)(cid:24)(cid:11)(cid:17)(cid:6)(cid:23)(cid:7)(cid:2)(cid:12)(cid:23)(cid:24)(cid:11)(cid:17)(cid:14)(cid:13)(cid:2)(cid:11)(cid:17)(cid:2) (cid:26)(cid:17)(cid:17)(cid:30)*..(cid:25)(cid:25)(cid:25)(cid:4)(cid:19)(cid:6)(cid:24)(cid:18)(cid:23)(cid:24)(cid:26)(cid:6)(cid:30)(cid:4)(cid:24)(cid:23)(cid:19).(cid:30)(cid:11)(cid:24)(cid:28)(cid:11)(cid:29)(cid:6)(cid:7)(cid:29)  2003-2019 Microchip Technology Inc. DS20001822H-page 26

25AA256/25LC256 APPENDIX A: REVISION HISTORY Revision H (08/2019) Revise Product ID System, packages and notes; Clarified Extended E-Temp description; Update RoHS compliant description; Update PDIP package drawing. Revision G (01/2013) Revise Automotive E Temp; Revise Table 1-2, Param. No. 21. Revision F (05/07) Update Pb-free; Replace Package Drawings (Rev. AP); Update Product ID section. Revision E (08/05) Remove Preliminary status. Revise Table 1-1, Params. D011 and D012. Revision D (06/05) Update package information Revision C (11/03) Corrections to Section 1.0, Electrical Characteristics.  2003-2019 Microchip Technology Inc. DS20001822H-page 27

25AA256/25LC256 THE MICROCHIP WEBSITE CUSTOMER SUPPORT Microchip provides online support via our website at Users of Microchip products can receive assistance www.microchip.com. This website is used as a means through several channels: to make files and information easily available to • Distributor or Representative customers. Accessible by using your favorite Internet • Local Sales Office browser, the website contains the following information: • Field Application Engineer (FAE) • Product Support – Data sheets and errata, • Technical Support application notes and sample programs, design resources, user’s guides and hardware support Customers should contact their distributor, documents, latest software releases and archived representative or Field Application Engineer (FAE) for software support. Local sales offices are also available to help customers. A listing of sales offices and locations is • General Technical Support – Frequently Asked included in the back of this document. Questions (FAQ), technical support requests, online discussion groups, Microchip consultant Technical support is available through the website program member listing at: http://microchip.com/support • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip website at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions.  2003-2019 Microchip Technology Inc. DS20001822H-page 28

25AA256/25LC256 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X – X /XX Examples: Device Tape & Reel Temp Range Package a) 25AA256T-I/SN = 256 kbit, 1.8V Serial EEPROM, Industrial temp., Tape & Reel, SOIC package b) 25AA256T-I/ST = 256 kbit, 1.8V Serial EEPROM, Industrial temp., Tape & Reel, Device: 25AA256 256k-bit, 1.8V, 64-Byte Page, SPI Serial EEPROM TSSOP package 25LC256 256k-bit, 2.5V, 64-Byte Page, SPI Serial EEPROM 25AA256X 256k-bit, 1.8V, 64-Byte Page, SPI Serial EEPROM, c) 25LC256-I/P = 256 kbit, 2.5V Serial EEPROM, rotated pinout (ST only) Industrial temp., P-DIP package 25LC256X 256k-bit, 2.5V, 64-Byte Page, SPI Serial EEPROM, d) 25LC256T-E/ST = 256 kbit, 2.5V Serial rotated pinout (ST only) EEPROM, Extended temp., Tape & Reel, TSSOP package Tape & Reel: Blank = Standard packaging (tube) e) 25LC256XT-I/ST = 256 kbit, 2.5V Serial T = Tape & Reel EEPROM, Industrial temp., Tape and Reel, Temperature I = -40C to+85C (Industrial) Rotated TSSOP package Range: E = -40C to+125C (Extended) f) 25AA256T-E/SM = 256 kbit, 1.8V Serial EEPROM, Extended temp., Tape and Reel, SOIJ package Package: P = Plastic DIP (300 mil body), 8-lead SM = Plastic SOIJ (5.28 mm body), 8-lead SN = Plastic SOIC (3.90 mm body), 8-lead Note 1: Tape and Reel identifier only appears in ST = TSSOP, 8-lead the catalog part number description. This MF = Micro Lead Frame (6 x 5 mm body), 8-lead identifier is used for ordering purposes only and is not printed on the device package. Check with your Microchip Sales Office for package availability with the Tape and Reel option. 2: Contact Microchip for Automotive grade ordering part numbers.  2003-2019 Microchip Technology Inc. DS20001822H-page 29

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, Adaptec, and may be superseded by updates. It is your responsibility to AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, chipKIT, ensure that your application meets with your specifications. chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck, MICROCHIP MAKES NO REPRESENTATIONS OR LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi, WARRANTIES OF ANY KIND WHETHER EXPRESS OR Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer, IMPLIED, WRITTEN OR ORAL, STATUTORY OR PackeTime, PIC, picoPower, PICSTART, PIC32 logo, PolarFire, OTHERWISE, RELATED TO THE INFORMATION, Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST, INCLUDING BUT NOT LIMITED TO ITS CONDITION, SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon, TempTrackr, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA QUALITY, PERFORMANCE, MERCHANTABILITY OR are registered trademarks of Microchip Technology Incorporated in FITNESS FOR PURPOSE. Microchip disclaims all liability the U.S.A. and other countries. arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at APT, ClockWorks, The Embedded Control Solutions Company, the buyer’s risk, and the buyer agrees to defend, indemnify and EtherSynch, FlashTec, Hyper Speed Control, HyperLight Load, IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision hold harmless Microchip from any and all damages, claims, Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-Wire, suits, or expenses resulting from such use. No licenses are SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub, conveyed, implicitly or otherwise, under any Microchip TimePictra, TimeProvider, Vite, WinPath, and ZL are registered intellectual property rights unless otherwise stated. trademarks of Microchip Technology Incorporated in the U.S.A. Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BlueSky, BodyCom, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, memBrain, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. The Adaptec logo, Frequency on Demand, Silicon Storage Technology, and Symmcom are registered trademarks of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2003-2019, Microchip Technology Incorporated, All Rights Reserved. For information regarding Microchip’s Quality Management Systems, please visit www.microchip.com/quality. ISBN: 978-1-5224-4954-6  2003-2019 Microchip Technology Inc. DS20001822H-page 30

Worldwide Sales and Service AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office Australia - Sydney India - Bangalore Austria - Wels 2355 West Chandler Blvd. Tel: 61-2-9868-6733 Tel: 91-80-3090-4444 Tel: 43-7242-2244-39 Chandler, AZ 85224-6199 China - Beijing India - New Delhi Fax: 43-7242-2244-393 Tel: 480-792-7200 Tel: 86-10-8569-7000 Tel: 91-11-4160-8631 Denmark - Copenhagen Fax: 480-792-7277 Tel: 45-4450-2828 China - Chengdu India - Pune Technical Support: Tel: 86-28-8665-5511 Tel: 91-20-4121-0141 Fax: 45-4485-2829 http://www.microchip.com/ support China - Chongqing Japan - Osaka Finland - Espoo Tel: 86-23-8980-9588 Tel: 81-6-6152-7160 Tel: 358-9-4520-820 Web Address: www.microchip.com China - Dongguan Japan - Tokyo France - Paris Tel: 86-769-8702-9880 Tel: 81-3-6880- 3770 Tel: 33-1-69-53-63-20 Atlanta Fax: 33-1-69-30-90-79 Duluth, GA China - Guangzhou Korea - Daegu Tel: 678-957-9614 Tel: 86-20-8755-8029 Tel: 82-53-744-4301 Germany - Garching Tel: 49-8931-9700 Fax: 678-957-1455 China - Hangzhou Korea - Seoul Austin, TX Tel: 86-571-8792-8115 Tel: 82-2-554-7200 Germany - Haan Tel: 49-2129-3766400 Tel: 512-257-3370 China - Hong Kong SAR Malaysia - Kuala Lumpur Boston Tel: 852-2943-5100 Tel: 60-3-7651-7906 Germany - Heilbronn Tel: 49-7131-72400 Westborough, MA China - Nanjing Malaysia - Penang Tel: 774-760-0087 Tel: 86-25-8473-2460 Tel: 60-4-227-8870 Germany - Karlsruhe Fax: 774-760-0088 Tel: 49-721-625370 China - Qingdao Philippines - Manila Chicago Tel: 86-532-8502-7355 Tel: 63-2-634-9065 Germany - Munich Itasca, IL Tel: 49-89-627-144-0 China - Shanghai Singapore Tel: 630-285-0071 Tel: 86-21-3326-8000 Tel: 65-6334-8870 Fax: 49-89-627-144-44 Fax: 630-285-0075 Germany - Rosenheim China - Shenyang Taiwan - Hsin Chu Dallas Tel: 86-24-2334-2829 Tel: 886-3-577-8366 Tel: 49-8031-354-560 Addison, TX Israel - Ra’anana China - Shenzhen Taiwan - Kaohsiung Tel: 972-818-7423 Tel: 972-9-744-7705 Tel: 86-755-8864-2200 Tel: 886-7-213-7830 Fax: 972-818-2924 Italy - Milan China - Suzhou Taiwan - Taipei Detroit Tel: 39-0331-742611 Tel: 86-186-6233-1526 Tel: 886-2-2508-8600 Novi, MI Fax: 39-0331-466781 Tel: 248-848-4000 China - Wuhan Thailand - Bangkok Italy - Padova Tel: 86-27-5980-5300 Tel: 66-2-694-1351 Houston, TX Tel: 39-049-7625286 Tel: 281-894-5983 China - Xian Vietnam - Ho Chi Minh Netherlands - Drunen Tel: 86-29-8833-7252 Tel: 84-28-5448-2100 Indianapolis Tel: 31-416-690399 Noblesville, IN China - Xiamen Fax: 31-416-690340 Tel: 86-592-2388138 Tel: 317-773-8323 Norway - Trondheim Fax: 317-773-5453 China - Zhuhai Tel: 47-7288-4388 Tel: 317-536-2380 Tel: 86-756-3210040 Poland - Warsaw Los Angeles Tel: 48-22-3325737 Mission Viejo, CA Romania - Bucharest Tel: 949-462-9523 Tel: 40-21-407-87-50 Fax: 949-462-9608 Tel: 951-273-7800 Spain - Madrid Tel: 34-91-708-08-90 Raleigh, NC Fax: 34-91-708-08-91 Tel: 919-844-7510 Sweden - Gothenberg New York, NY Tel: 46-31-704-60-40 Tel: 631-435-6000 Sweden - Stockholm San Jose, CA Tel: 46-8-5090-4654 Tel: 408-735-9110 Tel: 408-436-4270 UK - Wokingham Tel: 44-118-921-5800 Canada - Toronto Fax: 44-118-921-5820 Tel: 905-695-1980 Fax: 905-695-2078  2003-2019 Microchip Technology Inc. DS20001822H-page 31 05/14/19