25LC080C/25LC080D/25LC160C/ 25LC160D/25LC320A/25LC640A/ 25LC128/25LC256 8K-256K SPI Serial EEPROM High Temp Family Data Sheet Features Communication to the device can be paused via the hold pin (HOLD). While the device is paused, • Maximum Clock: 5 MHz transitions on its inputs will be ignored, with the • Low-Power CMOS Technology: exception of Chip Select, allowing the host to service - Write current: 5 mA at 5.5V (maximum) higher priority interrupts. - Read current: 5 mA at 5.5V, 5 MHz Note1: 25LCXXX is used in this document as a - Standby current: 10 μA at 5.5V generic part number for the 25LC080C/ • 1,024 x 8 through 32,768 x 8-bit Organization 25LC080D/25LC160C/25LC160D/ 25LC320A/25LC640A/25LC128/ • Byte and Page-Level Write Operations 25LC256 devices. • Self-Timed Erase and Write Cycles (6 ms maximum) Packages • Block Write Protection: - Protect none, 1/4, 1/2 or all of array • 8-Lead SOIC • Built-in Write Protection: - Power-on/off data protection circuitry Package Types (not to scale) - Write enable latch - Write-protect pin 8-Lead SOIC • Sequential Read (Top View) • High Reliability: - Endurance: >1,000,000 erase/write cycles CS 1 8 VCC - Data retention: >200 years SO 2 7 HOLD - ESD protection: >4000V WP 3 6 SCK • Temperature Range Supported: VSS 4 5 SI - Extended (H): -40°C to +150°C • RoHS Compliant • Automotive AECQ-100 Qualified Pin Function Table Description Name Function Microchip Technology Inc. 25LCXXX(1) devices are CS Chip Select Input Mid-density 8- through 256-Kbit Serial Electrically SO Serial Data Output Erasable PROMs (EEPROM). The devices are organized in blocks of x8-bit memory and support the WP Write-Protect Serial Peripheral Interface (SPI) compatible serial bus VSS Ground architecture. Byte-level and page-level functions are supported. The bus signals required are a clock input SI Serial Data Input (SCK) plus separate data in (SI) and data out (SO) SCK Serial Clock Input lines. Access to the device is controlled through a Chip Select (CS) input. HOLD Hold Input VCC Supply Voltage  2009-2018 Microchip Technology Inc. DS20002131D-page 1

25LC080C/25LC080D/25LC160C/25LC160D/25LC320A/25LC640A/ 25LC128/25LC256 DEVICE SELECTION TABLE Density Max. Speed Page Size Temp. Part Number Organization VCC Range Package (bits) (MHz) (Bytes) Range 25LC080C 8K 1,024 x 8 2.5V-5.5V 5 16 H SN 25LC080D 8K 1,024 x 8 2.5V-5.5V 5 32 H SN 25LC160C 16K 2,048 x 8 2.5V-5.5V 5 16 H SN 25LC160D 16K 2,048 x 8 2.5V-5.5V 5 32 H SN 25LC320A 32K 4,096 x 8 2.5V-5.5V 5 32 H SN 25LC640A 64K 8,192 x 8 2.5V-5.5V 5 32 H SN 25LC128 128K 16,384 x 8 2.5V-5.5V 5 64 H SN 25LC256 256K 32,768 x 8 2.5V-5.5V 5 64 H SN  2009-2018 Microchip Technology Inc. DS20002131D-page 2

25LC080C/25LC080D/25LC160C/25LC160D/25LC320A/25LC640A/ 25LC128/25LC256 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings(†) VCC.............................................................................................................................................................................6.5V All inputs and outputs w.r.t. VSS.........................................................................................................-0.6V to VCC +1.0V Storage temperature...............................................................................................................................-65°C to +155°C Ambient temperature under bias.........................................................................................................-40°C to +150°C(1) ESD protection on all pins..........................................................................................................................................4 kV Note1: AEC-Q100 reliability testing for devices intended to operate at +150°C is 1,000 hours. Any design in which the total operating time between +125°C and +150°C will be greater than 1,000 hours is not warranted without prior written approval from Microchip Technology Inc. † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an extended period of time may affect device reliability. TABLE 1-1: DC CHARACTERISTICS Electrical Characteristics: DC CHARACTERISTICS Extended (H): TA = -40°C to +150°C VCC = 2.5V to 5.5V Param. Symbol Characteristic Min. Max. Units Test Conditions No. D001 VIH1 High-Level Input 0.7 VCC VCC + 1 V Voltage D002 VIL1 Low-Level Input -0.3 0.3VCC V VCC≥2.7V D003 VIL2 Voltage -0.3 0.2VCC V VCC < 2.7V D004 VOL1 Low-Level Output — 0.4 V IOL = 2.1 mA D005 VOL2 Voltage — 0.2 V IOL = 1.0 mA D006 VOH High-Level Output VCC – 0.5 — V IOH = -400 μA Voltage D007 ILI Input Leakage Current — ±2 μA CS = VCC, VIN = VSS OR VCC D008 ILO Output Leakage Current — ±2 μA CS = VCC, VOUT = VSS OR VCC D009 CINT Internal Capacitance — 7 pF TA = 25°C, CLK = 1.0 MHz, (all inputs and outputs) VCC = 5.0V (Note 1) D010 ICC Operating Current — 5 mA VCC = 5.5V; FCLK = 5.0 MHz; Read SO = Open — 2.5 mA VCC = 2.5V; FCLK = 3.0 MHz; SO = Open D011 ICC Operating Current — 5 mA VCC = 5.5V Write — 3 mA VCC = 2.5V D012 ICCS Standby Current — 10 μA CS = VCC = 5.5V, Inputs tied to VCC or VSS, +150°C Note1: This parameter is periodically sampled and not 100% tested.  2009-2018 Microchip Technology Inc. DS20002131D-page 3

25LC080C/25LC080D/25LC160C/25LC160D/25LC320A/25LC640A/ 25LC128/25LC256 TABLE 1-2: AC CHARACTERISTICS Electrical Characteristics: AC CHARACTERISTICS Extended (H): TA = -40°C to +150°C VCC = 2.5V to 5.5V Param. Symbol Characteristic Min. Max. Units Test Conditions No. 1 FCLK Clock Frequency — 5 MHz 4.5V ≤ Vcc ≤ 5.5V — 3 MHz 2.5V ≤ Vcc < 4.5V 2 TCSS CS Setup Time 100 — ns 4.5V ≤Vcc ≤ 5.5V 150 — ns 2.5V ≤Vcc < 4.5V 3 TCSH CS Hold Time 200 — ns 4.5V ≤ Vcc ≤ 5.5V 250 — ns 2.5V ≤ Vcc < 4.5V 4 TCSD CS Disable Time 50 — ns — 5 Tsu Data Setup Time 20 — ns 4.5V ≤ Vcc ≤ 5.5V 30 — ns 2.5V ≤ Vcc < 4.5V 6 THD Data Hold Time 40 — ns 4.5V ≤ Vcc ≤ 5.5V 50 — ns 2.5V ≤ Vcc < 4.5V 7 TR CLK Rise Time — 2 μs Note 1 8 TF CLK Fall Time — 2 μs Note 1 9 THI Clock High Time 100 — ns 4.5V ≤ Vcc ≤ 5.5V 150 — ns 2.5V ≤ Vcc < 4.5V 10 TLO Clock Low Time 100 — ns 4.5V ≤ Vcc ≤ 5.5V 150 — ns 2.5V ≤ Vcc < 4.5V 11 TCLD Clock Delay Time 50 — ns 12 TCLE Clock Enable Time 50 — ns 13 TV Output Valid from Clock — 100 ns 4.5V ≤ Vcc ≤ 5.5V Low — 160 ns 2.5V ≤ Vcc < 4.5V 14 THO Output Hold Time 0 — ns Note 1 15 TDIS Output Disable Time — 80 ns 4.5V ≤ Vcc ≤ 5.5V (Note 1) — 160 ns 2.5V ≤ Vcc < 4.5V (Note 1) 16 THS HOLD Setup Time 40 — ns 4.5V ≤ Vcc ≤ 5.5V 80 — ns 2.5V ≤ Vcc < 4.5V 17 THH HOLD Hold Time 40 — ns 4.5V ≤ Vcc ≤ 5.5V 80 — ns 2.5V ≤ Vcc < 4.5V 18 THZ HOLD Low to Output — 60 ns 4.5V ≤ Vcc ≤ 5.5V (Note 1) High Z — 160 ns 2.5V ≤ Vcc < 4.5V (Note 1) 19 THV HOLD High to Output — 60 ns 4.5V ≤ Vcc ≤ 5.5V Valid — 160 ns 2.5V ≤ Vcc < 4.5V 20 TWC Internal Write Cycle Time — 6 ms Note 2 21 Endurance 1,000,000 — E/W Page mode, 25°C, VCC = 5.5V (Note 3) Cycles Note1: This parameter is periodically sampled and not 100% tested. 2: TWC begins on the rising edge of CS after a valid write sequence and ends when the internal write cycle is complete. 3: This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total Endurance™ Model which can be obtained from our website: www.microchip.com.  2009-2018 Microchip Technology Inc. DS20002131D-page 4

25LC080C/25LC080D/25LC160C/25LC160D/25LC320A/25LC640A/ 25LC128/25LC256 TABLE 1-3: AC Waveform VLO = 0.2V VH I = VCC – 0.2V Note 1 VH I = 4.0V Note 2 CL = 50 pF Timing Measurement Reference Level Input 0.5 VCC Output 0.5 VCC Note1: For VCC ≤ 4.0V 2: For VCC > 4.0V FIGURE 1-1: HOLD TIMING CS 17 17 16 16 SCK 18 19 High-Impedance SO n + 2 n + 1 n n n - 1 Don’t Care 5 SI n + 2 n + 1 n n n - 1 HOLD FIGURE 1-2: SERIAL INPUT TIMING 4 CS 12 2 11 7 Mode 1,1 8 3 SCK Mode 0,0 5 6 SI MSB in LSB in High-Impedance SO  2009-2018 Microchip Technology Inc. DS20002131D-page 5

25LC080C/25LC080D/25LC160C/25LC160D/25LC320A/25LC640A/ 25LC128/25LC256 FIGURE 1-3: SERIAL OUTPUT TIMING CS 9 10 3 Mode 1,1 SCK Mode 0,0 13 14 15 SO MSB out LSB out Don’t Care SI  2009-2018 Microchip Technology Inc. DS20002131D-page 6

25LC080C/25LC080D/25LC160C/25LC160D/25LC320A/25LC640A/ 25LC128/25LC256 2.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table 2-1. The WP pin function is blocked when the WPEN bit in the STATUS register is low. This allows the user to TABLE 2-1: PIN FUNCTION TABLE install the 25LCXXX in a system with WP pin grounded Name Pin Number Function and still be able to write to the STATUS register. The WP pin functions will be enabled when the WPEN bit is CS 1 Chip Select Input set high. SO 2 Serial Data Output 2.4 Serial Input (SI) WP 3 Write-Protect Pin The SI pin is used to transfer data into the device. It VSS 4 Ground receives instructions, addresses and data. Data is SI 5 Serial Data Input latched on the rising edge of the serial clock. SCK 6 Serial Clock Input 2.5 Serial Clock (SCK) HOLD 7 Hold Input VCC 8 Supply Voltage The SCK is used to synchronize the communication between a master and the 25LCXXX. Instructions, 2.1 Chip Select (CS) addresses or data present on the SI pin are latched on the rising edge of the clock input, while data on the SO A low level on this pin selects the device. A high level pin is updated after the falling edge of the clock input. deselects the device and forces it into Standby mode. However, a programming cycle which is already 2.6 Hold (HOLD) initiated or in progress will be completed, regardless of the CS input signal. If CS is brought high during a The HOLD pin is used to suspend transmission to the program cycle, the device will go into Standby mode as 25LCXXX while in the middle of a serial sequence soon as the programming cycle is complete. When the without having to retransmit the entire sequence device is deselected, SO goes to the high-impedance again. It must be held high any time this function is not state, allowing multiple parts to share the same SPI being used. Once the device is selected and a serial bus. A low-to-high transition on CS after a valid write sequence is underway, the HOLD pin may be pulled sequence initiates an internal write cycle. After power- low to pause further serial communication without up, a low level on CS is required prior to any sequence resetting the serial sequence. The HOLD pin must be being initiated. brought low while SCK is low, otherwise the HOLD function will not be invoked until the next SCK high-to- 2.2 Serial Output (SO) low transition. The 25LCXXX must remain selected during this sequence. The SI, SCK and SO pins are in The SO pin is used to transfer data out of the a high-impedance state during the time the device is 25LCXXX. During a read cycle, data is shifted out on paused and transitions on these pins will be ignored. this pin after the falling edge of the serial clock. To resume serial communication, HOLD must be brought high while the SCK pin is low, otherwise serial 2.3 Write-Protect (WP) communication will not resume. Lowering the HOLD This pin is used in conjunction with the WPEN bit in the line at any time will tri-state the SO line. STATUS register to prohibit writes to the nonvolatile bits in the STATUS register. When WP is low and WPEN is high, writing to the nonvolatile bits in the STATUS register is disabled. All other operations function normally. When WP is high, all functions, including writes to the nonvolatile bits in the STATUS register operate normally. If the WPEN bit is set, WP low during a STATUS register write sequence will dis- able writing to the STATUS register. If an internal write cycle has already begun, WP going low will have no effect on the write.  2009-2018 Microchip Technology Inc. DS20002131D-page 7

25LC080C/25LC080D/25LC160C/25LC160D/25LC320A/25LC640A/ 25LC128/25LC256 3.0 FUNCTIONAL DESCRIPTION 3.1 Principles of Operation Block Diagram The 25LCXXX are Mid-Density Serial EEPROMs STATUS HV Generator designed to interface directly with the Serial Peripheral Register Interface (SPI) port of many of today’s popular microcontroller families, including Microchip’s PIC® microcontrollers. It may also interface with microcontrollers that do not have a built-in SPI port by using discrete I/O lines programmed properly in I/O Control Memory X EEAPrrRaOyM firmware to match the SPI protocol. Logic Control Logic Dec The 25LCXXX contains an 8-bit instruction register. The device is accessed via the SI pin, with data being Page Latches clocked in on the rising edge of SCK. The CS pin must be low and the HOLD pin must be high for the entire operation. SI Table 3-1 contains a list of the possible instruction SO Y Decoder bytes and format for device operation. All instructions, CS addresses, and data are transferred Most Significant SCK bit (MSb) first, Least Significant bit (LSb) last. Sense Amp. HOLD R/W Control Data (SI) is sampled on the first rising edge of SCK WP after CS goes low. If the clock line is shared with other VCC VSS peripheral devices on the SPI bus, the user can assert the HOLD input and place the 25LCXXX in ‘HOLD’ mode. After releasing the HOLD pin, operation will resume from the point when the HOLD was asserted. TABLE 3-1: INSTRUCTION SET Instruction Name Instruction Format Description READ 0000 0011 Read data from memory array beginning at selected address WRITE 0000 0010 Write data to memory array beginning at selected address WRDI 0000 0100 Reset the write enable latch (disable write operations) WREN 0000 0110 Set the write enable latch (enable write operations) RDSR 0000 0101 Read STATUS register WRSR 0000 0001 Write STATUS register  2009-2018 Microchip Technology Inc. DS20002131D-page 8

25LC080C/25LC080D/25LC160C/25LC160D/25LC320A/25LC640A/ 25LC128/25LC256 3.2 Read Sequence Once the write enable latch is set, the user may proceed by setting the CS low, issuing a WRITE instruc- The device is selected by pulling CS low. The 8-bit tion, followed by the 16-bit address, and then the data READ instruction is transmitted to the 25LCXXX to be written. Depending upon the density, a page of followed by the 16-bit address. After the correct READ data that ranges from 16 bytes to 64 bytes can be sent instruction and address are sent, the data stored in the to the device before a write cycle is necessary. The only memory at the selected address is shifted out on the restriction is that all of the bytes must reside in the SO pin. The data stored in the memory at the next same page. address can be read sequentially by continuing to provide clock pulses. The internal Address Pointer is Note: Page write operations are limited to automatically incremented to the next higher address writing bytes within a single physical page, after each byte of data is shifted out. When the highest regardless of the number of bytes address is reached, the address counter rolls over to actually being written. Physical page address 0000h allowing the read cycle to be continued boundaries start at addresses that are indefinitely. The read operation is terminated by raising integer multiples of the page buffer size the CS pin (Figure 3-1). (or ‘page size’) and, end at addresses that are integer multiples of page size – 1. If a 3.3 Write Sequence Page Write command attempts to write across a physical page boundary, the Prior to any attempt to write data to the 25LCXXX, the result is that the data wraps around to the write enable latch must be set by issuing the WREN beginning of the current page (overwriting instruction (Figure 3-4). This is done by setting CS low data previously stored there), instead of and then clocking out the proper instruction into the being written to the next page as might be 25LCXXX. After all eight bits of the instruction are expected. It is therefore necessary for the transmitted, the CS must be brought high to set the application software to prevent page write write enable latch. If the write operation is initiated operations that would attempt to cross a immediately after the WREN instruction without CS page boundary. being brought high, the data will not be written to the array because the write enable latch will not have been For the data to be actually written to the array, the CS properly set. must be brought high after the Least Significant bit (D0) of the nth data byte has been clocked in. If CS is brought high at any other time, the write operation will not be completed. Refer to Figure 3-2 and Figure 3-3 for more detailed illustrations on the byte write sequence and the page write sequence, respectively. While the write is in progress, the STATUS register may be read to check the status of the WPEN, WIP, WEL, BP1 and BP0 bits (Figure 3-6). A read attempt of a memory array location will not be possible during a write cycle. When the write cycle is completed, the write enable latch is reset. FIGURE 3-1: READ SEQUENCE CS 0 1 2 3 4 5 6 7 8 9 10 11 21 22 23 24 25 26 27 28 29 30 31 SCK Instruction 16-bit Address SI 0 0 0 0 0 0 1 1 15 14 13 12 2 1 0 Data Out High-Impedance SO 7 6 5 4 3 2 1 0  2009-2018 Microchip Technology Inc. DS20002131D-page 9

25LC080C/25LC080D/25LC160C/25LC160D/25LC320A/25LC640A/ 25LC128/25LC256 FIGURE 3-2: BYTE WRITE SEQUENCE CS Twc 0 1 2 3 4 5 6 7 8 9 10 11 21 22 23 24 25 26 27 28 29 30 31 SCK Instruction 16-bit Address Data Byte SI 0 0 0 0 0 0 1 0 15 14 13 12 2 1 0 7 6 5 4 3 2 1 0 High-Impedance SO FIGURE 3-3: PAGE WRITE SEQUENCE CS 0 1 2 3 4 5 6 7 8 9 10 11 21 22 23 24 25 26 27 28 29 30 31 SCK Instruction 16-bit Address Data Byte 1 SI 0 0 0 0 0 0 1 0 15 14 13 12 2 1 0 7 6 5 4 3 2 1 0 CS 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCK Data Byte 2 Data Byte 3 Data Byte n (16/32/64 max) SI 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0  2009-2018 Microchip Technology Inc. DS20002131D-page 10

25LC080C/25LC080D/25LC160C/25LC160D/25LC320A/25LC640A/ 25LC128/25LC256 3.4 Write Enable (WREN) and Write The following is a list of conditions under which the Disable (WRDI) write enable latch will be reset: • Power-up The 25LCXXX contains a write enable latch. See • WRDI instruction successfully executed Table 5-1 for the write-protect functionality matrix. This latch must be set before any write operation will be • WRSR instruction successfully executed completed internally. The WREN instruction will set the • WRITE instruction successfully executed latch, and the WRDI will reset the latch. FIGURE 3-4: WRITE ENABLE SEQUENCE (WREN) CS 0 1 2 3 4 5 6 7 SCK SI 0 0 0 0 0 1 1 0 High-Impedance SO FIGURE 3-5: WRITE DISABLE SEQUENCE (WRDI) CS 0 1 2 3 4 5 6 7 SCK SI 0 0 0 0 0 1 10 0 High-Impedance SO  2009-2018 Microchip Technology Inc. DS20002131D-page 11

25LC080C/25LC080D/25LC160C/25LC160D/25LC320A/25LC640A/ 25LC128/25LC256 3.5 Read STATUS Register Instruction The Write-In-Process (WIP) bit indicates whether the (RDSR) 25LCXXX is busy with a write operation. When set to a ‘1’, a write is in progress, when set to a ‘0’, no write is The Read STATUS Register instruction (RDSR) in progress. This bit is read-only. provides access to the STATUS register. The STATUS The Write Enable Latch (WEL) bit indicates the status register may be read at any time, even during a write of the write enable latch and is read-only. When set cycle. The STATUS register is formatted as seen in to a ‘1’, the latch allows writes to the array, when set Table 3-2. to a ‘0’, the latch prohibits writes to the array. The state TABLE 3-2: STATUS REGISTER of this bit can always be updated via the WREN or WRDI commands regardless of the state of write protection 7 6 5 4 3 2 1 0 on the STATUS register. These commands are shown W/R — — — W/R W/R R R in Figure 3-4 and Figure 3-5. WPEN X X X BP1 BP0 WEL WIP The Block Protection (BP0 and BP1) bits indicate W/R = writable/readable. R = read-only. which blocks are currently write-protected. These bits are set by the user issuing the WRSR instruction. These bits are nonvolatile, and are shown in Table 3-3. See Figure 3-6 for the RDSR timing sequence. FIGURE 3-6: READ STATUS REGISTER TIMING SEQUENCE (RDSR) CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCK Instruction SI 0 0 0 0 0 1 0 1 Data from STATUS Register High-Impedance SO 7 6 5 4 3 2 1 0  2009-2018 Microchip Technology Inc. DS20002131D-page 12

25LC080C/25LC080D/25LC160C/25LC160D/25LC320A/25LC640A/ 25LC128/25LC256 3.6 Write Status Register Instruction The Write-Protect Enable (WPEN) bit is a nonvolatile (WRSR) bit that is available as an enable bit for the WP pin. The Write-Protect (WP) pin and the Write-Protect Enable The Write STATUS Register instruction (WRSR) allows (WPEN) bit in the STATUS register control the the user to write to the nonvolatile bits in the STATUS programmable hardware write-protect feature. register as shown in Table 3-2. The user is able to Hardware write protection is enabled when WP pin is select one of four levels of protection for the array by low and the WPEN bit is high. Hardware write writing to the appropriate bits in the STATUS register. protection is disabled when either the WP pin is high or The array is divided up into four segments. The user the WPEN bit is low. When the chip is hardware write- has the ability to write-protect none, one, two or all four protected, only writes to nonvolatile bits in the STATUS of the segments of the array. The partitioning is register are disabled. See Table 5-1 for a matrix of controlled as shown in Table 3-3. functionality on the WPEN bit. See Figure 3-7 for the WRSR timing sequence. TABLE 3-3: ARRAY PROTECTION Array Addresses Array Addresses BP1 BP0 Write-Protected Unprotected 0 0 None All 0 1 Upper 1/4 Lower 3/4 1 0 Upper 1/2 Lower 1/2 1 1 All None TABLE 3-4: ARRAY PROTECTED ADDRESS LOCATIONS Density Upper 1/4 Upper 1/2 All 8K 300h-3FFh 200h-3FFh 000h-3FFh 16K 600h-7FFh 400h-7FFh 000h-7FFh 32K C00h-FFFh 800h-FFFh 000h-FFFh 64K 1800h-1FFFh 1000h-1FFFh 0000h-1FFFh 128K 3000h-3FFFh 2000h-3FFFh 0000h-3FFFh 256K 6000h-7FFFh 4000h-7FFFh 0000h-7FFFh FIGURE 3-7: WRITE STATUS REGISTER TIMING SEQUENCE (WRSR) CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCK Instruction Data to STATUS Register SI 0 0 0 0 0 0 0 1 7 6 5 4 3 2 1 0 High-Impedance SO Note: An internal write cycle (TWC) is initiated on the rising edge of CS after a valid write STATUS register sequence.  2009-2018 Microchip Technology Inc. DS20002131D-page 13

25LC080C/25LC080D/25LC160C/25LC160D/25LC320A/25LC640A/ 25LC128/25LC256 4.0 DATA PROTECTION 5.0 POWER-ON STATE The following protection has been implemented to The 25LCXXX powers on in the following state: prevent inadvertent writes to the array: • The device is in low-power Standby mode • The write enable latch is reset on power-up (CS = 1) • A write enable instruction must be issued to set • The write enable latch is reset the write enable latch • SO is in high-impedance state • After a byte write, page write or STATUS register • A high-to-low-level transition on CS is required to write, the write enable latch is reset enter active state • CS must be set high after the proper number of clock cycles to start an internal write cycle • Access to the array during an internal write cycle is ignored and programming is continued TABLE 5-1: WRITE-PROTECT FUNCTIONALITY MATRIX WEL WPEN WP Protected Blocks Unprotected Blocks STATUS Register (SR bit 1) (SR bit 7) (pin 3) 0 x x Protected Protected Protected 1 0 x Protected Writable Writable 1 1 0 (low) Protected Writable Protected 1 1 1 (high) Protected Writable Writable x = don’t care  2009-2018 Microchip Technology Inc. DS20002131D-page 14

25LC080C/25LC080D/25LC160C/25LC160D/25LC320A/25LC640A/ 25LC128/25LC256 6.0 PACKAGING INFORMATION 6.1 Package Marking Information 8-Lead SOIC Example XXXXXXXT 25LC32AH XXXXYYWW SN e 3 1837 NNN 13F 1st Line Marking Codes Part Number SOIC 25LC080C 25LC08CT 25LC080D 25LC08DT 25LC160C 25LC16CT 25LC160D 25LC16DT 25LC320A 25LC32AT 25LC640A 25L640AT 25LC128 25LC128T 25LC256 25LC256T Note: T = Temperature Grade (H). Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 JEDEC designator for Matte Tin (Sn) * This package is RoHS compliant. The JEDEC designator ( e 3 ) can be found on the outer packaging for this package. * Custom marking available. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2009-2018 Microchip Technology Inc. DS20002131D-page 15

25LC080C/25LC080D/25LC160C/25LC160D/25LC320A/25LC640A/ 25LC128/25LC256 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2X 0.10 C A–B D A D NOTE 5 N E 2 E1 2 E1 E NOTE 1 1 2 e NX b B 0.25 C A–B D NOTE 5 TOP VIEW 0.10 C C A A2 SEATING PLANE 8X 0.10 C A1 SIDE VIEW h R0.13 h R0.13 H 0.23 L SEE VIEW C (L1) VIEW A–A VIEW C Microchip Technology Drawing No. C04-057-SN Rev D Sheet 1 of 2  2009-2018 Microchip Technology Inc. DS20002131D-page 16

25LC080C/25LC080D/25LC160C/25LC160D/25LC320A/25LC640A/ 25LC128/25LC256 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Pins N 8 Pitch e 1.27 BSC Overall Height A - - 1.75 Molded Package Thickness A2 1.25 - - Standoff § A1 0.10 - 0.25 Overall Width E 6.00 BSC Molded Package Width E1 3.90 BSC Overall Length D 4.90 BSC Chamfer (Optional) h 0.25 - 0.50 Foot Length L 0.40 - 1.27 Footprint L1 1.04 REF Foot Angle 0° - 8° Lead Thickness c 0.17 - 0.25 Lead Width b 0.31 - 0.51 Mold Draft Angle Top 5° - 15° Mold Draft Angle Bottom 5° - 15° Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. 5. Datums A & B to be determined at Datum H. Microchip Technology Drawing No. C04-057-SN Rev D Sheet 2 of 2  2009-2018 Microchip Technology Inc. DS20002131D-page 17

25LC080C/25LC080D/25LC160C/25LC160D/25LC320A/25LC640A/ 25LC128/25LC256 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging SILK SCREEN C Y1 X1 E RECOMMENDED LAND PATTERN Units MILLIMETERS Dimension Limits MIN NOM MAX Contact Pitch E 1.27 BSC Contact Pad Spacing C 5.40 Contact Pad Width (X8) X1 0.60 Contact Pad Length (X8) Y1 1.55 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing C04-2057-SN Rev B  2009-2018 Microchip Technology Inc. DS20002131D-page 18

25LC080C/25LC080D/25LC160C/25LC160D/25LC320A/25LC640A/ 25LC128/25LC256 REVISION HISTORY Revision A (01/2009) Initial release of this document. Revision B (04/2009) Revised part number from 25XX to 25LCXXX; Added Note 1 to Electrical Characteristics. Revision C (06/2009) Revised Features: Endurance and Package; Revised Table 1-2, Para. 21. Revision D (09/2018) Removed Preliminary status; Minor typographical corrections.  2009-2018 Microchip Technology Inc. DS20002131D-page 19

25LC080C/25LC080D/25LC160C/25LC160D/25LC320A/25LC640A/ 25LC128/25LC256 THE MICROCHIP WEBSITE CUSTOMER SUPPORT Microchip provides online support via our website at Users of Microchip products can receive assistance www.microchip.com. This website is used as a means through several channels: to make files and information easily available to • Distributor or Representative customers. Accessible by using your favorite Internet • Local Sales Office browser, the website contains the following information: • Field Application Engineer (FAE) • Product Support – Data sheets and errata, appli- • Technical Support cation notes and sample programs, design resources, user’s guides and hardware support Customers should contact their distributor, representa- documents, latest software releases and archived tive or Field Application Engineer (FAE) for support. software Local sales offices are also available to help custom- • General Technical Support – Frequently Asked ers. A listing of sales offices and locations is included in Questions (FAQ), technical support requests, the back of this document. online discussion groups, Microchip consultant Technical support is available through the website program member listing at: http://microchip.com/support • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Micro- chip sales offices, distributors and factory repre- sentatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip website at www.microchip.com. Under “Support”, click on “Cus- tomer Change Notification” and follow the registra- tion instructions.  2009-2018 Microchip Technology Inc. DS20002131D-page 20

25LC080C/25LC080D/25LC160C/25LC160D/25LC320A/25LC640A/ 25LC128/25LC256 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. [X](1) -X /XX Examples: Device Tape and Reel Temperature Package a) 25LC080CT-H/SN = Tape and Reel, Extended Option Range Temp., 16-Byte Page, 2.5V-5.5V, SOIC package. Device: 25LC080C = 8-Kbit SPI Serial EEPROM b) 25LC080D-H/SN = Extended Temp., 32-Byte 25LC080D = 8-Kbit SPI Serial EEPROM Page, 2.5V-5.5V, SOIC 25LC160C = 16-Kbit SPI Serial EEPROM package. 25LC160D = 16-Kbit SPI Serial EEPROM c) 25LC160CT-H/SN = Tape and Reel, Extended 25LC320A = 32-Kbit SPI Serial EEPROM Temp. 16-Byte Page, 2.5V- 25LC640A = 64-Kbit SPI Serial EEPROM 5.5V, SOIC Package. 25LC128 = 128-Kbit SPI Serial EEPROM d) 25LC160D-H/SN = Extended Temp., 32-Byte 25LC256 = 256-Kbit SPI Serial EEPROM Page, 2.5V-5.5V, SOIC Package. e) 25LC320AT-H/SN = Tape and Reel, Extended Tape and Reel Blank = Standard packaging (tube or tray) Temp. 32-Byte Page, 2.5V- Option: T = Tape and Reel(1) 5.5V, SOIC Package. f) 25LC640A-H/SN = Extended Temp. 32-Byte Page, 2.5V-5.5V, SOIC Temperature H = -40C to +150C (Extended) Package. Range: g) 25LC128T-H/SN = Tape and Reel, Extended Temp. 64-Byte Page, 2.5V- 5.5V, SOIC Package. Package: SN = 8-Lead Plastic Small Outline – Narrow, 3.90 mm h) 25LC256-H/SN = Extended Temp. 64-Byte Body SOIC Page, 2.5V-5.5V, SOIC Package. Note 1: Tape and Reel identifier only appears in the catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. Check with your Microchip Sales Office for package availability with the Tape and Reel option. 2: Contact Microchip for Automotive grade ordering part numbers.  2009-2018 Microchip Technology Inc. DS20002131D-page 21

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, AnyRate, AVR, and may be superseded by updates. It is your responsibility to AVR logo, AVR Freaks, BitCloud, chipKIT, chipKIT logo, ensure that your application meets with your specifications. CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo, MICROCHIP MAKES NO REPRESENTATIONS OR JukeBlox, KeeLoq, Kleer, LANCheck, LINK MD, maXStylus, WARRANTIES OF ANY KIND WHETHER EXPRESS OR maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB, IMPLIED, WRITTEN OR ORAL, STATUTORY OR OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip OTHERWISE, RELATED TO THE INFORMATION, Designer, QTouch, SAM-BA, SpyNIC, SST, SST Logo, INCLUDING BUT NOT LIMITED TO ITS CONDITION, SuperFlash, tinyAVR, UNI/O, and XMEGA are registered QUALITY, PERFORMANCE, MERCHANTABILITY OR trademarks of Microchip Technology Incorporated in the U.S.A. FITNESS FOR PURPOSE. Microchip disclaims all liability and other countries. arising from this information and its use. Use of Microchip ClockWorks, The Embedded Control Solutions Company, devices in life support and/or safety applications is entirely at EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS, the buyer’s risk, and the buyer agrees to defend, indemnify and mTouch, Precision Edge, and Quiet-Wire are registered hold harmless Microchip from any and all damages, claims, trademarks of Microchip Technology Incorporated in the U.S.A. suits, or expenses resulting from such use. No licenses are Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any conveyed, implicitly or otherwise, under any Microchip Capacitor, AnyIn, AnyOut, BodyCom, CodeGuard, intellectual property rights unless otherwise stated. CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, memBrain, Mindi, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. Microchip received ISO/TS-16949:2009 certification for its worldwide SQTP is a service mark of Microchip Technology Incorporated in headquarters, design and wafer fabrication facilities in Chandler and the U.S.A. Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures Silicon Storage Technology is a registered trademark of Microchip are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping Technology Inc. in other countries. devices, Serial EEPROMs, microperipherals, nonvolatile memory and GestIC is a registered trademark of Microchip Technology analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2018, Microchip Technology Incorporated, All Rights Reserved. ISBN: 978-1-5224-3536-5  2009-2018 Microchip Technology Inc. DS20002131D-page 22

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