25AA040A/25LC040A 4K SPI Bus Serial EEPROM Device Selection Table Part Number VCC Range Page Size Temp. Ranges Packages 25AA040A 1.8-5.5V 16 Bytes I P, MS, SN, ST, MN, MC, OT 25LC040A 2.5-5.5V 16 Bytes I, E P, MS, SN, ST, MN, MC, OT Features: Description: • Max. Clock 10 MHz The Microchip Technology Inc. 25XX040A* is a 4 Kbit • Low-Power CMOS Technology: Serial Electrically Erasable Programmable Read-Only Memory (EEPROM). The memory is accessed via a - Max. Write Current: 5 mA at 5.5V, 10 MHz simple Serial Peripheral Interface (SPI) compatible - Read Current: 5 mA at 5.5V, 10 MHz serial bus. The bus signals required are a clock input - Standby Current: 5 A at 5.5V (SCK) plus separate data in (SI) and data out (SO) • 512 x 8-Bit Organization lines. Access to the device is controlled through a Chip • Write Page mode (up to 16 bytes) Select (CS) input. • Sequential Read Communication to the device can be paused via the • Self-timed Erase and Write Cycles (5 ms max.) hold pin (HOLD). While the device is paused, transi- • Block Write Protection: tions on its inputs will be ignored, with the exception of Chip Select, allowing the host to service higher priority - Protect none, 1/4, 1/2 or all of array interrupts. • Built-in Write Protection: The 25XX040A is available in standard packages - Power-on/off data protection circuitry including 8-lead PDIP and SOIC, and advanced - Write enable latch packages including 8-lead MSOP, 8-lead TSSOP - Write-protect pin and rotated TSSOP, 8-lead 2x3 DFN and TDFN, and • High Reliability: 6-lead SOT-23. - Endurance: 1,000,000 Erase/Write cycles Package Types (not to scale) - Data retention: >200 years TSSOP/MSOP PDIP/SOIC - ESD protection: >4000V (ST, MS) (P, SN) • Temperature Ranges Supported: CS 1 8 VCC -- IAnudtuosmtroiatilv (eI) (:E): --4400CC ttoo ++12855CC SSCCOOSS 1212 8787 VHVHCCOOCCLLDD SO 2 7 HOLD WWPP 33 66 SSCCKK WP 3 6 SCK • Pb-Free and RoHS Compliant VVSSSS 44 55 SSII VSS 4 5 SI Pin Function Table SOT-23 DFN/TDFN (MC, MN) (OT) Name Function SCK 1 6 VDD CS 1 8 VCC CS Chip Select Input VSS 2 5 CS SO 2 7 HOLD SI 3 4 SO WP 3 6 SCK SO Serial Data Output VSS 4 5 SI WP Write-Protect VSS Ground X-Rotated TSSOP (X/ST) SI Serial Data Input HOLD 1 8 SCK SCK Serial Clock Input VCC 2 7 SI CS 3 6 VSS HOLD Hold Input SO 4 5 WP VCC Supply Voltage *25XX040A is used in this document as a generic part number for the 25AA040A and the 25LC040A.  2003-2012 Microchip Technology Inc. DS21827H-page 1

25AA040A/25LC040A 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings(†) VCC.............................................................................................................................................................................6.5V All inputs and outputs w.r.t. VSS.........................................................................................................-0.6V to VCC +1.0V Storage temperature.................................................................................................................................-65°C to 150°C Ambient temperature under bias...............................................................................................................-40°C to 125°C ESD protection on all pins..........................................................................................................................................4kV † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an extended period of time may affect device reliability. TABLE 1-1: DC CHARACTERISTICS Industrial (I): TA = -40°C to +85°C VCC = 1.8V to 5.5V DC CHARACTERISTICS Automotive (E): TA = -40°C to +125°C VCC = 2.5V to 5.5V Param. Sym. Characteristic Min. Max. Units Test Conditions No. D001 VIH1 High-level Input 0.7 VCC VCC +1 V Voltage D002 VIL1 Low-level Input -0.3 0.3 VCC V VCC2.7V (Note 1) Voltage D003 VIL2 -0.3 0.2 VCC V VCC < 2.7V (Note 1) D004 VOL Low-level Output — 0.4 V IOL = 2.1mA Voltage D005 VOL — 0.2 V IOL = 1.0mA, VCC = 2.5V D006 VOH High-level Output VCC -0.5 — V IOH = -400A Voltage D007 ILI Input Leakage — ±1 A CS = VCC, VIN = VSS or VCC Current D008 ILO Output Leakage — ±1 A CS = VCC, VOUT = VSS or VCC Current D009 CINT Internal Capacitance — 7 pF TA = 25°C, CLK = 1.0MHz, (all inputs and VCC = 5.0V (Note 1) outputs) D010 ICC Read — 5 mA VCC = 5.5V; FCLK = 10.0MHz; SO = Open Operating Current — 2.5 mA VCC = 2.5V; FCLK = 5.0MHz; SO = Open D011 ICC Write — 5 mA VCC = 5.5V — 3 mA VCC = 2.5V D012 ICCS — 5 A CS = VCC = 5.5V, Inputs tied to VCC or Standby Current VSS, TA = +125°C — 1 A CS = VCC = 2.5V, Inputs tied to VCC or VSS, TA = +85°C Note1: This parameter is periodically sampled and not 100% tested. DS21827H-page 2  2003-2012 Microchip Technology Inc.

25AA040A/25LC040A TABLE 1-2: AC CHARACTERISTICS Industrial (I): TA = -40°C to +85°C VCC = 1.8V to 5.5V AC CHARACTERISTICS Automotive (E): TA = -40°C to +125°C VCC = 2.5V to 5.5V Param. Sym. Characteristic Min. Max. Units Test Conditions No. 1 FCLK Clock Frequency — 10 MHz 4.5V VCC  5.5V — 5 MHz 2.5V VCC  4.5V — 3 MHz 1.8V VCC  2.5V 2 TCSS CS Setup Time 50 — ns 4.5V VCC  5.5V 100 — ns 2.5V VCC  4.5V 150 — ns 1.8V VCC  2.5V 3 TCSH CS Hold Time 100 — ns 4.5V VCC  5.5V 200 — ns 2.5V VCC  4.5V 250 — ns 1.8V VCC  2.5V 4 TCSD CS Disable Time 50 — ns — 5 Tsu Data Setup Time 10 — ns 4.5V VCC  5.5V 20 — ns 2.5V VCC  4.5V 30 — ns 1.8V VCC  2.5V 6 THD Data Hold Time 20 — ns 4.5V VCC  5.5V 40 — ns 2.5V VCC  4.5V 50 — ns 1.8V VCC  2.5V 7 TR CLK Rise Time — 100 ns (Note1) 8 TF CLK Fall Time — 100 ns (Note1) 9 THI Clock High Time 50 — ns 4.5V VCC  5.5V 100 — ns 2.5V VCC  4.5V 150 — ns 1.8V VCC  2.5V 10 TLO Clock Low Time 50 — ns 4.5V VCC  5.5V 100 — ns 2.5V VCC  4.5V 150 — ns 1.8V VCC  2.5V 11 TCLD Clock Delay Time 50 — ns — 12 TCLE Clock Enable Time 50 — ns — 13 TV Output Valid from Clock — 50 ns 4.5V VCC  5.5V Low — 100 ns 2.5V VCC  4.5V — 160 ns 1.8V VCC  2.5V 14 THO Output Hold Time 0 — ns (Note1) 15 TDIS Output Disable Time — 40 ns 4.5V VCC  5.5V (Note1) — 80 ns 2.5V VCC  4.5V (Note1) — 160 ns 1.8V VCC  2.5V (Note1) 16 THS HOLD Setup Time 20 — ns 4.5V VCC  5.5V 40 — ns 2.5V VCC  4.5V 80 — ns 1.8V VCC  2.5V Note1: This parameter is periodically sampled and not 100% tested. 2: This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total Endurance™ Model which can be obtained from Microchip’s web site: www.microchip.com. 3: TWC begins on the rising edge of CS after a valid write sequence and ends when the internal write cycle is complete.  2003-2012 Microchip Technology Inc. DS21827H-page 3

25AA040A/25LC040A TABLE 1-2: AC CHARACTERISTICS (CONTINUED) Industrial (I): TA = -40°C to +85°C VCC = 1.8V to 5.5V AC CHARACTERISTICS Automotive (E): TA = -40°C to +125°C VCC = 2.5V to 5.5V Param. Sym. Characteristic Min. Max. Units Test Conditions No. 17 THH HOLD Hold Time 20 — ns 4.5V VCC  5.5V 40 — ns 2.5V VCC  4.5V 80 — ns 1.8V VCC  2.5V 18 THZ HOLD Low to Output 30 — ns 4.5V VCC  5.5V (Note1) High-Z 60 — ns 2.5V VCC  4.5V (Note1) 160 — ns 1.8V VCC  2.5V (Note1) 19 THV HOLD High to Output 30 — ns 4.5V VCC  5.5V Valid 60 — ns 2.5V VCC  4.5V 160 — ns 1.8V VCC  2.5V 20 TWC Internal Write Cycle Time — 5 ms (Note3) (byte or page) 21 — Endurance 1M — E/W 25°C, VCC = 5.5V (Note2) Cycles Note1: This parameter is periodically sampled and not 100% tested. 2: This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total Endurance™ Model which can be obtained from Microchip’s web site: www.microchip.com. 3: TWC begins on the rising edge of CS after a valid write sequence and ends when the internal write cycle is complete. TABLE 1-3: AC TEST CONDITIONS AC Waveform: VLO = 0.2V — VHI = VCC - 0.2V (Note 1) VHI = 4.0V (Note 2) CL = 100 pF — Timing Measurement Reference Level Input 0.5 VCC Output 0.5 VCC Note1: For VCC  4.0V 2: For VCC 4.0V DS21827H-page 4  2003-2012 Microchip Technology Inc.

25AA040A/25LC040A FIGURE 1-1: HOLD TIMING CS 17 17 16 16 SCK 18 19 High-Impedance SO n + 2 n + 1 n n n - 1 Don’t Care 5 SI n + 2 n + 1 n n n - 1 HOLD FIGURE 1-2: SERIAL INPUT TIMING 4 CS 12 2 11 7 Mode 1,1 8 3 SCK Mode 0,0 5 6 SI MSB in LSB in High-Impedance SO FIGURE 1-3: SERIAL OUTPUT TIMING CS 9 10 3 Mode 1,1 SCK Mode 0,0 13 15 14 SO MSB out ISB out Don’t Care SI  2003-2012 Microchip Technology Inc. DS21827H-page 5

25AA040A/25LC040A 2.0 FUNCTIONAL DESCRIPTION If the write operation is initiated immediately after the WREN instruction without CS driven high, data will not be written to the array since the write enable latch was 2.1 Principles of Operation not properly set. The 25XX040A is a 512-byte Serial EEPROM After setting the write enable latch, the user may designed to interface directly with the Serial Peripheral proceed by driving CS low, issuing a WRITE instruction, Interface (SPI) port of many of today’s popular followed by the remainder of the address, and then the microcontroller families, including Microchip’s PIC® data to be written. Keep in mind that the Most microcontrollers. It may also interface with microcon- Significant address bit (A8) is included in the instruction trollers that do not have a built-in SPI port by using dis- byte for the 25XX040A. Up to 16 bytes of data can be crete I/O lines programmed properly in firmware to sent to the device before a write cycle is necessary. match the SPI protocol. The only restriction is that all of the bytes must reside The 25XX040A contains an 8-bit instruction register. in the same page. Additionally, a page address begins The device is accessed via the SI pin, with data being with ‘XXXX 0000’ and ends with ‘XXXX 1111’. If the clocked in on the rising edge of SCK. The CS pin must internal address counter reaches ‘XXXX 1111’ and be low and the HOLD pin must be high for the entire clock signals continue to be applied to the chip, the operation. address counter will roll back to the first address of the page and over-write any data that previously existed in Table2-1 contains a list of the possible instruction those locations. bytes and format for device operation. All instructions, addresses and data are transferred MSb first, LSb last. Note: Page write operations are limited to Data (SI) is sampled on the first rising edge of SCK writing bytes within a single physical page, after CS goes low. If the clock line is shared with other regardless of the number of bytes peripheral devices on the SPI bus, the user can assert actually being written. Physical page the HOLD input and place the 25XX040A in ‘HOLD’ boundaries start at addresses that are mode. After releasing the HOLD pin, operation will integer multiples of the page buffer size resume from the point when the HOLD was asserted. (or ‘page size’) and, end at addresses that are integer multiples of page size – 1. If a Page Write command attempts to write 2.2 Read Sequence across a physical page boundary, the The device is selected by pulling CS low. The 8-bit result is that the data wraps around to the READ instruction is transmitted to the 25XX040A beginning of the current page (overwriting followed by a 9-bit address. The MSb (A8) is sent to the data previously stored there), instead of slave during the instruction sequence. See Figure 2-1 being written to the next page as might be for more details. expected. It is therefore necessary for the application software to prevent page write After the correct READ instruction and address are sent, operations that would attempt to cross a the data stored in the memory at the selected address page boundary. is shifted out on the SO pin. Data stored in the memory at the next address can be read sequentially by For the data to be actually written to the array, the CS continuing to provide clock pulses to the slave. The must be brought high after the Least Significant bit (D0) internal Address Pointer is automatically incremented of the nth data byte has been clocked in. If CS is driven to the next higher address after each byte of data is high at any other time, the write operation will not be shifted out. When the highest address is reached completed. Refer to Figure2-2 and Figure2-3 for more (1FFh), the address counter rolls over to address 000h detailed illustrations on the byte write sequence and allowing the read cycle to be continued indefinitely. The the page write sequence, respectively. While the write read operation is terminated by raising the CS pin is in progress, the STATUS register may be read to (Figure2-1). check the status of the WPEN, WIP, WEL, BP1 and BP0 bits (Figure2-6). Attempting to read a memory 2.3 Write Sequence array location will not be possible during a write cycle. Polling the WIP bit in the STATUS register is recom- Prior to any attempt to write data to the 25XX040A, the mended in order to determine if a write cycle is in prog- write enable latch must be set by issuing the WREN ress. When the write cycle is completed, the write instruction (Figure2-4). This is done by setting CS low enable latch is reset. and then clocking out the proper instruction into the 25XX040A. After all eight bits of the instruction are transmitted, CS must be driven high to set the write enable latch. DS21827H-page 6  2003-2012 Microchip Technology Inc.

25AA040A/25LC040A BLOCK DIAGRAM STATUS HV Generator Register EEPROM I/O Control Memory X Array Control Logic Logic Dec Page Latches SI SO Y Decoder CS SCK Sense Amp. HOLD R/W Control WP VCC VSS TABLE 2-1: INSTRUCTION SET Instruction Name Instruction Format Description READ 0000 A 011 Read data from memory array beginning at selected address 8 WRITE 0000 A 010 Write data to memory array beginning at selected address 8 WRDI 0000 x100 Reset the write enable latch (disable write operations) WREN 0000 x110 Set the write enable latch (enable write operations) RDSR 0000 x101 Read STATUS register WRSR 0000 x001 Write STATUS register Note: A is the 9th address bit, which is used to address the entire 512 byte array. 8 x = don’t care. FIGURE 2-1: READ SEQUENCE CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 SCK Instruction+Address MSb Lower Address Byte SI 0 0 0 0 A8 0 1 1 A7 A6 A5 A4 A3 A2 A1 A0 Data Out High-Impedance SO 7 6 5 4 3 2 1 0  2003-2012 Microchip Technology Inc. DS21827H-page 7

25AA040A/25LC040A FIGURE 2-2: BYTE WRITE SEQUENCE CS Twc 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 SCK Instruction+Address MSb Lower Address Byte Data Byte SI 0 0 0 0 A8 0 1 0 A7 A6 A5 A4 A3 A2 A1 A0 7 6 5 4 3 2 1 0 High-Impedance SO FIGURE 2-3: PAGE WRITE SEQUENCE CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 SCK Instruction+Address MSb Lower Address Byte Data Byte 1 SI 0 0 0 0 A8 0 1 0 A7 A6 A5 A4 A3 A2 A1 A0 7 6 5 4 3 2 1 0 CS 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 SCK Data Byte 2 Data Byte 3 Data Byte n (16 max.) SI 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 DS21827H-page 8  2003-2012 Microchip Technology Inc.

25AA040A/25LC040A 2.4 Write Enable (WREN) and Write The following is a list of conditions under which the Disable (WRDI) write enable latch will be reset: • Power-up The 25XX040A contains a write enable latch. See • WRDI instruction successfully executed Table2-4 for the Write-Protect Functionality Matrix. This latch must be set before any write operation will be • WRSR instruction successfully executed completed internally. The WREN instruction will set the • WRITE instruction successfully executed latch, and the WRDI will reset the latch. • WP pin is brought low FIGURE 2-4: WRITE ENABLE SEQUENCE (WREN) CS 0 1 2 3 4 5 6 7 SCK SI 0 0 0 0 0 1 1 0 High-Impedance SO FIGURE 2-5: WRITE DISABLE SEQUENCE (WRDI) CS 0 1 2 3 4 5 6 7 SCK SI 0 0 0 0 0 1 10 0 High-Impedance SO  2003-2012 Microchip Technology Inc. DS21827H-page 9

25AA040A/25LC040A 2.5 Read Status Register Instruction The Write Enable Latch (WEL) bit indicates the status (RDSR) of the write enable latch and is read-only. When set to a ‘1’, the latch allows writes to the array, when set to a The Read Status Register instruction (RDSR) provides ‘0’, the latch prohibits writes to the array. The state of access to the STATUS register. See Figure2-6 for the this bit can always be updated via the WREN or WRDI RDSR timing sequence. The STATUS register may be commands regardless of the state of write protection read at any time, even during a write cycle. The on the STATUS register. These commands are shown STATUS register is formatted as follows: in Figure2-4 and Figure2-5. The Block Protection (BP0 and BP1) bits indicate TABLE 2-2: STATUS REGISTER which blocks are currently write-protected. These bits 7 6 5 4 3 2 1 0 are set by the user issuing the WRSR instruction, which is shown in Figure 2-7. These bits are nonvolatile and – – – – W/R W/R R R are described in more detail in Table2-3. X X X X BP1 BP0 WEL WIP W/R = writable/readable. R = read-only. The Write-In-Process (WIP) bit indicates whether the 25XX040A is busy with a write operation. When set to a ‘1’, a write is in progress, when set to a ‘0’, no write is in progress. This bit is read-only. FIGURE 2-6: READ STATUS REGISTER TIMING SEQUENCE (RDSR) CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCK Instruction SI 0 0 0 0 0 1 0 1 Data from STATUS Register High-Impedance SO 7 6 5 4 3 2 1 0 DS21827H-page 10  2003-2012 Microchip Technology Inc.

25AA040A/25LC040A 2.6 Write Status Register Instruction TABLE 2-3: ARRAY PROTECTION (WRSR) Array Addresses BP1 BP0 Write-Protected The Write Status Register instruction (WRSR) allows the user to write to the nonvolatile bits in the STATUS regis- 0 0 none ter as shown in Table2-2. See Figure2-7 for the WRSR 0 1 upper 1/4 timing sequence. Four levels of protection for the array (180h-1FFh) are selectable by writing to the appropriate bits in the STATUS register. The user has the ability to write-protect 1 0 upper 1/2 none, one, two or all four of the segments of the array as (100h-1FFh) shown in Table2-3. 1 1 all (000h-1FFh) FIGURE 2-7: WRITE STATUS REGISTER TIMING SEQUENCE (WRSR) CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCK Instruction Data to STATUS Register SI 0 0 0 0 0 0 0 1 7 6 5 4 3 2 1 0 High-Impedance SO Note: An internal write cycle (TWC) is initiated on the rising edge of CS after a valid write STATUS register sequence.  2003-2012 Microchip Technology Inc. DS21827H-page 11

25AA040A/25LC040A 2.7 Data Protection 2.8 Power-On State The following protection has been implemented to The 25XX040A powers on in the following state: prevent inadvertent writes to the array: • The device is in low-power Standby mode • The write enable latch is reset on power-up (CS=1) • A write enable instruction must be issued to set • The write enable latch is reset the write enable latch • SO is in high-impedance state • After a byte write, page write or STATUS register • A high-to-low-level transition on CS is required to write, the write enable latch is reset enter active state • CS must be set high after the proper number of clock cycles to start an internal write cycle • Access to the array during an internal write cycle is ignored and programming is continued TABLE 2-4: WRITE-PROTECT FUNCTIONALITY MATRIX WP WEL Protected Blocks Unprotected Blocks STATUS Register (pin 3) (SR bit 1) 0 (low) x Protected Protected Protected 1 (high) 0 Protected Protected Protected 1 (high) 1 Protected Writable Writable x = don’t care DS21827H-page 12  2003-2012 Microchip Technology Inc.

25AA040A/25LC040A 3.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table3-1. TABLE 3-1: PIN FUNCTION TABLE Rotated Name PDIP SOIC MSOP TSSOP DFN(1) TDFN(1) SOT-23 Function TSSOP CS 1 1 1 1 1 1 3 5 Chip Select Input SO 2 2 2 2 2 2 4 4 Serial Data Output WP 3 3 3 3 3 3 5 — Write-Protect Pin VSS 4 4 4 4 4 4 6 2 Ground SI 5 5 5 5 5 5 7 3 Serial Data Input SCK 6 6 6 6 6 6 8 1 Serial Clock Input HOLD 7 7 7 7 7 7 1 — Hold Input VCC 8 8 8 8 8 8 2 6 Supply Voltage Note 1: The exposed pad on the DFN/TDFN packages can be connected to VSS or left floating. 3.1 Chip Select (CS) 3.4 Serial Input (SI) A low level on this pin selects the device. A high level The SI pin is used to transfer data into the device. It deselects the device and forces it into Standby mode. receives instructions, addresses and data. Data is However, a programming cycle which is already latched on the rising edge of the serial clock. initiated or in progress will be completed, regardless of the CS input signal. If CS is brought high during a 3.5 Serial Clock (SCK) program cycle, the device will go into Standby mode as The SCK is used to synchronize the communication soon as the programming cycle is complete. When the between a master and the 25XX040A. Instructions, device is deselected, SO goes to the high-impedance addresses or data present on the SI pin are latched on state, allowing multiple parts to share the same SPI the rising edge of the clock input, while data on the SO bus. A low-to-high transition on CS after a valid write pin is updated after the falling edge of the clock input. sequence initiates an internal write cycle. After power- up, a low level on CS is required prior to any sequence 3.6 Hold (HOLD) being initiated. The HOLD pin is used to suspend transmission to the 3.2 Serial Output (SO) 25XX040A while in the middle of a serial sequence without having to retransmit the entire sequence again. The SO pin is used to transfer data out of the It must be held high any time this function is not being 25XX040A. During a read cycle, data is shifted out on used. Once the device is selected and a serial this pin after the falling edge of the serial clock. sequence is underway, the HOLD pin may be pulled 3.3 Write-Protect (WP) low to pause further serial communication without resetting the serial sequence. The HOLD pin must be The WP pin is a hardware write-protect input pin. brought low while SCK is low, otherwise the HOLD When it is low, all writes to the array or STATUS function will not be invoked until the next SCK high-to- registers are disabled, but any other operations low transition. The 25XX040A must remain selected function normally. When WP is high, all functions, during this sequence. The SI, SCK and SO pins are in including nonvolatile writes, operate normally. At any a high-impedance state during the time the device is time, when WP is low, the write enable reset latch will paused and transitions on these pins will be ignored. To be reset and programming will be inhibited. However, resume serial communication, HOLD must be brought if a write cycle is already in progress, WP going low will high while the SCK pin is low, otherwise serial not change or disable the write cycle. See Table 2-4 for communication will not resume. Lowering the HOLD the Write-Protect Functionality Matrix. line at any time will tri-state the SO line.  2003-2012 Microchip Technology Inc. DS21827H-page 13

25AA040A/25LC040A 4.0 PACKAGING INFORMATION 4.1 Package Marking Information 8-Lead PDIP Example: XXXXXXXX 25AA040A T/XXXNNN I/P e 3 1L7 YYWW 0627 8-Lead SOIC Example: XXXXXXXT 25AA04AI XXXXYYWW SN e 3 0627 NNN 1L7 8-Lead TSSOP Example: XXXX 5A4A TYWW I627 NNN 1L7 8-Lead MSOP (150 mil) Example: XXXXXT 5L4AI YWWNNN 6271L7 Part Number 1st Line Marking Codes TSSOP MSOP SOT-23 DFN TDFN Standard Rotated I Temp. E Temp. I Temp E. Temp I Temp. E. Temp 25AA040A 5A4A A4AX 5A4AT 32NN — 421 — C21 — 25LC040A 5L4A L4AX 5L4AT 35NN 36NN 424 425 C24 C25 Note: T = Temperature grade (I, E) NN = Alphanumeric traceability code Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. DS21827H-page 14  2003-2012 Microchip Technology Inc.

25AA040A/25LC040A Package Marking Information (continued) 8-Lead 2X3 DFN Example: XXX 421 YWW 627 L7 NN 8-Lead 2X3 TDFN Example: XXX C24 YWW 627 L7 NN 6-Lead SOT-23 Example: XXNN 32L7  2003-2012 Microchip Technology Inc. DS21827H-page 15

25AA040A/25LC040A (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)(cid:15)(cid:16)(cid:6)(cid:10)(cid:8)(cid:17)(cid:18)(cid:3)(cid:4)(cid:13)(cid:18)(cid:5)(cid:8)(cid:19)(cid:9)(cid:20)(cid:8)(cid:21)(cid:8)(cid:22)(cid:23)(cid:23)(cid:8)(cid:24)(cid:13)(cid:10)(cid:8)(cid:25)(cid:26)(cid:7)(cid:27)(cid:8)(cid:28)(cid:9)(cid:15)(cid:17)(cid:9)(cid:29) (cid:30)(cid:26)(cid:12)(cid:5)(cid:31) 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) N NOTE1 E1 1 2 3 D E A A2 L A1 c e eB b1 b 6(cid:15)(cid:7)&! (cid:19)7,8.(cid:22) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:2)9(cid:7)’(cid:7)&! (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7"’)(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)(cid:31)(cid:7)(cid:15)! 7 < (cid:31)(cid:7)&(cid:8)(cid:11) (cid:14) (cid:20)(cid:30)(cid:4)(cid:4)(cid:2)1(cid:22), (cid:13)(cid:10)(cid:12)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)&(cid:7)(cid:15)(cid:17)(cid:2)(cid:31)(cid:16)(cid:28)(cid:15)(cid:14) (cid:25) = = (cid:20)(cid:3)(cid:30)(cid:4) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:25)(cid:3) (cid:20)(cid:30)(cid:30)(cid:29) (cid:20)(cid:30)-(cid:4) (cid:20)(cid:30)(cid:24)(cid:29) 1(cid:28)!(cid:14)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)&(cid:7)(cid:15)(cid:17)(cid:2)(cid:31)(cid:16)(cid:28)(cid:15)(cid:14) (cid:25)(cid:30) (cid:20)(cid:4)(cid:30)(cid:29) = = (cid:22)(cid:11)(cid:10)"(cid:16)#(cid:14)(cid:9)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:11)(cid:10)"(cid:16)#(cid:14)(cid:9)(cid:2)>(cid:7)#&(cid:11) . (cid:20)(cid:3)(cid:24)(cid:4) (cid:20)-(cid:30)(cid:4) (cid:20)-(cid:3)(cid:29) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)>(cid:7)#&(cid:11) .(cid:30) (cid:20)(cid:3)(cid:23)(cid:4) (cid:20)(cid:3)(cid:29)(cid:4) (cid:20)(cid:3)<(cid:4) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21) (cid:20)-(cid:23)< (cid:20)-?(cid:29) (cid:20)(cid:23)(cid:4)(cid:4) (cid:13)(cid:7)(cid:12)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)&(cid:7)(cid:15)(cid:17)(cid:2)(cid:31)(cid:16)(cid:28)(cid:15)(cid:14) 9 (cid:20)(cid:30)(cid:30)(cid:29) (cid:20)(cid:30)-(cid:4) (cid:20)(cid:30)(cid:29)(cid:4) 9(cid:14)(cid:28)#(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:8) (cid:20)(cid:4)(cid:4)< (cid:20)(cid:4)(cid:30)(cid:4) (cid:20)(cid:4)(cid:30)(cid:29) 6(cid:12)(cid:12)(cid:14)(cid:9)(cid:2)9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) )(cid:30) (cid:20)(cid:4)(cid:23)(cid:4) (cid:20)(cid:4)?(cid:4) (cid:20)(cid:4)(cid:5)(cid:4) 9(cid:10)*(cid:14)(cid:9)(cid:2)9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) ) (cid:20)(cid:4)(cid:30)(cid:23) (cid:20)(cid:4)(cid:30)< (cid:20)(cid:4)(cid:3)(cid:3) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)(cid:26)(cid:10)*(cid:2)(cid:22)(cid:12)(cid:28)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:2)+ (cid:14)1 = = (cid:20)(cid:23)-(cid:4) (cid:30)(cid:26)(cid:12)(cid:5)(cid:11)(cid:31) (cid:30)(cid:20) (cid:31)(cid:7)(cid:15)(cid:2)(cid:30)(cid:2) (cid:7)!"(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)#(cid:14)$(cid:2)%(cid:14)(cid:28)&"(cid:9)(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)((cid:2))"&(cid:2)’"!&(cid:2))(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)*(cid:7)&(cid:11)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)&(cid:8)(cid:11)(cid:14)#(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) +(cid:2)(cid:22)(cid:7)(cid:17)(cid:15)(cid:7)%(cid:7)(cid:8)(cid:28)(cid:15)&(cid:2),(cid:11)(cid:28)(cid:9)(cid:28)(cid:8)&(cid:14)(cid:9)(cid:7)!&(cid:7)(cid:8)(cid:20) -(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)!(cid:2)(cid:21)(cid:2)(cid:28)(cid:15)#(cid:2).(cid:30)(cid:2)#(cid:10)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)"#(cid:14)(cid:2)’(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:20)(cid:2)(cid:6)(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:2)!(cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:14)$(cid:8)(cid:14)(cid:14)#(cid:2)(cid:20)(cid:4)(cid:30)(cid:4)/(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)!(cid:7)#(cid:14)(cid:20) (cid:23)(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)#(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6).(cid:2)0(cid:30)(cid:23)(cid:20)(cid:29)(cid:6)(cid:20) 1(cid:22),2(cid:2)1(cid:28)!(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)&(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)$(cid:28)(cid:8)&(cid:2) (cid:28)(cid:16)"(cid:14)(cid:2)!(cid:11)(cid:10)*(cid:15)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)!(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17),(cid:4)(cid:23)(cid:27)(cid:4)(cid:30)<1 DS21827H-page 16  2003-2012 Microchip Technology Inc.

25AA040A/25LC040A Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2003-2012 Microchip Technology Inc. DS21827H-page 17

25AA040A/25LC040A Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS21827H-page 18  2003-2012 Microchip Technology Inc.

25AA040A/25LC040A (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8) (cid:24)(cid:6)(cid:10)(cid:10)(cid:8)!(cid:16)(cid:12)(cid:10)(cid:13)(cid:18)(cid:5)(cid:8)(cid:19) (cid:30)(cid:20)(cid:8)(cid:21)(cid:8)(cid:30)(cid:6)""(cid:26)#$(cid:8)(cid:22)%&(cid:23)(cid:8)(cid:24)(cid:24)(cid:8)(cid:25)(cid:26)(cid:7)(cid:27)(cid:8)(cid:28) !(cid:17)’(cid:29) (cid:30)(cid:26)(cid:12)(cid:5)(cid:31) 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)  2003-2012 Microchip Technology Inc. DS21827H-page 19

25AA040A/25LC040A (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)()(cid:13)(cid:18)(cid:8) )"(cid:13)(cid:18)*(cid:8) (cid:24)(cid:6)(cid:10)(cid:10)(cid:8)!(cid:16)(cid:12)(cid:10)(cid:13)(cid:18)(cid:5)(cid:8)(cid:19) ((cid:20)(cid:8)(cid:21)(cid:8)+%+(cid:8)(cid:24)(cid:24)(cid:8)(cid:25)(cid:26)(cid:7)(cid:27)(cid:8)(cid:28)( !(cid:9)(cid:29) (cid:30)(cid:26)(cid:12)(cid:5)(cid:31) 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) D N E E1 NOTE1 1 2 b e c φ A A2 A1 L1 L 6(cid:15)(cid:7)&! (cid:6)(cid:19)99(cid:19)(cid:6).(cid:13).(cid:26)(cid:22) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:2)9(cid:7)’(cid:7)&! (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7"’)(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)(cid:31)(cid:7)(cid:15)! 7 < (cid:31)(cid:7)&(cid:8)(cid:11) (cid:14) (cid:4)(cid:20)?(cid:29)(cid:2)1(cid:22), : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)8(cid:14)(cid:7)(cid:17)(cid:11)& (cid:25) = = (cid:30)(cid:20)(cid:3)(cid:4) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:25)(cid:3) (cid:4)(cid:20)<(cid:4) (cid:30)(cid:20)(cid:4)(cid:4) (cid:30)(cid:20)(cid:4)(cid:29) (cid:22)&(cid:28)(cid:15)#(cid:10)%%(cid:2) (cid:25)(cid:30) (cid:4)(cid:20)(cid:4)(cid:29) = (cid:4)(cid:20)(cid:30)(cid:29) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)>(cid:7)#&(cid:11) . ?(cid:20)(cid:23)(cid:4)(cid:2)1(cid:22), (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)>(cid:7)#&(cid:11) .(cid:30) (cid:23)(cid:20)-(cid:4) (cid:23)(cid:20)(cid:23)(cid:4) (cid:23)(cid:20)(cid:29)(cid:4) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21) (cid:3)(cid:20)(cid:24)(cid:4) -(cid:20)(cid:4)(cid:4) -(cid:20)(cid:30)(cid:4) 3(cid:10)(cid:10)&(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) 9 (cid:4)(cid:20)(cid:23)(cid:29) (cid:4)(cid:20)?(cid:4) (cid:4)(cid:20)(cid:5)(cid:29) 3(cid:10)(cid:10)&(cid:12)(cid:9)(cid:7)(cid:15)& 9(cid:30) (cid:30)(cid:20)(cid:4)(cid:4)(cid:2)(cid:26).3 3(cid:10)(cid:10)&(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14) (cid:3) (cid:4)U = <U 9(cid:14)(cid:28)#(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:8) (cid:4)(cid:20)(cid:4)(cid:24) = (cid:4)(cid:20)(cid:3)(cid:4) 9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) ) (cid:4)(cid:20)(cid:30)(cid:24) = (cid:4)(cid:20)-(cid:4) (cid:30)(cid:26)(cid:12)(cid:5)(cid:11)(cid:31) (cid:30)(cid:20) (cid:31)(cid:7)(cid:15)(cid:2)(cid:30)(cid:2) (cid:7)!"(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)#(cid:14)$(cid:2)%(cid:14)(cid:28)&"(cid:9)(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)((cid:2))"&(cid:2)’"!&(cid:2))(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)*(cid:7)&(cid:11)(cid:7)(cid:15)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)&(cid:8)(cid:11)(cid:14)#(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)!(cid:2)(cid:21)(cid:2)(cid:28)(cid:15)#(cid:2).(cid:30)(cid:2)#(cid:10)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)"#(cid:14)(cid:2)’(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:20)(cid:2)(cid:6)(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:2)!(cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:14)$(cid:8)(cid:14)(cid:14)#(cid:2)(cid:4)(cid:20)(cid:30)(cid:29)(cid:2)’’(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)!(cid:7)#(cid:14)(cid:20) -(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)#(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6).(cid:2)0(cid:30)(cid:23)(cid:20)(cid:29)(cid:6)(cid:20) 1(cid:22),2 1(cid:28)!(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)&(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)$(cid:28)(cid:8)&(cid:2) (cid:28)(cid:16)"(cid:14)(cid:2)!(cid:11)(cid:10)*(cid:15)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)!(cid:20) (cid:26).32 (cid:26)(cid:14)%(cid:14)(cid:9)(cid:14)(cid:15)(cid:8)(cid:14)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)((cid:2)"!"(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)((cid:2)%(cid:10)(cid:9)(cid:2)(cid:7)(cid:15)%(cid:10)(cid:9)’(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:12)"(cid:9)(cid:12)(cid:10)!(cid:14)!(cid:2)(cid:10)(cid:15)(cid:16)(cid:18)(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17),(cid:4)(cid:23)(cid:27)(cid:4)<?1 DS21827H-page 20  2003-2012 Microchip Technology Inc.

25AA040A/25LC040A Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2003-2012 Microchip Technology Inc. DS21827H-page 21

25AA040A/25LC040A Note: For the mostcurrent package drawings,please seetheMicrochip Packaging Specification located at http://www.microchip.com/packaging DS21827H-page 22  2003-2012 Microchip Technology Inc.

25AA040A/25LC040A Note: For the mostcurrent package drawings,please seetheMicrochip Packaging Specification located at http://www.microchip.com/packaging  2003-2012 Microchip Technology Inc. DS21827H-page 23

25AA040A/25LC040A Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS21827H-page 24  2003-2012 Microchip Technology Inc.

25AA040A/25LC040A (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)(cid:15)(cid:16)(cid:6)(cid:10)(cid:8),(cid:10)(cid:6)(cid:12)$(cid:8)(cid:30)(cid:26)(cid:8)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:6)(cid:14)*(cid:6)-(cid:5)(cid:8)(cid:19).’(cid:20)(cid:8)(cid:21)(cid:8)/0(cid:22)0(cid:23)%&(cid:8)(cid:24)(cid:24)(cid:8)(cid:25)(cid:26)(cid:7)(cid:27)(cid:8)(cid:28)(cid:15),(cid:30)(cid:29) (cid:30)(cid:26)(cid:12)(cid:5)(cid:31) 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) D e b N N L K E E2 EXPOSEDPAD NOTE1 NOTE1 1 2 2 1 D2 TOPVIEW BOTTOMVIEW A NOTE2 A3 A1 6(cid:15)(cid:7)&! (cid:6)(cid:19)99(cid:19)(cid:6).(cid:13).(cid:26)(cid:22) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:2)9(cid:7)’(cid:7)&! (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7"’)(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)(cid:31)(cid:7)(cid:15)! 7 < (cid:31)(cid:7)&(cid:8)(cid:11) (cid:14) (cid:4)(cid:20)(cid:29)(cid:4)(cid:2)1(cid:22), : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)8(cid:14)(cid:7)(cid:17)(cid:11)& (cid:25) (cid:4)(cid:20)<(cid:4) (cid:4)(cid:20)(cid:24)(cid:4) (cid:30)(cid:20)(cid:4)(cid:4) (cid:22)&(cid:28)(cid:15)#(cid:10)%%(cid:2) (cid:25)(cid:30) (cid:4)(cid:20)(cid:4)(cid:4) (cid:4)(cid:20)(cid:4)(cid:3) (cid:4)(cid:20)(cid:4)(cid:29) ,(cid:10)(cid:15)&(cid:28)(cid:8)&(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:25)- (cid:4)(cid:20)(cid:3)(cid:4)(cid:2)(cid:26).3 : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21) (cid:3)(cid:20)(cid:4)(cid:4)(cid:2)1(cid:22), : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)>(cid:7)#&(cid:11) . -(cid:20)(cid:4)(cid:4)(cid:2)1(cid:22), .$(cid:12)(cid:10)!(cid:14)#(cid:2)(cid:31)(cid:28)#(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21)(cid:3) (cid:30)(cid:20)-(cid:4) = (cid:30)(cid:20)(cid:29)(cid:29) .$(cid:12)(cid:10)!(cid:14)#(cid:2)(cid:31)(cid:28)#(cid:2)>(cid:7)#&(cid:11) .(cid:3) (cid:30)(cid:20)(cid:29)(cid:4) = (cid:30)(cid:20)(cid:5)(cid:29) ,(cid:10)(cid:15)&(cid:28)(cid:8)&(cid:2)>(cid:7)#&(cid:11) ) (cid:4)(cid:20)(cid:3)(cid:4) (cid:4)(cid:20)(cid:3)(cid:29) (cid:4)(cid:20)-(cid:4) ,(cid:10)(cid:15)&(cid:28)(cid:8)&(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) 9 (cid:4)(cid:20)-(cid:4) (cid:4)(cid:20)(cid:23)(cid:4) (cid:4)(cid:20)(cid:29)(cid:4) ,(cid:10)(cid:15)&(cid:28)(cid:8)&(cid:27)&(cid:10)(cid:27).$(cid:12)(cid:10)!(cid:14)#(cid:2)(cid:31)(cid:28)# V (cid:4)(cid:20)(cid:3)(cid:4) = = (cid:30)(cid:26)(cid:12)(cid:5)(cid:11)(cid:31) (cid:30)(cid:20) (cid:31)(cid:7)(cid:15)(cid:2)(cid:30)(cid:2) (cid:7)!"(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)#(cid:14)$(cid:2)%(cid:14)(cid:28)&"(cid:9)(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)((cid:2))"&(cid:2)’"!&(cid:2))(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)*(cid:7)&(cid:11)(cid:7)(cid:15)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)&(cid:8)(cid:11)(cid:14)#(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) (cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2)(cid:11)(cid:28) (cid:14)(cid:2)(cid:10)(cid:15)(cid:14)(cid:2)(cid:10)(cid:9)(cid:2)’(cid:10)(cid:9)(cid:14)(cid:2)(cid:14)$(cid:12)(cid:10)!(cid:14)#(cid:2)&(cid:7)(cid:14)(cid:2))(cid:28)(cid:9)!(cid:2)(cid:28)&(cid:2)(cid:14)(cid:15)#!(cid:20) -(cid:20) (cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)(cid:7)!(cid:2)!(cid:28)*(cid:2)!(cid:7)(cid:15)(cid:17)"(cid:16)(cid:28)&(cid:14)#(cid:20) (cid:23)(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)#(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6).(cid:2)0(cid:30)(cid:23)(cid:20)(cid:29)(cid:6)(cid:20) 1(cid:22),2 1(cid:28)!(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)&(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)$(cid:28)(cid:8)&(cid:2) (cid:28)(cid:16)"(cid:14)(cid:2)!(cid:11)(cid:10)*(cid:15)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)!(cid:20) (cid:26).32 (cid:26)(cid:14)%(cid:14)(cid:9)(cid:14)(cid:15)(cid:8)(cid:14)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)((cid:2)"!"(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)((cid:2)%(cid:10)(cid:9)(cid:2)(cid:7)(cid:15)%(cid:10)(cid:9)’(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:12)"(cid:9)(cid:12)(cid:10)!(cid:14)!(cid:2)(cid:10)(cid:15)(cid:16)(cid:18)(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17),(cid:4)(cid:23)(cid:27)(cid:30)(cid:3)-,  2003-2012 Microchip Technology Inc. DS21827H-page 25

25AA040A/25LC040A Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS21827H-page 26  2003-2012 Microchip Technology Inc.

25AA040A/25LC040A Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2003-2012 Microchip Technology Inc. DS21827H-page 27

25AA040A/25LC040A Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS21827H-page 28  2003-2012 Microchip Technology Inc.

25AA040A/25LC040A (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)(cid:15)(cid:16)(cid:6)(cid:10)(cid:8),(cid:10)(cid:6)(cid:12)$(cid:8)(cid:30)(cid:26)(cid:8)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:6)(cid:14)*(cid:6)-(cid:5)(cid:8)(cid:19).(cid:30)(cid:20)(cid:8)(cid:21)(cid:8)/0(cid:22)0(cid:23)%12(cid:8)(cid:24)(cid:24)(cid:8)(cid:25)(cid:26)(cid:7)(cid:27)(cid:8)(cid:28)((cid:15),(cid:30)(cid:29) (cid:30)(cid:26)(cid:12)(cid:5)(cid:31) 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)  2003-2012 Microchip Technology Inc. DS21827H-page 29

25AA040A/25LC040A 3(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8) (cid:24)(cid:6)(cid:10)(cid:10)(cid:8)!(cid:16)(cid:12)(cid:10)(cid:13)(cid:18)(cid:5)(cid:8)("(cid:6)(cid:18)(cid:11)(cid:13)(cid:11)(cid:12)(cid:26)"(cid:8)(cid:19)!((cid:20)(cid:8)(cid:28) !((cid:3)/(cid:22)(cid:29) (cid:30)(cid:26)(cid:12)(cid:5)(cid:31) 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) b N 4 E E1 PIN1IDBY LASERMARK 1 2 3 e e1 D A A2 c φ L A1 L1 6(cid:15)(cid:7)&! (cid:6)(cid:19)99(cid:19)(cid:6).(cid:13).(cid:26)(cid:22) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:2)9(cid:7)’(cid:7)&! (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7"’)(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)(cid:31)(cid:7)(cid:15)! 7 ? (cid:31)(cid:7)&(cid:8)(cid:11) (cid:14) (cid:4)(cid:20)(cid:24)(cid:29)(cid:2)1(cid:22), :"&!(cid:7)#(cid:14)(cid:2)9(cid:14)(cid:28)#(cid:2)(cid:31)(cid:7)&(cid:8)(cid:11) (cid:14)(cid:30) (cid:30)(cid:20)(cid:24)(cid:4)(cid:2)1(cid:22), : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)8(cid:14)(cid:7)(cid:17)(cid:11)& (cid:25) (cid:4)(cid:20)(cid:24)(cid:4) = (cid:30)(cid:20)(cid:23)(cid:29) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:25)(cid:3) (cid:4)(cid:20)<(cid:24) = (cid:30)(cid:20)-(cid:4) (cid:22)&(cid:28)(cid:15)#(cid:10)%% (cid:25)(cid:30) (cid:4)(cid:20)(cid:4)(cid:4) = (cid:4)(cid:20)(cid:30)(cid:29) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)>(cid:7)#&(cid:11) . (cid:3)(cid:20)(cid:3)(cid:4) = -(cid:20)(cid:3)(cid:4) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)>(cid:7)#&(cid:11) .(cid:30) (cid:30)(cid:20)-(cid:4) = (cid:30)(cid:20)<(cid:4) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21) (cid:3)(cid:20)(cid:5)(cid:4) = -(cid:20)(cid:30)(cid:4) 3(cid:10)(cid:10)&(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) 9 (cid:4)(cid:20)(cid:30)(cid:4) = (cid:4)(cid:20)?(cid:4) 3(cid:10)(cid:10)&(cid:12)(cid:9)(cid:7)(cid:15)& 9(cid:30) (cid:4)(cid:20)-(cid:29) = (cid:4)(cid:20)<(cid:4) 3(cid:10)(cid:10)&(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14) (cid:3) (cid:4)U = -(cid:4)U 9(cid:14)(cid:28)#(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:8) (cid:4)(cid:20)(cid:4)< = (cid:4)(cid:20)(cid:3)? 9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) ) (cid:4)(cid:20)(cid:3)(cid:4) = (cid:4)(cid:20)(cid:29)(cid:30) (cid:30)(cid:26)(cid:12)(cid:5)(cid:11)(cid:31) (cid:30)(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)!(cid:2)(cid:21)(cid:2)(cid:28)(cid:15)#(cid:2).(cid:30)(cid:2)#(cid:10)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)"#(cid:14)(cid:2)’(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:20)(cid:2)(cid:6)(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:2)!(cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:14)$(cid:8)(cid:14)(cid:14)#(cid:2)(cid:4)(cid:20)(cid:30)(cid:3)(cid:5)(cid:2)’’(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)!(cid:7)#(cid:14)(cid:20) (cid:3)(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)#(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6).(cid:2)0(cid:30)(cid:23)(cid:20)(cid:29)(cid:6)(cid:20) 1(cid:22),2 1(cid:28)!(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)&(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)$(cid:28)(cid:8)&(cid:2) (cid:28)(cid:16)"(cid:14)(cid:2)!(cid:11)(cid:10)*(cid:15)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)!(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17),(cid:4)(cid:23)(cid:27)(cid:4)(cid:3)<1 DS21827H-page 30  2003-2012 Microchip Technology Inc.

25AA040A/25LC040A Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2003-2012 Microchip Technology Inc. DS21827H-page 31

25AA040A/25LC040A APPENDIX A: REVISION HISTORY Revision A (9/2003) Initial Release. Revision B (12/2003) Corrections to Section 1.0, Electrical Characteristics. Revision C (2/2006) Added Packages SOT-23, DFN and X-rotated TSSOP; Revised AC Char., Params. 9, 10; Revised Package Legend. Revision D (5/2007) Removed Preliminary status; Replaced package drawings (Rev. AP); Revise Table 1-1, Param. D004, D007, D008; Revise Table 1-2, Param. 7, 8, 9 ,10. Revision E (10/2007) Revised Features (Pb-free); Replaced Package Drawings. Revision F (7/2009) Replaced 6-Lead SOT-23 package drawing (from CH to OT); Revised 8-Lead DFN (MC); Added 8-Lead DFN (MC) Land Pattern. Revision G (11/2011) Added TDFN Package. Revision H (12/2012) Revised Table 1-2, Param. 21. DS21827H-page 32  2003-2012 Microchip Technology Inc.

25AA040A/25LC040A THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at Users of Microchip products can receive assistance www.microchip.com. This web site is used as a means through several channels: to make files and information easily available to • Distributor or Representative customers. Accessible by using your favorite Internet • Local Sales Office browser, the web site contains the following • Field Application Engineer (FAE) information: • Technical Support • Product Support – Data sheets and errata, • Development Systems Information Line application notes and sample programs, design resources, user’s guides and hardware support Customers should contact their distributor, documents, latest software releases and archived representative or field application engineer (FAE) for software support. Local sales offices are also available to help • General Technical Support – Frequently Asked customers. A listing of sales offices and locations is Questions (FAQ), technical support requests, included in the back of this document. online discussion groups, Microchip consultant Technical support is available through the web site program member listing at: http://microchip.com/support • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions.  2003-2012 Microchip Technology Inc. DS21827H-page 33

25AA040A/25LC040A READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480)792-4150. Please list the following information, and use this outline to provide us with your comments about this document. TO: Technical Publications Manager Total Pages Sent ________ RE: Reader Response From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y N Device: 25AA040A/25LC040A Literature Number: DS21827H Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS21827H-page 34  2003-2012 Microchip Technology Inc.

25AA040A/25LC040A PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X X /XX Examples: Device Tape & Reel Temperature Package a) 25AA040A-I/MS = 4 Kbit, 16-byte page, 1.8V Serial EEPROM, Industrial temp., MSOP package b) 25AA040AT-I/SN = 4 Kbit, 16-byte page, 1.8V Serial EEPROM, Industrial temp., Tape & Reel, Device: 25AA040A 4 Kbit, 1.8V, 16 Byte Page, SPI Serial EEPROM SOIC package 25LC040A 4 Kbit, 2.5V, 16 Byte Page, SPI Serial EEPROM c) 25LC040AT-I/SN = 4 Kbit, 16-byte page, 2.5V 25AA040AX 4 Kbit, 1.8V, 16 Byte Page, SPI Serial EEPROM, Serial EEPROM, Industrial temp., Tape & Reel, in alternate pinout (ST only) SOIC package 25LC040AX 4 Kbit, 2.5V, 16 Byte Page, SPI EEPROM, in d) 25LC040AT-I/ST = 4 Kbit, 16-byte page, 2.5V alternate pinout (ST only) Serial EEPROM, Industrial temp., Tape & Reel, Tape & Reel: Blank = Standard packaging TSSOP package T = Tape & Reel e) 25LC040AT-E/SN = 4 Kbit, 16-byte page, 2.5V Temperature I = -40C to+85C Serial EEPROM, Extended temp., Tape & Reel, Range: E = -40C to+125C SOIC package f) 25LC040AX-E/ST = 4 Kbit, 16-byte page, 2.5V Serial EEPROM, Extended temp., rotated pin- Package: MS = Plastic MSOP (Micro Small Outline), 8-lead out, TSSOP package P = Plastic DIP (300 mil body), 8-lead g) 25LC040AT-I/MNY = 4 Kbit, 16-byte page, 2.5V SN = Plastic SOIC (3.90 mm body), 8-lead ST = Plastic TSSOP (4.4 mm body), 8-lead Serial EEPROM, Industrial temp., Tape & Reel, MC = Plastic (2x3x0.9 mm body), 8-lead TDFN package MNY(1) = Plastic TDFN (2x3x0.75 mm body), 8-lead (Tape and Reel only) OT = Plastic SOT-23, 6-lead (Tape and Reel only) Note 1: “Y” indicates a Nickel Palladium Gold (NiPdAu) finish.  2003-2012 Microchip Technology Inc. DS21827H-page 35

25AA040A/25LC040A NOTES: DS21827H-page 36  2003-2012 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC, and may be superseded by updates. It is your responsibility to FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, ensure that your application meets with your specifications. PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash MICROCHIP MAKES NO REPRESENTATIONS OR and UNI/O are registered trademarks of Microchip Technology WARRANTIES OF ANY KIND WHETHER EXPRESS OR Incorporated in the U.S.A. and other countries. IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, INCLUDING BUT NOT LIMITED TO ITS CONDITION, MTP, SEEVAL and The Embedded Control Solutions QUALITY, PERFORMANCE, MERCHANTABILITY OR Company are registered trademarks of Microchip Technology FITNESS FOR PURPOSE. Microchip disclaims all liability Incorporated in the U.S.A. arising from this information and its use. Use of Microchip Silicon Storage Technology is a registered trademark of devices in life support and/or safety applications is entirely at Microchip Technology Inc. in other countries. the buyer’s risk, and the buyer agrees to defend, indemnify and Analog-for-the-Digital Age, Application Maestro, BodyCom, hold harmless Microchip from any and all damages, claims, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, suits, or expenses resulting from such use. No licenses are dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, conveyed, implicitly or otherwise, under any Microchip ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial intellectual property rights. Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O, Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA and Z-Scale are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. GestIC and ULPP are registered trademarks of Microchip Technology Germany II GmbH & Co. & KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2003-2012, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 9781620767245 QUALITY MANAGEMENT SYSTEM Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and CERTIFIED BY DNV Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures == ISO/TS 16949 == are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.  2003-2012 Microchip Technology Inc. DS21827H-page 37

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