25AA256/25LC256 256K SPI™ Bus Serial EEPROM Device Selection Table Part Number VCC Range Page Size Temp. Ranges Packages 25LC256 2.5-5.5V 64 Byte I, E P, SN, ST, MF 25AA256 1.8-5.5V 64 Byte I P, SN, ST, MF Features Description • Max. clock 10 MHz The Microchip Technology Inc. 25AA256/25LC256 (cid:127) Low-power CMOS technology (25XX256*) are 256k-bit Serial Electrically Erasable PROMs. The memory is accessed via a simple Serial - Max. Write Current: 5 mA at 5.5V, 10 MHz Peripheral Interface™ (SPI™) compatible serial bus. - Read Current: 5 mA at 5.5V, 10 MHz The bus signals required are a clock input (SCK) plus - Standby Current: 1 µA at 5.5V separate data in (SI) and data out (SO) lines. Access to (cid:127) 32,768 x 8-bit organization the device is controlled through a Chip Select (CS) (cid:127) 64 byte page input. (cid:127) Self-timed ERASE and WRITE cycles (5 ms Communication to the device can be paused via the max.) hold pin (HOLD). While the device is paused, (cid:127) Block write protection transitions on its inputs will be ignored, with the - Protect none, 1/4, 1/2 or all of array exception of Chip Select, allowing the host to service higher priority interrupts. (cid:127) Built-in write protection - Power-on/off data protection circuitry The 25XX256 is available in standard packages including 8-lead PDIP and SOIC, and advanced - Write enable latch packaging including 8-lead DFN and 8-lead TSSOP. - Write-protect pin Pb-free (Pure Sn) finish is also available. (cid:127) Sequential read (cid:127) High reliability Package Types (not to scale) - Endurance: 1,000,000 erase/write cycles - Data retention: > 200 years TSSOP PDIP/SOIC - ESD protection: > 4000V (ST) (P, SN) (cid:127) Temperature ranges supported; -- IAnudtuosmtroiatilv (eI) (:E): --4400°°CC ttoo ++12855°°CC WSCOSP 123 876 VHSCCOCKLD SCOS 12 25LC 87 HVCOCLD (cid:127) Standard and Pb-free packages available VSS 4 5 SI VWSPS 34 256 65 SSCI K Pin Function Table DFN (MF) Name Function CS 1 8 VCC CS Chip Select Input 2 SO 2 5L 7 HOLD C SO Serial Data Output WP 3 25 6 SCK 6 WP Write-Protect VSS 4 5 SI VSS Ground SI Serial Data Input SPI is a registered trademark of Motorola Corporation. SCK Serial Clock Input HOLD Hold Input VCC Supply Voltage * 25XX256 is used in this document as a generic part number for the 25AA256, 25LC256 devices. Preliminary  2003 Microchip Technology Inc. DS21822C-page 1

25AA256/25LC256 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings (†) VCC.............................................................................................................................................................................6.5V All inputs and outputs w.r.t. VSS.........................................................................................................-0.6V to VCC +1.0V Storage temperature.................................................................................................................................-65°C to 150°C Ambient temperature under bias...............................................................................................................-40°C to 125°C ESD protection on all pins..........................................................................................................................................4kV † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an extended period of time may affect device reliability. TABLE 1-1: DC CHARACTERISTICS Industrial (I): TA = -40°C to +85°C VCC = 1.8V to 5.5V DC CHARACTERISTICS Automotive (E): TA = -40°C to +125°C VCC = 2.5V to 5.5V Param. Sym. Characteristic Min. Max. Units Test Conditions No. D001 VIH1 High-level input .7 VCC VCC+1 V voltage D002 VIL1 Low-level input -0.3 0.3VCC V VCC ≥ 2.7V D003 VIL2 voltage -0.3 0.2VCC V VCC < 2.7V D004 VOL Low-level output — 0.4 V IOL = 2.1mA D005 VOL voltage — 0.2 V IOL = 1.0mA, VCC < 2.5V D006 VOH High-level output VCC -0.5 — V IOH = -400µA voltage D007 ILI Input leakage current — ±1 µA CS = VCC, VIN = VSS TO VCC D008 ILO Output leakage — ±1 µA CS = VCC, VOUT = VSS TO VCC current D009 CINT Internal Capacitance — 7 pF TA = 25°C, CLK = 1.0MHz, (all inputs and VCC = 5.0V (Note) outputs) D010 ICC Read — 5 mA VCC = 5.5V; FCLK = 10.0MHz; — SO = Open Operating Current 2.5 mA VCC = 2.5V; FCLK = 5.0MHz; SO = Open D011 ICC Write — 5 mA VCC = 5.5V — 3 mA VCC = 2.5V D012 ICCS — 5 µA CS = VCC = 5.5V, Inputs tied to VCC or Standby Current — VSS, 125°C 1 µA CS = VCC = 5.5V, Inputs tied to VCC or VSS, 85°C Note: This parameter is periodically sampled and not 100% tested. Preliminary DS21822C-page 2  2003 Microchip Technology Inc.

25AA256/25LC256 TABLE 1-2: AC CHARACTERISTICS Industrial (I): TA = -40°C to +85°C VCC = 1.8V to 5.5V AC CHARACTERISTICS Automotive (E): TA = -40°C to +125°C VCC = 2.5V to 5.5V Param. Sym. Characteristic Min. Max. Units Test Conditions No. 1 FCLK Clock Frequency — 10 MHz 4.5V ≤ Vcc ≤ 5.5V — 5 MHz 2.5V ≤ Vcc < 4.5V — 3 MHz 1.8V ≤ Vcc < 2.5V 2 TCSS CS Setup Time 50 — ns 4.5V ≤ Vcc ≤ 5.5V 100 — ns 2.5V ≤ Vcc < 4.5V 150 — ns 1.8V ≤ Vcc < 2.5V 3 TCSH CS Hold Time 100 — ns 4.5V ≤ Vcc ≤ 5.5V 200 — ns 2.5V ≤ Vcc < 4.5V 250 — ns 1.8V ≤ Vcc < 2.5V 4 TCSD CS Disable Time 50 — ns — 5 Tsu Data Setup Time 10 — ns 4.5V ≤ Vcc ≤ 5.5V 20 — ns 2.5V ≤ Vcc < 4.5V 30 — ns 1.8V ≤ Vcc < 2.5V 6 THD Data Hold Time 20 — ns 4.5V ≤ Vcc ≤ 5.5V 40 — ns 2.5V ≤ Vcc < 4.5V 50 — ns 1.8V ≤ Vcc < 2.5V 7 TR CLK Rise Time — 2 µs (Note1) 8 TF CLK Fall Time — 2 µs (Note1) 9 THI Clock High Time 50 — ns 4.5V ≤ Vcc ≤ 5.5V 100 — ns 2.5V ≤ Vcc < 4.5V 150 — ns 1.8V ≤ Vcc < 2.5V 10 TLO Clock Low Time 50 — ns 4.5V ≤ Vcc ≤ 5.5V 100 — ns 2.5V ≤ Vcc < 4.5V 150 — ns 1.8V ≤ Vcc < 2.5V 11 TCLD Clock Delay Time 50 — ns — 12 TCLE Clock Enable Time 50 — ns — 13 TV Output Valid from Clock — 50 ns 4.5V ≤ Vcc ≤ 5.5V Low — 100 ns 2.5V ≤ Vcc < 4.5V — 160 ns 1.8V ≤ Vcc < 2.5V 14 THO Output Hold Time 0 — ns (Note1) 15 TDIS Output Disable Time — 40 ns 4.5V ≤ Vcc ≤ 5.5V(Note1) — 80 ns 2.5V ≤ Vcc ≤ 4.5V(Note1) — 160 ns 1.8V ≤ Vcc ≤ 2.5V(Note1) 16 THS HOLD Setup Time 20 — ns 4.5V ≤ Vcc ≤ 5.5V 40 — ns 2.5V ≤ Vcc < 4.5V 80 — ns 1.8V ≤ Vcc < 2.5V Note1: This parameter is periodically sampled and not 100% tested. 2: TWC begins on the rising edge of CS after a valid write sequence and ends when the internal write cycle is complete. 3: This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total Endurance™ Model which can be obtained from our web site: www.microchip.com. Preliminary  2003 Microchip Technology Inc. DS21822C-page 3

25AA256/25LC256 TABLE 1-2: AC CHARACTERISTICS (CONTINUED) Industrial (I): TA = -40°C to +85°C VCC = 1.8V to 5.5V AC CHARACTERISTICS Automotive (E): TA = -40°C to +125°C VCC = 2.5V to 5.5V Param. Sym. Characteristic Min. Max. Units Test Conditions No. 17 THH HOLD Hold Time 20 — ns 4.5V ≤ Vcc ≤ 5.5V 40 — ns 2.5V ≤ Vcc < 4.5V 80 — ns 1.8V ≤ Vcc < 2.5V 18 THZ HOLD Low to Output 30 — ns 4.5V ≤ Vcc ≤ 5.5V(Note1) High-Z 60 — ns 2.5V ≤ Vcc < 4.5V(Note1) 160 — ns 1.8V ≤ Vcc < 2.5V(Note1) 19 THV HOLD High to Output 30 — ns 4.5V ≤ Vcc ≤ 5.5V Valid 60 — ns 2.5V ≤ Vcc < 4.5V 160 — ns 1.8V ≤ Vcc < 2.5V 20 TWC Internal Write Cycle Time — 5 ms (NOTE2) 21 — Endurance 1M — E/W (NOTE3) Cycles Note1: This parameter is periodically sampled and not 100% tested. 2: TWC begins on the rising edge of CS after a valid write sequence and ends when the internal write cycle is complete. 3: This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total Endurance™ Model which can be obtained from our web site: www.microchip.com. TABLE 1-3: AC TEST CONDITIONS AC Waveform: VLO = 0.2V — VHI = VCC - 0.2V (Note1) VHI = 4.0V (Note2) CL = 100 pF — Timing Measurement Reference Level Input 0.5 VCC Output 0.5 VCC Note 1: For VCC ≤ 4.0V 2: For Vcc > 4.0V Preliminary DS21822C-page 4  2003 Microchip Technology Inc.

25AA256/25LC256 FIGURE 1-1: HOLD TIMING CS 17 17 16 16 SCK 18 19 high-impedance SO n+2 n+1 n n n-1 don’t care 5 SI n+2 n+1 n n n-1 HOLD FIGURE 1-2: SERIAL INPUT TIMING 4 CS 12 2 11 7 Mode 1,1 8 3 SCK Mode 0,0 5 6 SI MSB in LSB in high-impedance SO FIGURE 1-3: SERIAL OUTPUT TIMING CS 9 10 3 Mode 1,1 SCK Mode 0,0 13 15 14 SO MSB out ISB out don’t care SI Preliminary  2003 Microchip Technology Inc. DS21822C-page 5

25AA256/25LC256 2.0 FUNCTIONAL DESCRIPTION 2.1 Principles of Operation 2.3 Write Sequence The 25XX256 is a 32768 byte Serial EEPROM Prior to any attempt to write data to the 25XX256, the designed to interface directly with the Serial Peripheral write enable latch must be set by issuing the WREN Interface (SPI) port of many of today’s popular instruction (Figure2-4). This is done by setting CS low microcontroller families, including Microchip’s and then clocking out the proper instruction into the PICmicro® microcontrollers. It may also interface with 25XX256. After all eight bits of the instruction are microcontrollers that do not have a built-in SPI port by transmitted, the CS must be brought high to set the using discrete I/O lines programmed properly in write enable latch. If the write operation is initiated firmware to match the SPI protocol. immediately after the WREN instruction without CS being brought high, the data will not be written to the The 25XX256 contains an 8-bit instruction register. The array because the write enable latch will not have been device is accessed via the SI pin, with data being properly set. clocked in on the rising edge of SCK. The CS pin must be low and the HOLD pin must be high for the entire Once the write enable latch is set, the user may operation. proceed by setting the CS low, issuing a WRITE instruction, followed by the 16-bit address, with the first Table2-1 contains a list of the possible instruction MSB of the address being a don’t care bit, and then the bytes and format for device operation. All instructions, data to be written. Up to 64 bytes of data can be sent to addresses, and data are transferred MSB first, LSB the device before a write cycle is necessary. The only last. restriction is that all of the bytes must reside in the Data (SI) is sampled on the first rising edge of SCK same page. after CS goes low. If the clock line is shared with other peripheral devices on the SPI bus, the user can assert Note: Page write operations are limited to writing the HOLD input and place the 25XX256 in ‘HOLD’ bytes within a single physical page, mode. After releasing the HOLD pin, operation will regardless of the number of bytes resume from the point when the HOLD was asserted. actually being written. Physical page boundaries start at addresses that are 2.2 Read Sequence integer multiples of the page buffer size (or ‘page size’) and, end at addresses that are The device is selected by pulling CS low. The 8-bit read integer multiples of page size - 1. If a Page instruction is transmitted to the 25XX256 followed by Write command attempts to write across a the 16-bit address, with the first MSB of the address physical page boundary, the result is that being a don’t care bit. After the correct read instruction the data wraps around to the beginning of and address are sent, the data stored in the memory at the current page (overwriting data the selected address is shifted out on the SO pin. The previously stored there), instead of being data stored in the memory at the next address can be written to the next page as might be read sequentially by continuing to provide clock pulses. expected. It is therefore necessary for the The internal address pointer is automatically incre- application software to prevent page write mented to the next higher address after each byte of operations that would attempt to cross a data is shifted out. When the highest address is page boundary. reached (7FFFh), the address counter rolls over to For the data to be actually written to the array, the CS address 0000h allowing the read cycle to be continued must be brought high after the Least Significant bit (D0) indefinitely. The read operation is terminated by raising of the nth data byte has been clocked in. If CS is the CS pin (Figure2-1). brought high at any other time, the write operation will not be completed. Refer to Figure2-2 and Figure2-3 for more detailed illustrations on the byte write sequence and the page write sequence respectively. While the write is in progress, the Status register may be read to check the status of the WPEN, WIP, WEL, BP1 and BP0 bits (Figure2-6). A read attempt of a memory array location will not be possible during a write cycle. When the write cycle is completed, the write enable latch is reset. Preliminary DS21822C-page 6  2003 Microchip Technology Inc.

25AA256/25LC256 BLOCK DIAGRAM Status HV Generator Register EEPROM I/O Control Memory X Array Control Logic Logic Dec Page Latches SI SO Y Decoder CS SCK Sense Amp. HOLD R/W Control WP VCC VSS TABLE 2-1: INSTRUCTION SET Instruction Name Instruction Format Description READ 0000 0011 Read data from memory array beginning at selected address WRITE 0000 0010 Write data to memory array beginning at selected address WRDI 0000 0100 Reset the write enable latch (disable write operations) WREN 0000 0110 Set the write enable latch (enable write operations) RDSR 0000 0101 Read Status register WRSR 0000 0001 Write Status register FIGURE 2-1: READ SEQUENCE CS 0 1 2 3 4 5 6 7 8 9 10 11 21 22 23 24 25 26 27 28 29 30 31 SCK instruction 16-bit address SI 0 0 0 0 0 0 1 1 15 14 13 12 2 1 0 data out high-impedance SO 7 6 5 4 3 2 1 0 Preliminary  2003 Microchip Technology Inc. DS21822C-page 7

25AA256/25LC256 FIGURE 2-2: BYTE WRITE SEQUENCE CS Twc 0 1 2 3 4 5 6 7 8 9 10 11 21 22 23 24 25 26 27 28 29 30 31 SCK instruction 16-bit address data byte SI 0 0 0 0 0 0 1 0 15 14 13 12 2 1 0 7 6 5 4 3 2 1 0 high-impedance SO FIGURE 2-3: PAGE WRITE SEQUENCE CS 0 1 2 3 4 5 6 7 8 9 10 11 21 22 23 24 25 26 27 28 29 30 31 SCK instruction 16-bit address data byte 1 SI 0 0 0 0 0 0 1 0 15 14 13 12 2 1 0 7 6 5 4 3 2 1 0 CS 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCK data byte 2 data byte 3 data byte n (64 max) SI 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Preliminary DS21822C-page 8  2003 Microchip Technology Inc.

25AA256/25LC256 2.4 Write Enable (WREN) and Write The following is a list of conditions under which the Disable (WRDI) write enable latch will be reset: (cid:127) Power-up The 25XX256 contains a write enable latch. See (cid:127) WRDI instruction successfully executed Table2-4 for the Write-Protect Functionality Matrix. This latch must be set before any write operation will be (cid:127) WRSR instruction successfully executed completed internally. The WREN instruction will set the (cid:127) WRITE instruction successfully executed latch, and the WRDI will reset the latch. FIGURE 2-4: WRITE ENABLE SEQUENCE (WREN) CS 0 1 2 3 4 5 6 7 SCK 0 0 0 0 0 1 1 0 SI high-impedance SO FIGURE 2-5: WRITE DISABLE SEQUENCE (WRDI) CS 0 1 2 3 4 5 6 7 SCK 0 0 0 0 0 1 10 0 SI high-impedance SO Preliminary  2003 Microchip Technology Inc. DS21822C-page 9

25AA256/25LC256 2.5 Read Status Register Instruction The Write Enable Latch (WEL) bit indicates the status (RDSR) of the write enable latch and is read-only. When set to a ‘1’, the latch allows writes to the array, when set to a The Read Status Register instruction (RDSR) provides ‘0’, the latch prohibits writes to the array. The state of access to the Status register. The Status register may this bit can always be updated via the WREN or WRDI be read at any time, even during a write cycle. The commands regardless of the state of write protection Status register is formatted as follows: on the Status register. These commands are shown in Figure2-4 and Figure2-5. TABLE 2-2: STATUS REGISTER The Block Protection (BP0 and BP1) bits indicate 7 6 5 4 3 2 1 0 which blocks are currently write-protected. These bits are set by the user issuing the WRSR instruction. These W/R – – – W/R W/R R R bits are nonvolatile, and are shown in Table2-3. WPEN X X X BP1 BP0 WEL WIP See Figure2-6 for the RDSR timing sequence. W/R = writable/readable. R = read-only. The Write-In-Process (WIP) bit indicates whether the 25XX256 is busy with a write operation. When set to a ‘1’, a write is in progress, when set to a ‘0’, no write is in progress. This bit is read-only. FIGURE 2-6: READ STATUS REGISTER TIMING SEQUENCE (RDSR) CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCK instruction SI 0 0 0 0 0 1 0 1 data from Status register high-impedance SO 7 6 5 4 3 2 1 0 Preliminary DS21822C-page 10  2003 Microchip Technology Inc.

25AA256/25LC256 2.6 Write Status Register Instruction See Figure2-7 for the WRSR timing sequence. (WRSR) TABLE 2-3: ARRAY PROTECTION The Write Status Register instruction (WRSR) allows the user to write to the nonvolatile bits in the Status register Array Addresses BP1 BP0 as shown in Table2-2. The user is able to select one of Write-Protected four levels of protection for the array by writing to the 0 0 none appropriate bits in the Status register. The array is divided up into four segments. The user has the ability 0 1 upper 1/4 to write-protect none, one, two, or all four of the (6000h - 7FFFh) segments of the array. The partitioning is controlled as 1 0 upper 1/2 shown in Table2-3. (4000h - 7FFFh) The Write-Protect Enable (WPEN) bit is a nonvolatile 1 1 all bit that is available as an enable bit for the WP pin. The (0000h - 7FFFh) Write-Protect (WP) pin and the Write-Protect Enable (WPEN) bit in the Status register control the programmable hardware write-protect feature. Hard- ware write protection is enabled when WP pin is low and the WPEN bit is high. Hardware write protection is disabled when either the WP pin is high or the WPEN bit is low. When the chip is hardware write-protected, only writes to nonvolatile bits in the Status register are disabled. See Table2-4 for a matrix of functionality on the WPEN bit. FIGURE 2-7: WRITE STATUS REGISTER TIMING SEQUENCE (WRSR) CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCK instruction data to Status register SI 0 0 0 0 0 0 0 1 7 6 5 4 3 2 1 0 high-impedance SO Note: An internal write cycle (TWC) is initiated on the rising edge of CS after a valid write Status Register sequence. Preliminary  2003 Microchip Technology Inc. DS21822C-page 11

25AA256/25LC256 2.7 Data Protection 2.8 Power-On State The following protection has been implemented to The 25XX256 powers on in the following state: prevent inadvertent writes to the array: (cid:127) The device is in low-power Standby mode (cid:127) The write enable latch is reset on power-up (CS=1) (cid:127) A write enable instruction must be issued to set (cid:127) The write enable latch is reset the write enable latch (cid:127) SO is in high-impedance state (cid:127) After a byte write, page write or Status register (cid:127) A high-to-low-level transition on CS is required to write, the write enable latch is reset enter active state (cid:127) CS must be set high after the proper number of clock cycles to start an internal write cycle (cid:127) Access to the array during an internal write cycle is ignored and programming is continued TABLE 2-4: WRITE-PROTECT FUNCTIONALITY MATRIX WEL WPEN WP Protected Blocks Unprotected Blocks Status Register (SR bit 1) (SR bit 7) (pin 3) 0 x x Protected Protected Protected 1 0 x Protected Writable Writable 1 1 0 (low) Protected Writable Protected 1 1 1 (high) Protected Writable Writable x = don’t care Preliminary DS21822C-page 12  2003 Microchip Technology Inc.

25AA256/25LC256 3.0 PIN DESCRIPTIONS The WP pin function is blocked when the WPEN bit in the Status register is low. This allows the user to install The descriptions of the pins are listed in Table3-1. the 25XX256 in a system with WP pin grounded and still be able to write to the Status register. The WP pin TABLE 3-1: PIN FUNCTION TABLE functions will be enabled when the WPEN bit is set high. Name Pin Number Function 3.4 Serial Input (SI) CS 1 Chip Select Input The SI pin is used to transfer data into the device. It SO 2 Serial Data Output receives instructions, addresses and data. Data is latched on the rising edge of the serial clock. WP 3 Write-Protect Pin VSS 4 Ground 3.5 Serial Clock (SCK) SI 5 Serial Data Input The SCK is used to synchronize the communication SCK 6 Serial Clock Input between a master and the 25XX256. Instructions, addresses or data present on the SI pin are latched on HOLD 7 Hold Input the rising edge of the clock input, while data on the SO VCC 8 Supply Voltage pin is updated after the falling edge of the clock input. 3.1 Chip Select (CS) 3.6 Hold (HOLD) A low level on this pin selects the device. A high level The HOLD pin is used to suspend transmission to the deselects the device and forces it into Standby mode. 25XX256 while in the middle of a serial sequence with- However, a programming cycle which is already out having to retransmit the entire sequence again. It initiated or in progress will be completed, regardless of must be held high any time this function is not being the CS input signal. If CS is brought high during a used. Once the device is selected and a serial program cycle, the device will go into Standby mode as sequence is underway, the HOLD pin may be pulled low to pause further serial communication without soon as the programming cycle is complete. When the device is deselected, SO goes to the high-impedance resetting the serial sequence. The HOLD pin must be state, allowing multiple parts to share the same SPI brought low while SCK is low, otherwise the HOLD bus. A low-to-high transition on CS after a valid write function will not be invoked until the next SCK high-to- sequence initiates an internal write cycle. After power- low transition. The 25XX256 must remain selected up, a low level on CS is required prior to any sequence during this sequence. The SI, SCK and SO pins are in being initiated. a high-impedance state during the time the device is paused and transitions on these pins will be ignored. To 3.2 Serial Output (SO) resume serial communication, HOLD must be brought high while the SCK pin is low, otherwise serial The SO pin is used to transfer data out of the 25XX256. communication will not resume. Lowering the HOLD During a read cycle, data is shifted out on this pin after line at any time will tri-state the SO line. the falling edge of the serial clock. 3.3 Write-Protect (WP) This pin is used in conjunction with the WPEN bit in the Status register to prohibit writes to the nonvolatile bits in the Status register. When WP is low and WPEN is high, writing to the nonvolatile bits in the Status register is disabled. All other operations function normally. When WP is high, all functions, including writes to the nonvolatile bits in the Status register, operate normally. If the WPEN bit is set, WP low during a Status register write sequence will disable writing to the Status register. If an internal write cycle has already begun, WP going low will have no effect on the write. Preliminary  2003 Microchip Technology Inc. DS21822C-page 13

25AA256/25LC256 4.0 PACKAGING INFORMATION 4.1 Package Marking Information 8-Lead DFN Example: XXXXXXX 25LC256 T/XXXXX I/MF YYWW 0328 NNN 1L7 8-Lead PDIP Example: XXXXXXXX 25AA256 T/XXXNNN I/P 1L7 YYWW 0328 8-Lead SOIC Example: XXXXXXXX 25LC256 T/XXYYWW I/SN 0328 NNN 1L7 8-Lead TSSOP Example: TSSOP 1st Line Marking Codes XXXX 5LE Pb-free TYWW I328 Device std mark mark NNN 1L7 25AA256 5AE NAE 25LC256 5LE NLE Legend: XX...X Part number T Temperature (I, E) Blank Commercial YY Year code (last 2 digits of calendar year) except TSSOP which uses only the last 1 digit WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code Note: Custom marking available. Preliminary DS21822C-page 14  2003 Microchip Technology Inc.

25AA256/25LC256 8-Lead Plastic Dual Flat No Lead Package (MF) 6x5 mm Body (DFN-S) E B p E1 n L R D1 D D2 PIN 1 EXPOSED ID METAL 1 2 PADS E2 TOP VIEW BOTTOM VIEW α A2 A3 A A1 Units INCHES MILLIMETERS* Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 8 8 Pitch p .050 BSC 1.27 BSC Overall Height A .033 .039 0.85 1.00 Molded Package Thickness A2 .026 .031 0.65 0.80 Standoff A1 .000 .0004 .002 0.00 0.01 0.05 Base Thickness A3 .008 REF. 0.20 REF. Overall Length E .194 BSC 4.92 BSC Molded Package Length E1 .184 BSC 4.67 BSC Exposed Pad Length E2 .152 .158 .163 3.85 4.00 4.15 Overall Width D .236 BSC 5.99 BSC Molded Package Width D1 .226 BSC 5.74 BSC Exposed Pad Width D2 .085 .091 .097 2.16 2.31 2.46 Lead Width B .014 .016 .019 0.35 0.40 0.47 Lead Length L .020 .024 .030 0.50 0.60 0.75 Tie Bar Width R .014 .356 Mold Draft Angle Top α 12 12 *Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC equivalent: pending Drawing No. C04-113 Preliminary  2003 Microchip Technology Inc. DS21822C-page 15

25AA256/25LC256 8-Lead Plastic Dual In-line (P) – 300 mil (PDIP) E1 D 2 n 1 α E A A2 L c A1 β B1 p eB B Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 8 8 Pitch p .100 2.54 Top to Seating Plane A .140 .155 .170 3.56 3.94 4.32 Molded Package Thickness A2 .115 .130 .145 2.92 3.30 3.68 Base to Seating Plane A1 .015 0.38 Shoulder to Shoulder Width E .300 .313 .325 7.62 7.94 8.26 Molded Package Width E1 .240 .250 .260 6.10 6.35 6.60 Overall Length D .360 .373 .385 9.14 9.46 9.78 Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43 Lead Thickness c .008 .012 .015 0.20 0.29 0.38 Upper Lead Width B1 .045 .058 .070 1.14 1.46 1.78 Lower Lead Width B .014 .018 .022 0.36 0.46 0.56 Overall Row Spacing § eB .310 .370 .430 7.87 9.40 10.92 Mold Draft Angle Top α 5 10 15 5 10 15 Mold Draft Angle Bottom β 5 10 15 5 10 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-018 Preliminary DS21822C-page 16  2003 Microchip Technology Inc.

25AA256/25LC256 8-Lead Plastic Small Outline (SN) –Narrow, 150 mil (SOIC) E E1 p D 2 B n 1 h α 45° c A A2 φ β L A1 Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 8 8 Pitch p .050 1.27 Overall Height A .053 .061 .069 1.35 1.55 1.75 Molded Package Thickness A2 .052 .056 .061 1.32 1.42 1.55 Standoff § A1 .004 .007 .010 0.10 0.18 0.25 Overall Width E .228 .237 .244 5.79 6.02 6.20 Molded Package Width E1 .146 .154 .157 3.71 3.91 3.99 Overall Length D .189 .193 .197 4.80 4.90 5.00 Chamfer Distance h .010 .015 .020 0.25 0.38 0.51 Foot Length L .019 .025 .030 0.48 0.62 0.76 Foot Angle φ 0 4 8 0 4 8 Lead Thickness c .008 .009 .010 0.20 0.23 0.25 Lead Width B .013 .017 .020 0.33 0.42 0.51 Mold Draft Angle Top α 0 12 15 0 12 15 Mold Draft Angle Bottom β 0 12 15 0 12 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-057 Preliminary  2003 Microchip Technology Inc. DS21822C-page 17

25AA256/25LC256 8-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP) E E1 p D 2 1 n B α A c φ A1 A2 β L Units INCHES MILLIMETERS* Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 8 8 Pitch p .026 0.65 Overall Height A .043 1.10 Molded Package Thickness A2 .033 .035 .037 0.85 0.90 0.95 Standoff § A1 .002 .004 .006 0.05 0.10 0.15 Overall Width E .246 .251 .256 6.25 6.38 6.50 Molded Package Width E1 .169 .173 .177 4.30 4.40 4.50 Molded Package Length D .114 .118 .122 2.90 3.00 3.10 Foot Length L .020 .024 .028 0.50 0.60 0.70 Foot Angle φ 0 4 8 0 4 8 Lead Thickness c .004 .006 .008 0.09 0.15 0.20 Lead Width B .007 .010 .012 0.19 0.25 0.30 Mold Draft Angle Top α 0 5 10 0 5 10 Mold Draft Angle Bottom β 0 5 10 0 5 10 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005” (0.127mm) per side. JEDEC Equivalent: MO-153 Drawing No. C04-086 Preliminary DS21822C-page 18  2003 Microchip Technology Inc.

25AA256/25LC256 APPENDIX A: REVISION HISTORY Revision C Corrections to Section 1.0, Electrical Characteristics. Preliminary  2003 Microchip Technology Inc. DS21822C-page 19

25AA256/25LC256 NOTES: Preliminary DS21822C-page 20  2003 Microchip Technology Inc.

25AA256/25LC256 ON-LINE SUPPORT SYSTEMS INFORMATION AND UPGRADE HOT LINE Microchip provides on-line support on the Microchip World Wide Web site. The Systems Information and Upgrade Line provides The web site is used by Microchip as a means to make system users a listing of the latest versions of all of files and information easily available to customers. To Microchip's development systems software products. view the site, the user must have access to the Internet Plus, this line provides information on how customers and a web browser, such as Netscape® or Microsoft® can receive the most current upgrade kits.The Hot Line Internet Explorer. Files are also available for FTP Numbers are: download from our FTP site. 1-800-755-2345 for U.S. and most of Canada, and 1-480-792-7302 for the rest of the world. Connecting to the Microchip Internet Web Site 042003 The Microchip web site is available at the following URL: www.microchip.com The file transfer site is available by using an FTP service to connect to: ftp://ftp.microchip.com The web site and file transfer site provide a variety of services. Users may download files for the latest Development Tools, Data Sheets, Application Notes, User's Guides, Articles and Sample Programs. A variety of Microchip specific business information is also available, including listings of Microchip sales offices, distributors and factory representatives. Other data available for consideration is: (cid:127) Latest Microchip Press Releases (cid:127) Technical Support Section with Frequently Asked Questions (cid:127) Design Tips (cid:127) Device Errata (cid:127) Job Postings (cid:127) Microchip Consultant Program Member Listing (cid:127) Links to other useful web sites related to Microchip Products (cid:127) Conferences for products, Development Systems, technical information and more (cid:127) Listing of seminars and events Preliminary  2003 Microchip Technology Inc. DS21822C-page 21

25AA256/25LC256 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod- uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: Technical Publications Manager Total Pages Sent ________ RE: Reader Response From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y N Device: 25AA256/25LC256 Literature Number: DS21822C Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? Preliminary DS21822C-page 22  2003 Microchip Technology Inc.

25AA256/25LC256 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X – X /XX X Examples: Device Tape & Reel Temp Range Package Lead a) 25AA256-I/STG = 256k-bit, 1.8V Serial Finish EEPROM, Industrial temp., TSSOP package, Pb-free b) 25AA256T-I/SN = 256k-bit, 1.8V Serial EEPROM, Industrial temp., Tape & Reel, SOIC Device 25AA256 256k-bit, 1.8V, 64-Byte Page, SPI Serial EEPROM package 25LC256 256k-bit, 2.5V, 64-Byte Page, SPI Serial EEPROM c) 25AA256T-I/ST = 256k-bit, 1.8V Serial EEPROM, Industrial temp., Tape & Reel, Tape & Reel Blank = Standard packaging (tube) TSSOP package T = Tape & Reel d) 25LC256-I/STG = 256k-bit, 2.5V Serial Temperature Range I = -40°C to+85°C EEPROM, Industrial temp., TSSOP package, E = -40°C to+125°C Pb-free e) 25LC256-I/P = 256k-bit, 2.5V Serial EEPROM, Industrial temp., P-DIP package Package MF = Micro Lead Frame (6 x 5 mm body), 8-lead f) 25LC256T-E/ST = 256k-bit, 2.5V Serial P = Plastic DIP (300 mil body), 8-lead SN = Plastic SOIC (150 mil body), 8-lead EEPROM, Extended temp., Tape & Reel, ST = TSSOP, 8-lead TSSOP package Lead Finish Blank = Standard 63% / 37% Sn/Pb G = Matte Tin (Pure Sn) Sales and Support Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. Your local Microchip sales office 2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277 3. The Microchip Worldwide Site (www.microchip.com) Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products. Preliminary  2003 Microchip Technology Inc. DS21822C-page 23

25AA256/25LC256 NOTES: Preliminary DS21822C-page 24  2003 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices: (cid:127) Microchip products meet the specification contained in their particular Microchip Data Sheet. (cid:127) Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. (cid:127) There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. (cid:127) Microchip is willing to work with the customer who is concerned about the integrity of their code. (cid:127) Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is intended through suggestion only The Microchip name and logo, the Microchip logo, Accuron, and may be superseded by updates. It is your responsibility to dsPIC, KEELOQ, MPLAB, PIC, PICmicro, PICSTART, ensure that your application meets with your specifications. PRO MATE and PowerSmart are registered trademarks of No representation or warranty is given and no liability is Microchip Technology Incorporated in the U.S.A. and other assumed by Microchip Technology Incorporated with respect countries. to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such AmpLab, FilterLab, microID, MXDEV, MXLAB, PICMASTER, use or otherwise. Use of Microchip’s products as critical com- SEEVAL and The Embedded Control Solutions Company are ponents in life support systems is not authorized except with registered trademarks of Microchip Technology Incorporated express written approval by Microchip. No licenses are con- in the U.S.A. veyed, implicitly or otherwise, under any intellectual property Application Maestro, dsPICDEM, dsPICDEM.net, ECAN, rights. ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, microPort, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPIC, Select Mode, SmartSensor, SmartShunt, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. Serialized Quick Turn Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2003, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999 and Mountain View, California in March 2002. The Company’s quality system processes and procedures are QS-9000 compliant for its PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, non-volatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001 certified. Preliminary  2003 Microchip Technology Inc. DS21822C-page 25

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Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: M icrochip: 25LC256-E/MF 25LC256-E/ST 25LC256-E/SN 25AA256-I/P 25AA256T-I/SN 25AA256T-I/ST 25AA256-I/MF 25AA256T-I/MF 25AA256-I/ST 25AA256-I/SN 25LC256T-E/ST 25LC256T-E/SN 25LC256-I/P 25LC256-I/MF 25LC256-I/SN 25LC256-E/P 25LC256T-I/SN 25LC256T-I/MF 25LC256T-I/ST 25LC256T-E/MF 25LC256-I/ST