25AA128/25LC128 128K SPI Bus Serial EEPROM Device Selection Table Part Number VCC Range Page Size Temp. Ranges Packages 25AA128 1.8V-5.5V 64 Byte I MF, P, SN, SM, ST 25LC128 2.5V-5.5V 64 Byte I, E MF, P, SN, SM, ST Features Pin Function Table • Maximum Clock: 10MHz Name Function • Low-Power CMOS Technology: CS Chip Select Input - Write current (maximum): 5mA at 5.5V, SO Serial Data Output 10 MHz WP Write-Protect - Read current: 5mA at 5.5V, 10MHz - Standby current: 5µA at 5.5V VSS Ground • 16,384 x 8-Bit Organization SI Serial Data Input • 64-Byte Page SCK Serial Clock Input • Self-Timed Erase and Write Cycles HOLD Hold Input (5ms maximum) VCC Supply Voltage • Block Write Protection: - Protect none, 1/4, 1/2 or all of array Description • Built-In Write Protection: - Power-on/off data protection circuitry The Microchip Technology Inc. 25XX128(1) is a - Write enable latch 128Kbit Serial Electrically Erasable PROM. The mem- ory is accessed via a simple Serial Peripheral Interface - Write-protect pin (SPI) compatible serial bus. The bus signals required • Sequential Read are a clock input (SCK) plus separate data in (SI) and • High Reliability: data out (SO) lines. Access to the device is controlled - Endurance: 1,000,000 erase/write cycles through a Chip Select (CS) input. - Data retention: >200 years Communication to the device can be paused via the - ESD protection: >4000V hold pin (HOLD). While the device is paused, • RoHS Compliant transitions on its inputs will be ignored, with the exception of Chip Select, allowing the host to service • Temperature Ranges; higher priority interrupts. - Industrial (I): -40C to +85C - Extended (E): -40°C to +125°C Note1: 25XX128 is used in this document as a • Automotive AEC-Q100 Qualified generic part number for the 25AA128/ 25LC128 devices. Packages • 8-Lead DFN, 8-Lead PDIP, 8-Lead SOIC, 8-Lead SOIJ and 8-Lead TSSOP 8-Lead DFN 8-Lead PDIP/SOIC/SOIJ 8-Lead TSSOP 8-Lead X-Rotated TSSOP (Top View) (Top View) (Top View) (Top View) CS 1 8 VCC CS 11 88 VCC SO 2 7 HOLD SO 22 77 HOLD SCOS 12 87 HVCOCLD HOVLCDC 12 87 SSCIK WP 3 6 SCK WP 33 66 SCK WP 3 6 SCK CS 3 6 VSS VSS 4 5 SI VSS 44 55 SI VSS 4 5 SI SO 4 5 WP  2003-2019 Microchip Technology Inc. DS20001831F-page 1

25AA128/25LC128 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings (†) VCC.............................................................................................................................................................................6.5V All inputs and outputs w.r.t. VSS..........................................................................................................-0.6V to VCC +1.0V Storage temperature.................................................................................................................................-65°C to 150°C Ambient temperature under bias...............................................................................................................-40°C to 125°C ESD protection on all pins..........................................................................................................................................4kV † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an extended period of time may affect device reliability. TABLE 1-1: DC CHARACTERISTICS Industrial (I): TA = -40°C to +85°C VCC = 1.8V to 5.5V DC CHARACTERISTICS Extended (E): TA = -40°C to +125°C VCC = 2.5V to 5.5V Param. Symbol Characteristic Min. Max. Units Conditions No. D1 VIH High-Level Input Voltage 0.7 VCC VCC+1 V D2 VIL1 Low-Level Input Voltage -0.3 0.3VCC V VCC2.7V D3 VIL2 -0.3 0.2VCC V VCC < 2.7V D4 VOL Low-Level Output Voltage — 0.4 V IOL = 2.1mA D5 VOL — 0.2 V IOL = 1.0mA, VCC < 2.5V D6 VOH High-Level Output Voltage VCC -0.5 — V IOH = -400µA D7 ILI Input Leakage Current — ±1 µA CS = VCC, VIN = VSS or VCC D8 ILO Output Leakage Current — ±1 µA CS = VCC, VOUT = VSS or VCC D9 CINT Internal Capacitance — 7 pF TA = 25°C, CLK = 1.0MHz, (all inputs and outputs) VCC = 5.0V (Note) D10 ICC Read Operating Current — 5 mA VCC = 5.5V, FCLK = 10.0MHz, SO = Open — 2.5 mA VCC = 2.5V, FCLK = 5.0MHz SO = Open D11 ICC Write Operating Current — 5 mA VCC = 5.5V — 3 mA VCC = 2.5V D12 ICCS Standby Current — 5 µA CS = VCC = 5.5V, Inputs tied to VCC or VSS, 125°C — 1 µA CS = VCC = 5.5V, Inputs tied to VCC or VSS, 85°C Note: This parameter is periodically sampled and not 100% tested.  2003-2019 Microchip Technology Inc. DS20001831F-page 2

25AA128/25LC128 TABLE 1-2: AC CHARACTERISTICS Industrial (I): TA = -40°C to +85°C VCC = 1.8V to 5.5V AC CHARACTERISTICS Extended (E): TA = -40°C to +125°C VCC = 2.5V to 5.5V Param. Symbol Characteristic Min. Max. Units Conditions No. 1 FCLK Clock Frequency — 10 MHz 4.5V Vcc  5.5V — 5 MHz 2.5V Vcc  4.5V — 3 MHz 1.8V Vcc  2.5V 2 TCSS CS Setup Time 50 — ns 4.5V Vcc  5.5V 100 — ns 2.5V Vcc  4.5V 150 — ns 1.8V Vcc  2.5V 3 TCSH CS Hold Time 100 — ns 4.5V Vcc  5.5V 200 — ns 2.5V Vcc  4.5V 250 — ns 1.8V Vcc  2.5V 4 TCSD CS Disable Time 50 — ns 5 TSU Data Setup Time 10 — ns 4.5V Vcc  5.5V 20 — ns 2.5V Vcc  4.5V 30 — ns 1.8V Vcc  2.5V 6 THD Data Hold Time 20 — ns 4.5V Vcc  5.5V 40 — ns 2.5V Vcc  4.5V 50 — ns 1.8V Vcc  2.5V 7 TR CLK Rise Time — 100 ns Note1 8 TF CLK Fall Time — 100 ns Note1 9 THI Clock High Time 50 — ns 4.5V Vcc  5.5V 100 — ns 2.5V Vcc  4.5V 150 — ns 1.8V Vcc  2.5V 10 TLO Clock Low Time 50 — ns 4.5V Vcc  5.5V 100 — ns 2.5V Vcc  4.5V 150 — ns 1.8V Vcc  2.5V 11 TCLD Clock Delay Time 50 — ns 12 TCLE Clock Enable Time 50 — ns 13 TV Output Valid from Clock — 50 ns 4.5V Vcc  5.5V Low — 100 ns 2.5V Vcc  4.5V — 160 ns 1.8V Vcc  2.5V 14 THO Output Hold Time 0 — ns Note1 15 TDIS Output Disable Time — 40 ns 4.5V Vcc  5.5V (Note1) — 80 ns 2.5V Vcc  4.5V (Note1) — 160 ns 1.8V Vcc  2.5V (Note1) Note 1: This parameter is periodically sampled and not 100% tested. 2: TWC begins on the rising edge of CS after a valid write sequence and ends when the internal write cycle is complete. 3: This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total Endurance™ Model which can be obtained from Microchip’s website: www.microchip.com.  2003-2019 Microchip Technology Inc. DS20001831F-page 3

25AA128/25LC128 TABLE 1-2: AC CHARACTERISTICS (CONTINUED) Industrial (I): TA = -40°C to +85°C VCC = 1.8V to 5.5V AC CHARACTERISTICS Extended (E): TA = -40°C to +125°C VCC = 2.5V to 5.5V Param. Symbol Characteristic Min. Max. Units Conditions No. 16 THS HOLD Setup Time 20 — ns 4.5V Vcc  5.5V 40 — ns 2.5V Vcc  4.5V 80 — ns 1.8V Vcc  2.5V 17 THH HOLD Hold Time 20 — ns 4.5V Vcc  5.5V 40 — ns 2.5V Vcc  4.5V 80 — ns 1.8V Vcc  2.5V 18 THZ HOLD Low to Output — 30 ns 4.5V Vcc  5.5V (Note1) High-Z — 60 ns 2.5V Vcc  4.5V (Note1) — 160 ns 1.8V Vcc  2.5V (Note1) 19 THV HOLD High to Output — 30 ns 4.5V Vcc  5.5V Valid — 60 ns 2.5V Vcc  4.5V — 160 ns 1.8V Vcc  2.5V 20 TWC Internal Write Cycle Time — 5 ms Note2 21 Endurance 1,000,000 — E/W Page mode, 25°C, VCC = 5.5V Cycles (Note3) Note 1: This parameter is periodically sampled and not 100% tested. 2: TWC begins on the rising edge of CS after a valid write sequence and ends when the internal write cycle is complete. 3: This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total Endurance™ Model which can be obtained from Microchip’s website: www.microchip.com. TABLE 1-1: AC TEST CONDITIONS AC Waveform: VLO = 0.2V VHI = VCC - 0.2V Note1 VHI = 4.0V Note2 CL = 50 pF Timing Measurement Reference Level Input 0.5 VCC Output 0.5 VCC Note 1: For VCC  4.0V 2: For VCC > 4.0V  2003-2019 Microchip Technology Inc. DS20001831F-page 4

25AA128/25LC128 FIGURE 1-1: HOLD TIMING CS 17 17 16 16 SCK 18 19 High-Impedance SO n + 2 n + 1 n n n - 1 Don’t Care 5 SI n + 2 n + 1 n n n - 1 HOLD FIGURE 1-2: SERIAL INPUT TIMING 4 CS 12 2 11 7 Mode 1,1 8 3 SCK Mode 0,0 5 6 SI MSB in LSB in High-Impedance SO FIGURE 1-3: SERIAL OUTPUT TIMING CS 9 10 3 Mode 1,1 SCK Mode 0,0 13 15 14 SO MSB out LSB out Don’t Care SI  2003-2019 Microchip Technology Inc. DS20001831F-page 5

25AA128/25LC128 2.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table2-1. TABLE 2-1: PIN FUNCTION TABLE Name DFN(1) PDIP SOIC SOIJ TSSOP X-Rotated TSSOP Function CS 1 1 1 1 1 3 Chip Select Input SO 2 2 2 2 2 4 Serial Data Output WP 3 3 3 3 3 5 Write-Protect Pin VSS 4 4 4 4 4 6 Ground SI 5 5 5 5 5 7 Serial Data Input SCK 6 6 6 6 6 8 Serial Clock Input HOLD 7 7 7 7 7 1 Hold Input VCC 8 8 8 8 8 2 Supply Voltage Note 1: The exposed pad on the DFN package can be connected to VSS or left floating. 2.1 Chip Select (CS) The WP pin functions will be enabled when the WPEN bit is set high. A low level on this pin selects the device. A high level deselects the device and forces it into Standby mode. 2.4 Serial Input (SI) However, a programming cycle which is already initiated or in progress will be completed, regardless of The SI pin is used to transfer data into the device. It the CS input signal. If CS is brought high during a receives instructions, addresses and data. Data is program cycle, the device will go into Standby mode as latched on the rising edge of the serial clock. soon as the programming cycle is complete. When the 2.5 Serial Clock (SCK) device is deselected, SO goes to the high-impedance state, allowing multiple parts to share the same SPI The SCK is used to synchronize the communication bus. A low-to-high transition on CS after a valid write between a master and the 25XX128. Instructions, sequence initiates an internal write cycle. After power- addresses or data present on the SI pin are latched on up, a low level on CS is required prior to any sequence the rising edge of the clock input, while data on the SO being initiated. pin is updated after the falling edge of the clock input. 2.2 Serial Output (SO) 2.6 Hold (HOLD) The SO pin is used to transfer data out of the 25XX128. The HOLD pin is used to suspend transmission to the During a read cycle, data is shifted out on this pin after 25XX128 while in the middle of a serial sequence with- the falling edge of the serial clock. out having to retransmit the entire sequence again. It must be held high any time this function is not being 2.3 Write-Protect (WP) used. Once the device is selected and a serial This pin is used in conjunction with the WPEN bit in the sequence is underway, the HOLD pin may be pulled STATUS register to prohibit writes to the nonvolatile low to pause further serial communication without bits in the STATUS register. When WP is low and resetting the serial sequence. The HOLD pin must be WPEN is high, writing to the nonvolatile bits in the brought low while SCK is low, otherwise the HOLD STATUS register is disabled. All other operations function will not be invoked until the next SCK high-to- function normally. When WP is high, all functions, low transition. The 25XX128 must remain selected including writes to the nonvolatile bits in the STATUS during this sequence. The SI, SCK and SO pins are in register, operate normally. If the WPEN bit is set, WP a high-impedance state during the time the device is low during a STATUS register write sequence will dis- paused and transitions on these pins will be ignored. To able writing to the STATUS register. If an internal write resume serial communication, HOLD must be brought cycle has already begun, WP going low will have no high while the SCK pin is low, otherwise serial effect on the write. communication will not resume. Lowering the HOLD line at any time will tri-state the SO line. The WP pin function is blocked when the WPEN bit in the STATUS register is low. This allows the user to install the 25XX128 in a system with WP pin grounded and still be able to write to the STATUS register.  2003-2019 Microchip Technology Inc. DS20001831F-page 6

25AA128/25LC128 3.0 FUNCTIONAL DESCRIPTION 3.3 Write Sequence Prior to any attempt to write data to the 25AA128/ 3.1 Principles of Operation 25LC128, the write enable latch must be set by issuing the WREN instruction (Figure3-4). This is done by set- The 25AA128/25LC128 is a 16,384 byte Serial ting CS low and then clocking out the proper instruction EEPROM designed to interface directly with the Serial into the 25AA128/25LC128. After all eight bits of the Peripheral Interface (SPI) port of many of today’s pop- instruction are transmitted, the CS must be brought ular microcontroller families, including Microchip’s PIC® microcontrollers. It may also interface with micro- high to set the write enable latch. If the write operation is initiated immediately after the WREN instruction with- controllers that do not have a built-in SPI port by using out CS being brought high, the data will not be written discrete I/O lines programmed properly in firmware to to the array because the write enable latch will not have match the SPI protocol. been properly set. The 25AA128/25LC128 contains an 8-bit instruction Once the write enable latch is set, the user may register. The device is accessed via the SI pin, with proceed by setting the CS low, issuing a WRITE data being clocked in on the rising edge of SCK. The instruction, followed by the 16-bit address, with two CS pin must be low and the HOLD pin must be high for MSBs of the address being “don’t care” bits, and then the entire operation. the data to be written. Up to 64 bytes of data can be Table3-1 contains a list of the possible instruction sent to the device before a write cycle is necessary. bytes and format for device operation. All instructions, The only restriction is that all of the bytes must reside addresses and data are transferred MSB first, LSB last. in the same page. Data (SI) is sampled on the first rising edge of SCK Note: Page write operations are limited to after CS goes low. If the clock line is shared with other writing bytes within a single physical page, peripheral devices on the SPI bus, the user can assert regardless of the number of bytes the HOLD input and place the 25AA128/25LC128 in actually being written. Physical page ‘HOLD’ mode. After releasing the HOLD pin, operation boundaries start at addresses that are will resume from the point when the HOLD was integer multiples of the page buffer size asserted. (or ‘page size’) and, end at addresses that are integer multiples of page size – 1. If a 3.2 Read Sequence Page Write command attempts to write across a physical page boundary, the The device is selected by pulling CS low. The 8-bit result is that the data wraps around to the READ instruction is transmitted to the 25AA128/ beginning of the current page (overwriting 25LC128 followed by the 16-bit address, with two data previously stored there), instead of MSBs of the address being “don’t care” bits. After the being written to the next page as might be correct READ instruction and address are sent, the data expected. It is therefore necessary for the stored in the memory at the selected address is shifted application software to prevent page write out on the SO pin. The data stored in the memory at the operations that would attempt to cross a next address can be read sequentially by continuing to page boundary. provide clock pulses. The internal Address Pointer is automatically incremented to the next higher address after each byte of data is shifted out. When the highest For the data to be actually written to the array, the CS address is reached (3FFFh), the address counter rolls must be brought high after the Least Significant bit (D0) over to address 0000h, allowing the read cycle to be of the nth data byte has been clocked in. If CS is continued indefinitely. The read operation is terminated brought high at any other time, the write operation will by raising the CS pin (Figure3-1). not be completed. Refer to Figure3-2 and Figure3-3 for more detailed illustrations on the byte write sequence and the page write sequence, respectively. While the write is in progress, the STATUS register may be read to check the status of the Write-in-Process (WIP) bit (Figure3-6). A read attempt of a memory array location will not be possible during a write cycle. When the write cycle is completed, the write enable latch is reset.  2003-2019 Microchip Technology Inc. DS20001831F-page 7

25AA128/25LC128 BLOCK DIAGRAM STATUS HV Generator Register EEPROM I/O Control Memory X Array Control Logic Logic Dec Page Latches SI SO Y Decoder CS SCK Sense Amp. HOLD R/W Control WP VCC VSS TABLE 3-1: INSTRUCTION SET Instruction Name Instruction Format Description READ 0000 0011 Read data from memory array beginning at selected address WRITE 0000 0010 Write data to memory array beginning at selected address WRDI 0000 0100 Reset the write enable latch (disable write operations) WREN 0000 0110 Set the write enable latch (enable write operations) RDSR 0000 0101 Read STATUS register WRSR 0000 0001 Write STATUS register FIGURE 3-1: READ SEQUENCE CS 0 1 2 3 4 5 6 7 8 9 10 11 21 22 23 24 25 26 27 28 29 30 31 SCK Instruction 16-bit Address SI 0 0 0 0 0 0 1 1 15 14 13 12 2 1 0 Data Out High-Impedance SO 7 6 5 4 3 2 1 0  2003-2019 Microchip Technology Inc. DS20001831F-page 8

25AA128/25LC128 FIGURE 3-2: BYTE WRITE SEQUENCE CS Twc 0 1 2 3 4 5 6 7 8 9 10 11 21 22 23 24 25 26 27 28 29 30 31 SCK Instruction 16-bit Address Data Byte SI 0 0 0 0 0 0 1 0 15 14 13 12 2 1 0 7 6 5 4 3 2 1 0 High-Impedance SO FIGURE 3-3: PAGE WRITE SEQUENCE CS 0 1 2 3 4 5 6 7 8 9 10 11 21 22 23 24 25 26 27 28 29 30 31 SCK Instruction 16-bit Address Data Byte 1 SI 0 0 0 0 0 0 1 0 15 14 13 12 2 1 0 7 6 5 4 3 2 1 0 CS 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCK Data Byte 2 Data Byte 3 Data Byte n (64 max) SI 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0  2003-2019 Microchip Technology Inc. DS20001831F-page 9

25AA128/25LC128 3.4 Write Enable (WREN) and Write The following is a list of conditions under which the Disable (WRDI) write enable latch will be reset: • Power-up The 25AA128/25LC128 contains a write enable latch. • WRDI instruction successfully executed See Table3-2 for the write-protect functionality matrix. This latch must be set before any write operation will be • WRSR instruction successfully executed completed internally. The WREN instruction will set the • WRITE instruction successfully executed latch, and the WRDI will reset the latch. FIGURE 3-4: WRITE ENABLE SEQUENCE (WREN) CS 0 1 2 3 4 5 6 7 SCK SI 0 0 0 0 0 1 1 0 High-Impedance SO FIGURE 3-5: WRITE DISABLE SEQUENCE (WRDI) CS 0 1 2 3 4 5 6 7 SCK SI 0 0 0 0 0 1 0 0 High-Impedance SO  2003-2019 Microchip Technology Inc. DS20001831F-page 10

25AA128/25LC128 3.5 Read STATUS Register Instruction The Write Enable Latch (WEL) bit indicates the status (RDSR) of the write enable latch and is read-only. When set to a‘1’, the latch allows writes to the array, when set to a The Read STATUS Register instruction (RDSR) ‘0’, the latch prohibits writes to the array. The state of provides access to the STATUS register. The STATUS this bit can always be updated via the WREN or WRDI register may be read at any time, even during a write commands regardless of the state of write protection cycle. The STATUS register is formatted as follows: on the STATUS register. These commands are shown in Figure3-4 and Figure3-5. TABLE 3-2: STATUS REGISTER The Block Protection (BP0 and BP1) bits indicate 7 6 5 4 3 2 1 0 which blocks are currently write-protected. These bits are set by the user issuing the WRSR instruction. These W/R – – – W/R W/R R R bits are nonvolatile, and are shown in Table3-1. WPEN X X X BP1 BP0 WEL WIP See Figure3-6 for the RDSR timing sequence. Note: W/R = writable/readable. R = read-only. The Write-In-Process (WIP) bit indicates whether the 25AA128/25LC128 is busy with a write operation. When set to a ‘1’, a write is in progress, when set to a‘0’, no write is in progress. This bit is read-only. FIGURE 3-6: READ STATUS REGISTER TIMING SEQUENCE (RDSR) CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCK Instruction SI 0 0 0 0 0 1 0 1 Data from STATUS Register High-Impedance SO 7 6 5 4 3 2 1 0 Note: Bits 7-1 of the STATUS register are undetermined during a write cycle.  2003-2019 Microchip Technology Inc. DS20001831F-page 11

25AA128/25LC128 3.6 Write STATUS Register (WRSR) The Write STATUS Register (WRSR) instruction allows TABLE 3-1: ARRAY PROTECTION the user to write to the nonvolatile bits in the STATUS register as shown in Table3-2. The user is able to Array Addresses BP1 BP0 select one of four levels of protection for the array by Write-Protected writing to the appropriate bits in the STATUS register. 0 0 none The array is divided up into four segments. The user has the ability to write-protect none, one, two, or all four 0 1 upper 1/4 (3000h-3FFFh) of the segments of the array. The partitioning is con- trolled as shown in Table3-1. 1 0 upper 1/2 (2000h-3FFFh) The Write-Protect Enable (WPEN) bit is a nonvolatile bit that is available as an enable bit for the WP pin. The 1 1 all Write-Protect (WP) pin and the Write-Protect Enable (0000h-3FFFh) (WPEN) bit in the STATUS register control the programmable hardware write-protect feature. Hard- ware write protection is enabled when WP pin is low and the WPEN bit is high. Hardware write protection is disabled when either the WP pin is high or the WPEN bit is low. When the chip is hardware write-protected, only writes to nonvolatile bits in the STATUS register are disabled. See Table3-2 for a matrix of functionality on the WPEN bit. See Figure3-7 for the WRSR timing sequence. FIGURE 3-7: WRITE STATUS REGISTER TIMING SEQUENCE (WRSR) CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCK Instruction Data to STATUS Register SI 0 0 0 0 0 0 0 1 7 6 5 4 3 2 1 0 High-Impedance SO Note: An internal write cycle (TWC) is initiated on the rising edge of CS after a valid write STATUS register sequence.  2003-2019 Microchip Technology Inc. DS20001831F-page 12

25AA128/25LC128 3.7 Data Protection 3.8 Power-On State The following protection has been implemented to The 25AA128/25LC128 powers on in the following prevent inadvertent writes to the array: state: • The write enable latch is reset on power-up • The device is in low-power Standby mode • A write enable instruction must be issued to set (CS = 1) the write enable latch • The write enable latch is reset • After a byte write, page write or STATUS register • SO is in high-impedance state write, the write enable latch is reset • A high-to-low-level transition on CS is required to • CS must be set high after the proper number of enter active state clock cycles to start an internal write cycle • Access to the array during an internal write cycle is ignored and programming is continued TABLE 3-2: WRITE-PROTECT FUNCTIONALITY MATRIX WEL WPEN WP Protected Blocks Unprotected Blocks STATUS Register (SR bit 1) (SR bit 7) (pin 3) 0 x x Protected Protected Protected 1 0 x Protected Writable Writable 1 1 0 (low) Protected Writable Protected 1 1 1 (high) Protected Writable Writable Note: x = don’t care  2003-2019 Microchip Technology Inc. DS20001831F-page 13

25AA128/25LC128 4.0 PACKAGING INFORMATION 4.1 Package Marking Information 8-Lead DFN-S Example XXXXXXX 25LC128 T/XXXXX I/MF e 3 YYWW 1934 NNN 13F 8-Lead PDIP (300 mil) Example XXXXXXX 25AA128 T/XXXNNN I/P e 3 13F YYWW 1934 8-Lead SOIC (3.90 mm) Example XXXXXXXX 25LC128I XXXYYWW SN e 3 1934 NNN 13F 8-Lead SOIJ (5.28 mm) Example XXXXXXXX 25LC128 T/XXXXXXX I/SM e 3 YYWWNNN 193413F 8-Lead TSSOP Example XXXX 5LD TYYW I934 NNN 13F 1st Line Marking Codes Part DFN PDIP SOIC SOIJ TSSOP No. I-Temp. E-Temp. I-Temp. E-Temp. I-Temp. E-Temp. I-Temp. E-Temp. I-Temp. E-Temp. 25AA128 25AA128 — 25AA128 — 25AA128T(1) 25AA128T(1) 25AA128 — 5AD — 5ADX(2) — 25LC128 25LC128 25LC128 25LC128 25LC128 25LC128T(1) 25LC128T(1) 25AA128 25AA128 5LD 5LD 5LDX(3) 5LDX(3) Note 1: T = Temperature grade (I, E) 2: For 25AA128X 3: For 25LC128X  2003-2019 Microchip Technology Inc. DS20001831F-page 14

25AA128/25LC128 Legend: XX...X Part number or part number code T Temperature (I, E) Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code (2 characters for small packages) e3 JEDEC® designator for Matte Tin (Sn) * Standard OTP marking consists of Microchip part number, year code, week code and traceability code. Note: For very small packages with no room for the JEDEC® designator e 3 , the marking will only appear on the outer carton or reel label. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2003-2019 Microchip Technology Inc. DS20001831F-page 15

25AA128/25LC128 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)(cid:15)(cid:16)(cid:6)(cid:10)(cid:8)(cid:17)(cid:10)(cid:6)(cid:12)(cid:18)(cid:8)(cid:19)(cid:20)(cid:8)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:6)(cid:14)(cid:21)(cid:6)(cid:22)(cid:5)(cid:8)(cid:23)(cid:24)(cid:17)(cid:25)(cid:8)(cid:26)(cid:8)(cid:27)(cid:28)(cid:29)(cid:8)(cid:30)(cid:30)(cid:8)(cid:31)(cid:20)(cid:7) (cid:8)!(cid:15)(cid:17)(cid:19)(cid:3)"# (cid:19)(cid:20)(cid:12)(cid:5)$ 3(cid:22)(cid:21)(cid:14)&(cid:23)(cid:13)(cid:14)’(cid:22)!&(cid:14)(cid:20)"(cid:21)(cid:21)(cid:13)(cid:25)&(cid:14)(cid:10)(cid:11)(cid:20)+(cid:11)(cid:12)(cid:13)(cid:14)#(cid:21)(cid:11)*(cid:19)(cid:25)(cid:12)!((cid:14)(cid:10)(cid:26)(cid:13)(cid:11)!(cid:13)(cid:14)!(cid:13)(cid:13)(cid:14)&(cid:23)(cid:13)(cid:14)(cid:18)(cid:19)(cid:20)(cid:21)(cid:22)(cid:20)(cid:23)(cid:19)(cid:10)(cid:14)(cid:31)(cid:11)(cid:20)+(cid:11)(cid:12)(cid:19)(cid:25)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:20)(cid:19)%(cid:19)(cid:20)(cid:11)&(cid:19)(cid:22)(cid:25)(cid:14)(cid:26)(cid:22)(cid:20)(cid:11)&(cid:13)#(cid:14)(cid:11)&(cid:14) (cid:23)&&(cid:10)244***(cid:29)’(cid:19)(cid:20)(cid:21)(cid:22)(cid:20)(cid:23)(cid:19)(cid:10)(cid:29)(cid:20)(cid:22)’4(cid:10)(cid:11)(cid:20)+(cid:11)(cid:12)(cid:19)(cid:25)(cid:12) (cid:14) e D L b N N K E E2 EXPOSEDPAD NOTE1 NOTE1 1 2 2 1 D2 TOPVIEW BOTTOMVIEW A A3 A1 NOTE2 5(cid:25)(cid:19)&! (cid:18)(cid:28)66(cid:28)(cid:18)-(cid:24)-(cid:8)(cid:3) (cid:2)(cid:19)’(cid:13)(cid:25)!(cid:19)(cid:22)(cid:25)(cid:14)6(cid:19)’(cid:19)&! (cid:18)(cid:28)7 78(cid:18) (cid:18)(cid:7)9 7"’)(cid:13)(cid:21)(cid:14)(cid:22)%(cid:14)(cid:31)(cid:19)(cid:25)! 7 : (cid:31)(cid:19)&(cid:20)(cid:23) (cid:13) (cid:30)(cid:29)(cid:16)(cid:17)(cid:14)0(cid:3)1 8 (cid:13)(cid:21)(cid:11)(cid:26)(cid:26)(cid:14);(cid:13)(cid:19)(cid:12)(cid:23)& (cid:7) (cid:4)(cid:29):(cid:4) (cid:4)(cid:29):/ (cid:30)(cid:29)(cid:4)(cid:4) (cid:3)&(cid:11)(cid:25)#(cid:22)%%(cid:14) (cid:7)(cid:30) (cid:4)(cid:29)(cid:4)(cid:4) (cid:4)(cid:29)(cid:4)(cid:30) (cid:4)(cid:29)(cid:4)/ 1(cid:22)(cid:25)&(cid:11)(cid:20)&(cid:14)(cid:24)(cid:23)(cid:19)(cid:20)+(cid:25)(cid:13)!! (cid:7), (cid:4)(cid:29)(cid:16)(cid:4)(cid:14)(cid:8)-3 8 (cid:13)(cid:21)(cid:11)(cid:26)(cid:26)(cid:14)6(cid:13)(cid:25)(cid:12)&(cid:23) (cid:2) /(cid:29)(cid:4)(cid:4)(cid:14)0(cid:3)1 8 (cid:13)(cid:21)(cid:11)(cid:26)(cid:26)(cid:14)<(cid:19)#&(cid:23) - (cid:15)(cid:29)(cid:4)(cid:4)(cid:14)0(cid:3)1 -$(cid:10)(cid:22)!(cid:13)#(cid:14)(cid:31)(cid:11)#(cid:14)6(cid:13)(cid:25)(cid:12)&(cid:23) (cid:2)(cid:16) ,(cid:29)(cid:6)(cid:4) (cid:5)(cid:29)(cid:4)(cid:4) (cid:5)(cid:29)(cid:30)(cid:4) -$(cid:10)(cid:22)!(cid:13)#(cid:14)(cid:31)(cid:11)#(cid:14)<(cid:19)#&(cid:23) -(cid:16) (cid:16)(cid:29)(cid:16)(cid:4) (cid:16)(cid:29),(cid:4) (cid:16)(cid:29)(cid:5)(cid:4) 1(cid:22)(cid:25)&(cid:11)(cid:20)&(cid:14)<(cid:19)#&(cid:23) ) (cid:4)(cid:29),/ (cid:4)(cid:29)(cid:5)(cid:4) (cid:4)(cid:29)(cid:5): 1(cid:22)(cid:25)&(cid:11)(cid:20)&(cid:14)6(cid:13)(cid:25)(cid:12)&(cid:23) 6 (cid:4)(cid:29)/(cid:4) (cid:4)(cid:29)(cid:15)(cid:4) (cid:4)(cid:29)(cid:17)/ 1(cid:22)(cid:25)&(cid:11)(cid:20)&(cid:9)&(cid:22)(cid:9)-$(cid:10)(cid:22)!(cid:13)#(cid:14)(cid:31)(cid:11)# = (cid:4)(cid:29)(cid:16)(cid:4) > > (cid:19)(cid:20)(cid:12)(cid:5)(cid:11)$ (cid:30)(cid:29) (cid:31)(cid:19)(cid:25)(cid:14)(cid:30)(cid:14) (cid:19)!"(cid:11)(cid:26)(cid:14)(cid:19)(cid:25)#(cid:13)$(cid:14)%(cid:13)(cid:11)&"(cid:21)(cid:13)(cid:14)’(cid:11)(cid:27)(cid:14) (cid:11)(cid:21)(cid:27)((cid:14))"&(cid:14)’"!&(cid:14))(cid:13)(cid:14)(cid:26)(cid:22)(cid:20)(cid:11)&(cid:13)#(cid:14)*(cid:19)&(cid:23)(cid:19)(cid:25)(cid:14)&(cid:23)(cid:13)(cid:14)(cid:23)(cid:11)&(cid:20)(cid:23)(cid:13)#(cid:14)(cid:11)(cid:21)(cid:13)(cid:11)(cid:29) (cid:16)(cid:29) (cid:31)(cid:11)(cid:20)+(cid:11)(cid:12)(cid:13)(cid:14)’(cid:11)(cid:27)(cid:14)(cid:23)(cid:11) (cid:13)(cid:14)(cid:22)(cid:25)(cid:13)(cid:14)(cid:22)(cid:21)(cid:14)’(cid:22)(cid:21)(cid:13)(cid:14)(cid:13)$(cid:10)(cid:22)!(cid:13)#(cid:14)&(cid:19)(cid:13)(cid:14))(cid:11)(cid:21)!(cid:14)(cid:11)&(cid:14)(cid:13)(cid:25)#!(cid:29) ,(cid:29) (cid:31)(cid:11)(cid:20)+(cid:11)(cid:12)(cid:13)(cid:14)(cid:19)!(cid:14)!(cid:11)*(cid:14)!(cid:19)(cid:25)(cid:12)"(cid:26)(cid:11)&(cid:13)#(cid:29) (cid:5)(cid:29) (cid:2)(cid:19)’(cid:13)(cid:25)!(cid:19)(cid:22)(cid:25)(cid:19)(cid:25)(cid:12)(cid:14)(cid:11)(cid:25)#(cid:14)&(cid:22)(cid:26)(cid:13)(cid:21)(cid:11)(cid:25)(cid:20)(cid:19)(cid:25)(cid:12)(cid:14)(cid:10)(cid:13)(cid:21)(cid:14)(cid:7)(cid:3)(cid:18)-(cid:14).(cid:30)(cid:5)(cid:29)/(cid:18)(cid:29) 0(cid:3)12 0(cid:11)!(cid:19)(cid:20)(cid:14)(cid:2)(cid:19)’(cid:13)(cid:25)!(cid:19)(cid:22)(cid:25)(cid:29)(cid:14)(cid:24)(cid:23)(cid:13)(cid:22)(cid:21)(cid:13)&(cid:19)(cid:20)(cid:11)(cid:26)(cid:26)(cid:27)(cid:14)(cid:13)$(cid:11)(cid:20)&(cid:14) (cid:11)(cid:26)"(cid:13)(cid:14)!(cid:23)(cid:22)*(cid:25)(cid:14)*(cid:19)&(cid:23)(cid:22)"&(cid:14)&(cid:22)(cid:26)(cid:13)(cid:21)(cid:11)(cid:25)(cid:20)(cid:13)!(cid:29) (cid:8)-32 (cid:8)(cid:13)%(cid:13)(cid:21)(cid:13)(cid:25)(cid:20)(cid:13)(cid:14)(cid:2)(cid:19)’(cid:13)(cid:25)!(cid:19)(cid:22)(cid:25)((cid:14)"!"(cid:11)(cid:26)(cid:26)(cid:27)(cid:14)*(cid:19)&(cid:23)(cid:22)"&(cid:14)&(cid:22)(cid:26)(cid:13)(cid:21)(cid:11)(cid:25)(cid:20)(cid:13)((cid:14)%(cid:22)(cid:21)(cid:14)(cid:19)(cid:25)%(cid:22)(cid:21)’(cid:11)&(cid:19)(cid:22)(cid:25)(cid:14)(cid:10)"(cid:21)(cid:10)(cid:22)!(cid:13)!(cid:14)(cid:22)(cid:25)(cid:26)(cid:27)(cid:29) (cid:18)(cid:19)(cid:20)(cid:21)(cid:22)(cid:20)(cid:23)(cid:19)(cid:10)(cid:24)(cid:13)(cid:20)(cid:23)(cid:25)(cid:22)(cid:26)(cid:22)(cid:12)(cid:27)(cid:2)(cid:21)(cid:11)*(cid:19)(cid:25)(cid:12)1(cid:4)(cid:5)(cid:9)(cid:30)(cid:16)(cid:16)0  2003-2019 Microchip Technology Inc. DS20001831F-page 16

25AA128/25LC128 (cid:19)(cid:20)(cid:12)(cid:5)$ 3(cid:22)(cid:21)(cid:14)&(cid:23)(cid:13)(cid:14)’(cid:22)!&(cid:14)(cid:20)"(cid:21)(cid:21)(cid:13)(cid:25)&(cid:14)(cid:10)(cid:11)(cid:20)+(cid:11)(cid:12)(cid:13)(cid:14)#(cid:21)(cid:11)*(cid:19)(cid:25)(cid:12)!((cid:14)(cid:10)(cid:26)(cid:13)(cid:11)!(cid:13)(cid:14)!(cid:13)(cid:13)(cid:14)&(cid:23)(cid:13)(cid:14)(cid:18)(cid:19)(cid:20)(cid:21)(cid:22)(cid:20)(cid:23)(cid:19)(cid:10)(cid:14)(cid:31)(cid:11)(cid:20)+(cid:11)(cid:12)(cid:19)(cid:25)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:20)(cid:19)%(cid:19)(cid:20)(cid:11)&(cid:19)(cid:22)(cid:25)(cid:14)(cid:26)(cid:22)(cid:20)(cid:11)&(cid:13)#(cid:14)(cid:11)&(cid:14) (cid:23)&&(cid:10)244***(cid:29)’(cid:19)(cid:20)(cid:21)(cid:22)(cid:20)(cid:23)(cid:19)(cid:10)(cid:29)(cid:20)(cid:22)’4(cid:10)(cid:11)(cid:20)+(cid:11)(cid:12)(cid:19)(cid:25)(cid:12)  2003-2019 Microchip Technology Inc. DS20001831F-page 17

25AA128/25LC128 8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D A N B E1 NOTE 1 1 2 TOP VIEW E C A A2 PLANE L c A1 e eB 8X b1 8X b .010 C SIDE VIEW END VIEW Microchip Technology Drawing No. C04-018-P Rev E Sheet 1 of 2  2003-2019 Microchip Technology Inc. DS20001831F-page 18

25AA128/25LC128 8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging ALTERNATE LEAD DESIGN (NOTE 5) DATUM A DATUM A b b e e 2 2 e e Units INCHES Dimension Limits MIN NOM MAX Number of Pins N 8 Pitch e .100 BSC Top to Seating Plane A - - .210 Molded Package Thickness A2 .115 .130 .195 Base to Seating Plane A1 .015 - - Shoulder to Shoulder Width E .290 .310 .325 Molded Package Width E1 .240 .250 .280 Overall Length D .348 .365 .400 Tip to Seating Plane L .115 .130 .150 Lead Thickness c .008 .010 .015 Upper Lead Width b1 .040 .060 .070 Lower Lead Width b .014 .018 .022 Overall Row Spacing § eB - - .430 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side. 4. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. 5. Lead design above seating plane may vary, based on assembly vendor. Microchip Technology Drawing No. C04-018-P Rev E Sheet 2 of 2  2003-2019 Microchip Technology Inc. DS20001831F-page 19

25AA128/25LC128 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2X 0.10 C A–B D A D NOTE 5 N E 2 E1 2 E1 E NOTE 1 1 2 e NX b B 0.25 C A–B D NOTE 5 TOP VIEW 0.10 C C A A2 SEATING PLANE 8X 0.10 C A1 SIDE VIEW h R0.13 h R0.13 H 0.23 L SEE VIEW C (L1) VIEW A–A VIEW C Microchip Technology Drawing No. C04-057-SN Rev D Sheet 1 of 2  2003-2019 Microchip Technology Inc. DS20001831F-page 20

25AA128/25LC128 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Pins N 8 Pitch e 1.27 BSC Overall Height A - - 1.75 Molded Package Thickness A2 1.25 - - Standoff § A1 0.10 - 0.25 Overall Width E 6.00 BSC Molded Package Width E1 3.90 BSC Overall Length D 4.90 BSC Chamfer (Optional) h 0.25 - 0.50 Foot Length L 0.40 - 1.27 Footprint L1 1.04 REF Foot Angle 0° - 8° Lead Thickness c 0.17 - 0.25 Lead Width b 0.31 - 0.51 Mold Draft Angle Top 5° - 15° Mold Draft Angle Bottom 5° - 15° Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. 5. Datums A & B to be determined at Datum H. Microchip Technology Drawing No. C04-057-SN Rev D Sheet 2 of 2  2003-2019 Microchip Technology Inc. DS20001831F-page 21

25AA128/25LC128 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging SILK SCREEN C Y1 X1 E RECOMMENDED LAND PATTERN Units MILLIMETERS Dimension Limits MIN NOM MAX Contact Pitch E 1.27 BSC Contact Pad Spacing C 5.40 Contact Pad Width (X8) X1 0.60 Contact Pad Length (X8) Y1 1.55 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing C04-2057-SN Rev B  2003-2019 Microchip Technology Inc. DS20001831F-page 22

25AA128/25LC128 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2003-2019 Microchip Technology Inc. DS20001831F-page 23

25AA128/25LC128 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2003-2019 Microchip Technology Inc. DS20001831F-page 24

25AA128/25LC128 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2003-2019 Microchip Technology Inc. DS20001831F-page 25

25AA128/25LC128 8-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm Body [TSSOP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D N E E1 NOTE 1 1 2 b e c φ A A2 A1 L1 L Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Pins N 8 Pitch e 0.65 BSC Overall Height A – – 1.20 Molded Package Thickness A2 0.80 1.00 1.05 Standoff A1 0.05 – 0.15 Overall Width E 6.40 BSC Molded Package Width E1 4.30 4.40 4.50 Molded Package Length D 2.90 3.00 3.10 Foot Length L 0.45 0.60 0.75 Footprint L1 1.00 REF Foot Angle φ 0° – 8° Lead Thickness c 0.09 – 0.20 Lead Width b 0.19 – 0.30 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side. 3. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. MicrochipTechnologyDrawingC04-086B  2003-2019 Microchip Technology Inc. DS20001831F-page 26

25AA128/25LC128 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2003-2019 Microchip Technology Inc. DS20001831F-page 27

25AA128/25LC128 APPENDIX A: REVISION HISTORY Revision F (08/2019) Updated content throughout for clarification. Update 8L PDIP Package Drawing. Revision E (07/2011) Added SOIJ (SM) package. Revision D (06/2009) Added X-Rotated TSSOP to package types; Revised Table 1-2, Param. 21; Revised Table 3-1; Revised TSSOP Line Marking table; Added SOIC Land Pattern; Revised Product ID section. Revision C (05/2007) Removed Preliminary status; Revised Table 1-2, Para. 7 and 8; Revised Table 1-3, CL; Revised trademarks; Replaced Package drawings (Rev. AP); Replaced On- Line Support; Revised Product ID section. Revision B (12/2003) Corrections to Section 1.0, Electrical Characteristics. Revision A(09/2003) Initial release of this document.  2003-2019 Microchip Technology Inc. DS20001831F-page 28

25AA128/25LC128 THE MICROCHIP WEBSITE CUSTOMER SUPPORT Microchip provides online support via our website at Users of Microchip products can receive assistance www.microchip.com. This website is used as a means through several channels: to make files and information easily available to • Distributor or Representative customers. Accessible by using your favorite Internet • Local Sales Office browser, the website contains the following information: • Field Application Engineer (FAE) • Product Support – Data sheets and errata, appli- • Technical Support cation notes and sample programs, design resources, user’s guides and hardware support Customers should contact their distributor, representa- documents, latest software releases and archived tive or Field Application Engineer (FAE) for support. software Local sales offices are also available to help custom- ers. A listing of sales offices and locations is included in • General Technical Support – Frequently Asked the back of this document. Questions (FAQ), technical support requests, online discussion groups, Microchip consultant Technical support is available through the website program member listing at: http://microchip.com/support • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Micro- chip sales offices, distributors and factory repre- sentatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a spec- ified product family or development tool of interest. To register, access the Microchip website at www.microchip.com. Under “Support”, click on “Cus- tomer Change Notification” and follow the registra- tion instructions.  2003-2019 Microchip Technology Inc. DS20001831F-page 29

25AA128/25LC128 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. (1) Examples: PART NO. [X] -X /XX a)25AA128T-I/SN: Tape and Reel, Industrial Device Tape and Reel Temperature Package Temp., 1.8V, SOIC package. Option Range b)25AA128T-I/ST: Tape and Reel, Industrial Temp., 1.8V, TSSOP package. Device: 25AA128: 128-Kbit, 1.8V,SPI Serial EEPROM c)25LC128-I/P: Industrial Temp., 2.5V, PDIP 25LC128: 128-Kbit, 2.5V, SPI Serial EEPROM package. 25AA128X: 128-Kbit, 1.8V, SPI Serial EEPROM in alternate pinout (ST only) d)25LC128T-E/MF: Tape and Reel, Extended 25LC128X: 128-Kbit, 2.5V, SPI Serial EEPROM in Temp., 2.5V, DFN package. alternate pinout (ST only) e)25LC128XT-I/ST: Tape and Reel, Industrial Temp., 2.5V, Rotated pinout, TSSOP package. Tape and Reel Blank = Standard packaging (tube or tray) Option: T = Tape and Reel(1) Temperature I = -40C to +85C (Industrial) Range: E = -40C to +125C (Extended) Package: MF = Plastic Dual Flat, No Lead Package – 5x6x0.85mm Body, 8-lead (DFN-S) Note 1: Tape and Reel identifier only appears P = Plastic Dual In-Line – 300 mil Body, 8-lead in the catalog part number description. (PDIP) This identifier is used for ordering pur- SN = Plastic Small Outline - Narrow, 3.90 mm poses and is not printed on the device Body, 8-lead (SOIC) package. Check with your Microchip SM = Plastic Small Outline - Medium, 5.28 mm Sales Office for package availability Body, 8-lead (SOIJ) with the Tape and Reel option. ST = Plastic Thin Shrink Small Outline – 4.4mm, 2: Contact Microchip for Automotive 8-lead (TSSOP) grade ordering part numbers.  2003-2019 Microchip Technology Inc. DS20001831F-page 30

25AA128/25LC128 Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, Adaptec, and may be superseded by updates. It is your responsibility to AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, chipKIT, ensure that your application meets with your specifications. chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck, MICROCHIP MAKES NO REPRESENTATIONS OR LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi, WARRANTIES OF ANY KIND WHETHER EXPRESS OR Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer, IMPLIED, WRITTEN OR ORAL, STATUTORY OR PackeTime, PIC, picoPower, PICSTART, PIC32 logo, PolarFire, OTHERWISE, RELATED TO THE INFORMATION, Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST, INCLUDING BUT NOT LIMITED TO ITS CONDITION, SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon, TempTrackr, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA QUALITY, PERFORMANCE, MERCHANTABILITY OR are registered trademarks of Microchip Technology Incorporated in FITNESS FOR PURPOSE. Microchip disclaims all liability the U.S.A. and other countries. arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at APT, ClockWorks, The Embedded Control Solutions Company, the buyer’s risk, and the buyer agrees to defend, indemnify and EtherSynch, FlashTec, Hyper Speed Control, HyperLight Load, IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision hold harmless Microchip from any and all damages, claims, Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-Wire, suits, or expenses resulting from such use. No licenses are SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub, conveyed, implicitly or otherwise, under any Microchip TimePictra, TimeProvider, Vite, WinPath, and ZL are registered intellectual property rights unless otherwise stated. trademarks of Microchip Technology Incorporated in the U.S.A. Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BlueSky, BodyCom, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, memBrain, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. The Adaptec logo, Frequency on Demand, Silicon Storage Technology, and Symmcom are registered trademarks of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2003-2019, Microchip Technology Incorporated, All Rights Reserved. For information regarding Microchip’s Quality Management Systems, please visit www.microchip.com/quality. ISBN: 978-1-5224-4947-8  2003-2019 Microchip Technology Inc. DS20001831F-page 31

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