25AA1024 1 Mbit SPI Bus Serial EEPROM Device Selection Table Part Number VCC Range Page Size Temp. Ranges Packages 25AA1024 1.8-5.5V 256 Byte I P, SM, MF Features Description • 20MHz Maximum Clock Speed The Microchip Technology Inc. 25AA1024 is a • Byte and Page-level Write Operations: 1024Kbit serial EEPROM memory with byte-level and - 256 byte page page-level serial EEPROM functions. It also features - 6ms maximum write cycle time Page, Sector and Chip erase functions typically - No page or sector erase required associated with Flash-based products. These functions • Low-Power CMOS Technology: are not required for byte or page write operations. The - Maximum Write current: 7mA at 5.5V memory is accessed via a simple Serial Peripheral - Maximum Read current: 10mA at 5.5V, Interface (SPI) compatible serial bus. The bus signals 20MHz required are a clock input (SCK) plus separate data in - Standby current: 1µA at 2.5V, 85°C (SI) and data out (SO) lines. Access to the device is (Deep Power-down) controlled by a Chip Select (CS) input. • Electronic Signature for Device ID Communication to the device can be paused via the • Self-Timed Erase and Write Cycles: hold pin (HOLD). While the device is paused, - Page Erase (6ms maximum) transitions on its inputs will be ignored, with the - Sector Erase (10ms maximum) exception of Chip Select, allowing the host to service - Chip Erase (10ms maximum) higher priority interrupts. • Sector Write Protection (32K byte/sector): - Protect none, 1/4, 1/2 or all of array The 25AA1024 is available in standard packages including 8-lead PDIP and SOIJ, and advanced 8-lead • Built-in Write Protection: DFN package. All devices are RoHS compliant. - Power-on/off data protection circuitry - Write enable latch - Write-protect pin Package Types (not to scale) • High Reliability: - Endurance: 1M erase/write cycles DFN PDIP/SOIJ - Data Retention: >200years (MF) (P, SM) - ESD Protection: 4000V CS 1 8 VCC • Temperature Ranges Supported: 24 CS 1 4 8 VCC SO 2 0 7 HOLD 2 - Industrial (I):-40°C to +85°C A1 SO 2 10 7 HOLD • RoHS Compliant WP 3 5A 6 SCK WP 3 AA 6 SCK VSS 4 2 5 SI VSS 4 25 5 SI Pin Function Table Name Function CS Chip Select Input SO Serial Data Output WP Write-Protect VSS Ground SI Serial Data Input SCK Serial Clock Input HOLD Hold Input VCC Supply Voltage  2007-2015 Microchip Technology Inc. DS20001836J-page 1

25AA1024 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings (†) VCC.............................................................................................................................................................................6.5V All inputs and outputs w.r.t. VSS.........................................................................................................-0.6V to VCC +1.0V Storage temperature.................................................................................................................................-65°C to 150°C Ambient temperature under bias...............................................................................................................-40°C to 125°C ESD protection on all pins..........................................................................................................................................4kV † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an extended period of time may affect device reliability. TABLE 1-1: DC CHARACTERISTICS Industrial (I)*: TA=0°C to +85°C VCC=1.8V to 5.5V DC CHARACTERISTICS Industrial (I): TA=-40°C to +85°C VCC=2.0V to 5.5V * Limited industrial temperature range. Param. Sym. Characteristic Min. Max. Units Test Conditions No. D001 VIH1 High-level Input 0.7 VCC VCC +1 V Voltage D002 VIL1 Low-level Input -0.3 0.3 VCC V VCC≥ 2.7V D003 VIL2 Voltage -0.3 0.2 VCC V VCC < 2.7V D004 VOL Low-level Output — 0.4 V IOL = 2.1mA D005 VOL Voltage — 0.2 V IOL = 1.0mA, VCC<2.5V D006 VOH High-level Output VCC -0.2 — V IOH = -400µA Voltage D007 ILI Input Leakage — ±1 µA CS = VCC, VIN = VSS or VCC Current D008 ILO Output Leakage — ±1 µA CS = VCC, VOUT = VSS or VCC Current D009 CINT Internal Capacitance — 7 pF TA = 25°C, CLK = 1.0MHz, (all inputs and VCC = 5.0V (Note) outputs) D010 ICCREAD — 10 mA VCC = 5.5V; FCLK = 20.0MHz; SO = Open — 5 mA VCC = 2.5V; FCLK = 10.0MHz; Operating Current SO = Open D011 ICCWRITE — 7 mA VCC = 5.5V — 5 mA VCC = 2.5V D012 ICCS Standby Current — 12 A CS = VCC = 5.5V, Inputs tied to VCC or VSS, 85°C D013 ICCSPD Deep Power-down — 1 µA CS = VCC = 2.5V, Inputs tied to VCC or Current VSS, 85°C Note: This parameter is periodically sampled and not 100% tested. DS20001836J-page 2  2007-2015 Microchip Technology Inc.

25AA1024 TABLE 1-2: AC CHARACTERISTICS Industrial (I)*: TA = 0°C to +85°C VCC = 1.8V to 5.5V AC CHARACTERISTICS Industrial (I): TA = -40°C to +85°C VCC = 2.0V to 5.5V *Limited industrial temperature range. Param. Sym. Characteristic Min. Max. Units Conditions No. 1 FCLK Clock Frequency — 20 MHz 4.5≤VCC≤5.5 — 10 MHz 2.5≤VCC<4.5 — 2 MHz 2.0≤VCC<2.5 1.8≤VCC<2.0, 0°C to +85°C 2 TCSS CS Setup Time 25 — ns 4.5≤VCC≤5.5 50 — ns 2.5≤VCC<4.5 250 — ns 2.0≤VCC<2.5 1.8≤VCC<2.0, 0°C to +85°C 3 TCSH CS Hold Time 50 — ns 4.5≤VCC≤5.5 100 — ns 2.5≤VCC<4.5 500 — ns 2.0≤VCC<2.5 1.8≤VCC<2.0, 0°C to +85°C (Note3) 4 TCSD CS Disable Time 50 — ns 5 TSU Data Setup Time 5 — ns 4.5≤VCC≤5.5 10 — ns 2.5≤VCC<4.5 50 — ns 2.0≤VCC<2.5 1.8≤VCC<2.0, 0°C to +85°C 6 THD Data Hold Time 10 — ns 4.5≤VCC≤5.5 20 — ns 2.5≤VCC<4.5 100 — ns 2.0≤VCC<2.5 1.8≤VCC<2.0, 0°C to +85°C 7 TR CLK Rise Time — 20 ns (Note1) 8 TF CLK Fall Time — 20 ns (Note1) 9 THI Clock High Time 25 — 4.5≤VCC≤5.5 50 — ns 2.5≤VCC<4.5 250 — ns 2.0≤VCC<2.5 1.8≤VCC<2.0, 0°C to +85°C 10 TLO Clock Low Time 25 — ns 4.5≤VCC≤5.5 50 — ns 2.5≤VCC<4.5 250 — ns 2.0≤VCC<2.5 1.8≤VCC<2.0, 0°C to +85°C 11 TCLD Clock Delay Time 50 — ns 12 TCLE Clock Enable Time 50 — ns 13 TV Output Valid from Clock — 25 ns 4.5≤VCC≤5.5 Low — 50 ns 2.5≤VCC<4.5 — 250 ns 2.0≤VCC<2.5 1.8≤VCC<2.0, 0°C to +85°C Note1: This parameter is periodically sampled and not 100% tested. 2: This parameter is not tested but established by characterization and qualification. For endurance estimates in a specific application, please consult the Total Endurance™ Model which can be obtained from Microchip’s web site at www.microchip.com. 3: Includes THI time.  2007-2015 Microchip Technology Inc. DS20001836J-page 3

25AA1024 TABLE 1-2: AC CHARACTERISTICS (CONTINUED) Industrial (I)*: TA = 0°C to +85°C VCC = 1.8V to 5.5V AC CHARACTERISTICS Industrial (I): TA = -40°C to +85°C VCC = 2.0V to 5.5V *Limited industrial temperature range. Param. Sym. Characteristic Min. Max. Units Conditions No. 14 THO Output Hold Time 0 — ns (Note1) 15 TDIS Output Disable Time — 25 ns 4.5≤VCC≤5.5 — 50 ns 2.5≤VCC<4.5 — 250 ns 2.0≤VCC<2.5 1.8≤VCC<2.0, 0°C to +85°C (Note1) 16 THS HOLD Setup Time 10 — ns 4.5≤VCC≤5.5 20 — ns 2.5≤VCC<4.5 100 — ns 2.0≤VCC<2.5 1.8≤VCC<2.0, 0°C to +85°C 17 THH HOLD Hold Time 10 — ns 4.5≤VCC≤5.5 20 — ns 2.5≤VCC<4.5 100 — ns 2.0≤VCC<2.5 1.8≤VCC<2.0, 0°C to +85°C 18 THZ HOLD Low to Output 15 — ns 4.5≤VCC≤5.5 High Z 30 — ns 2.5≤VCC<4.5 150 — ns 2.0≤VCC<2.5 1.8≤VCC<2.0, 0°C to +85°C (Note1) 19 THV HOLD High to Output 15 — ns 4.5≤VCC≤5.5 Valid 30 — ns 2.5≤VCC<4.5 150 — ns 2.0≤VCC<2.5 1.8≤VCC<2.0, 0°C to +85°C 20 TREL CS High to Standby mode — 100 µs VCC = 1.8V to 5.5V 21 TPD CS High to Deep — 100 µs VCC = 1.8V to 5.5V Power-down 22 TCE Chip Erase Cycle Time — 10 ms VCC = 1.8V to 5.5V 23 TSE Sector Erase Cycle Time — 10 ms VCC = 1.8V to 5.5V 24 TWC Internal Write Cycle Time — 6 ms Byte or Page mode and Page Erase 25 — Endurance 1M — E/W Page mode, 25°C, 5.5V (Note2) cycles Note1: This parameter is periodically sampled and not 100% tested. 2: This parameter is not tested but established by characterization and qualification. For endurance estimates in a specific application, please consult the Total Endurance™ Model which can be obtained from Microchip’s web site at www.microchip.com. 3: Includes THI time. DS20001836J-page 4  2007-2015 Microchip Technology Inc.

25AA1024 TABLE 1-3: AC TEST CONDITIONS AC Waveform VLO = 0.2V — VHI = VCC - 0.2V (Note1) VHI = 4.0V (Note2) CL = 30 pF — Timing Measurement Reference Level Input 0.5 VCC Output 0.5 VCC Note1: For VCC4.0V 2: For VCC>4.0V FIGURE 1-1: HOLD TIMING CS 17 17 16 16 SCK 18 19 High-Impedance SO n + 2 n + 1 n n n - 1 Don’t Care 5 SI n + 2 n + 1 n n n - 1 HOLD FIGURE 1-2: SERIAL INPUT TIMING 4 CS 12 2 11 7 Mode 1,1 8 3 SCK Mode 0,0 5 6 SI MSB in LSB in High-Impedance SO  2007-2015 Microchip Technology Inc. DS20001836J-page 5

25AA1024 FIGURE 1-3: SERIAL OUTPUT TIMING CS 9 10 3 Mode 1,1 SCK Mode 0,0 13 15 14 SO MSB out LSB out Don’t Care SI DS20001836J-page 6  2007-2015 Microchip Technology Inc.

25AA1024 2.0 FUNCTIONAL DESCRIPTION BLOCK DIAGRAM STATUS 2.1 Principles of Operation HV Generator Register The 25AA1024 is a 131,072 byte Serial EEPROM designed to interface directly with the Serial Peripheral Interface (SPI) port of many of today’s popular microcontroller families, including Microchip’s PIC® EEPROM microcontrollers. It may also interface with I/O Control Memory X Array microcontrollers that do not have a built-in SPI port by Logic Control using discrete I/O lines programmed properly in Logic Dec firmware to match the SPI protocol. Page Latches The 25AA1024 contains an 8-bit instruction register. The device is accessed via the SI pin, with data being clocked in on the rising edge of SCK. The CS pin must SI be low and the HOLD pin must be high for the entire SO Y Decoder operation. CS Table2-1 contains a list of the possible instruction SCK bytes and format for device operation. All instructions, HOLD Sense Amp. addresses and data are transferred MSB first, LSB last. R/W Control WP Data (SI) is sampled on the first rising edge of SCK VCC VSS after CS goes low. If the clock line is shared with other peripheral devices on the SPI bus, the user can assert the HOLD input and place the 25AA1024 in ‘HOLD’ mode. After releasing the HOLD pin, operation will resume from the point when the HOLD was asserted. TABLE 2-1: INSTRUCTION SET Instruction Name Instruction Format Description READ 0000 0011 Read data from memory array beginning at selected address WRITE 0000 0010 Write data to memory array beginning at selected address WREN 0000 0110 Set the write enable latch (enable write operations) WRDI 0000 0100 Reset the write enable latch (disable write operations) RDSR 0000 0101 Read STATUS register WRSR 0000 0001 Write STATUS register PE 0100 0010 Page Erase – erase one page in memory array SE 1101 1000 Sector Erase – erase one sector in memory array CE 1100 0111 Chip Erase – erase all sectors in memory array RDID 1010 1011 Release from Deep Power-down and Read Electronic Signature DPD 1011 1001 Deep Power-Down mode  2007-2015 Microchip Technology Inc. DS20001836J-page 7

25AA1024 Read Sequence The data stored in the memory at the next address can be read sequentially by continuing to provide clock The device is selected by pulling CS low. The 8-bit pulses. The internal Address Pointer is automatically READ instruction is transmitted to the 25AA1024 incremented to the next higher address after each byte followed by the 24-bit address, with seven MSBs of the of data is shifted out. When the highest address is address being “don’t care” bits. After the correct READ reached (1FFFFh), the address counter rolls over to instruction and address are sent, the data stored in the address, 00000h, allowing the read cycle to be memory at the selected address is shifted out on the continued indefinitely. The read operation is terminated SO pin. by raising the CS pin (Figure2-1). FIGURE 2-1: READ SEQUENCE CS 0 1 2 3 4 5 6 7 8 9 10 11 29 30 31 32 33 34 35 36 37 38 39 SCK Instruction 24-bit Address SI 0 0 0 0 0 0 1 1 23 22 21 20 2 1 0 Data Out High-Impedance SO 7 6 5 4 3 2 1 0 DS20001836J-page 8  2007-2015 Microchip Technology Inc.

25AA1024 2.2 Write Sequence Note: Page write operations are limited to writing bytes within a single physical page, Prior to any attempt to write data to the 25AA1024, the regardless of the number of bytes write enable latch must be set by issuing the WREN actually being written. Physical page instruction (Figure2-4). This is done by setting CS low boundaries start at addresses that are and then clocking out the proper instruction into the integer multiples of the page buffer size 25AA1024. After all eight bits of the instruction are (or ‘page size’), and end at addresses that transmitted, the CS must be brought high to set the are integer multiples of page size – 1. If a write enable latch. If the write operation is initiated Page Write command attempts to write immediately after the WREN instruction without CS across a physical page boundary, the being brought high, the data will not be written to the result is that the data wraps around to the array because the write enable latch will not have been beginning of the current page (overwriting properly set. data previously stored there), instead of A write sequence includes an automatic, self-timed being written to the next page as might be erase cycle. It is not required to erase any portion of the expected. It is therefore necessary for the memory prior to issuing a Write command. application software to prevent page write Once the write enable latch is set, the user may operations that would attempt to cross a proceed by setting the CS low, issuing a WRITE page boundary. instruction, followed by the 24-bit address, with seven For the data to be actually written to the array, the CS MSBs of the address being “don’t care” bits, and then must be brought high after the Least Significant bit (D0) the data to be written. Up to 256 bytes of data can be of the nth data byte has been clocked in. If CS is sent to the device before a write cycle is necessary. brought high at any other time, the write operation will The only restriction is that all of the bytes must reside not be completed. Refer to Figure2-2 and Figure2-3 in the same page. for more detailed illustrations on the byte write Note: When doing a write of less than 256 bytes sequence and the page write sequence, respectively. the data in the rest of the page is While the write is in progress, the STATUS register may refreshed along with the data bytes being be read to check the status of the WPEN, WIP, WEL, written. This will force the entire page to BP1 and BP0 bits (Figure2-6). A read attempt of a endure a write cycle, for this reason memory array location will not be possible during a endurance is specified per page. write cycle. When the write cycle is completed, the write enable latch is reset. FIGURE 2-2: BYTE WRITE SEQUENCE CS TWC 0 1 2 3 4 5 6 7 8 9 10 11 29 30 31 32 33 34 35 36 37 38 39 SCK Instruction 24-bit Address Data Byte SI 0 0 0 0 0 0 1 0 23 22 21 20 2 1 0 7 6 5 4 3 2 1 0 High-Impedance SO  2007-2015 Microchip Technology Inc. DS20001836J-page 9

25AA1024 FIGURE 2-3: PAGE WRITE SEQUENCE CS 0 1 2 3 4 5 6 7 8 9 10 11 29 30 31 32 33 34 35 36 37 38 39 SCK Instruction 24-bit Address Data Byte 1 SI 0 0 0 0 0 0 1 0 23 22 21 20 2 1 0 7 6 5 4 3 2 1 0 CS 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 SCK Data Byte 2 Data Byte 3 Data Byte n (256 max.) SI 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 DS20001836J-page 10  2007-2015 Microchip Technology Inc.

25AA1024 2.3 Write Enable (WREN) and Write The following is a list of conditions under which the Disable (WRDI) write enable latch will be reset: • Power-up The 25AA1024 contains a write enable latch. See • WRDI instruction successfully executed Table2-4 for the Write-Protect Functionality Matrix. This latch must be set before any write operation will be • WRSR instruction successfully executed completed internally. The WREN instruction will set the • WRITE instruction successfully executed latch, and the WRDI will reset the latch. • PE instruction successfully executed • SE instruction successfully executed • CE instruction successfully executed FIGURE 2-4: WRITE ENABLE SEQUENCE (WREN) CS 0 1 2 3 4 5 6 7 SCK SI 0 0 0 0 0 1 1 0 High-Impedance SO FIGURE 2-5: WRITE DISABLE SEQUENCE (WRDI) CS 0 1 2 3 4 5 6 7 SCK SI 0 0 0 0 0 1 10 0 High-Impedance SO  2007-2015 Microchip Technology Inc. DS20001836J-page 11

25AA1024 2.4 Read Status Register Instruction The Write Enable Latch (WEL) bit indicates the status (RDSR) of the write enable latch and is read-only. When set to a ‘1’, the latch allows writes to the array, when set to a The Read Status Register instruction (RDSR) provides ‘0’, the latch prohibits writes to the array. The state of access to the STATUS register. The STATUS register this bit can always be updated via the WREN or WRDI may be read at any time, even during a write cycle. The commands regardless of the state of write protection STATUS register is formatted as follows: on the STATUS register. These commands are shown in Figure2-4 and Figure2-5. TABLE 2-2: STATUS REGISTER The Block Protection (BP0 and BP1) bits indicate 7 6 5 4 3 2 1 0 which blocks are currently write-protected. These bits are set by the user issuing the WRSR instruction. These W/R – – – W/R W/R R R bits are nonvolatile and are shown in Table2-3. WPEN X X X BP1 BP0 WEL WIP See Figure2-6 for the RDSR timing sequence. W/R = writable/readable. R = read-only. The Write-In-Process (WIP) bit indicates whether the 25AA1024 is busy with a write operation. When set to a ‘1’, a write is in progress, when set to a ‘0’, no write is in progress. This bit is read-only. FIGURE 2-6: READ STATUS REGISTER TIMING SEQUENCE (RDSR) CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCK Instruction SI 0 0 0 0 0 1 0 1 Data from STATUS register High-Impedance SO 7 6 5 4 3 2 1 0 DS20001836J-page 12  2007-2015 Microchip Technology Inc.

25AA1024 2.5 Write Status Register Instruction The Write-Protect Enable (WPEN) bit is a nonvolatile (WRSR) bit that is available as an enable bit for the WP pin. The Write-Protect (WP) pin and the Write-Protect Enable The Write Status Register instruction (WRSR) allows the (WPEN) bit in the STATUS register control the user to write to the nonvolatile bits in the STATUS programmable hardware write-protect feature. register, as shown in Table2-2. The user is able to Hardware write protection is enabled when the WP pin select one of four levels of protection for the array by is low and the WPEN bit is high. Hardware write writing to the appropriate bits in the STATUS register. protection is disabled when either the WP pin is high or The array is divided up into four segments. The user the WPEN bit is low. When the chip is hardware has the ability to write-protect none, one, two, or all four write-protected, only writes to nonvolatile bits in the of the segments of the array. The partitioning is STATUS register are disabled. See Table2-4 for a controlled, as shown in Table2-3. matrix of functionality on the WPEN bit. See Figure2-7 for the WRSR timing sequence. TABLE 2-3: ARRAY PROTECTION Array Addresses Array Addresses BP1 BP0 Write-Protected Unprotected 0 0 none All (Sectors 0, 1, 2 & 3) (00000h-1FFFFh) 0 1 Upper 1/4 (Sector 3) Lower 3/4 (Sectors 0, 1 & 2) (18000h-1FFFFh) (00000h-17FFFh) 1 0 Upper 1/2 (Sectors 2 & 3) Lower 1/2 (Sectors 0 & 1) (10000h-1FFFFh) (00000h-0FFFFh) 1 1 All (Sectors 0, 1, 2 & 3) none (00000h-1FFFFh) FIGURE 2-7: WRITE STATUS REGISTER TIMING SEQUENCE (WRSR) CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCK Instruction Data to STATUS register SI 0 0 0 0 0 0 0 1 7 6 5 4 3 2 1 0 High-Impedance SO  2007-2015 Microchip Technology Inc. DS20001836J-page 13

25AA1024 2.6 Data Protection 2.7 Power-On State The following protection has been implemented to The 25AA1024 powers on in the following state: prevent inadvertent writes to the array: • The device is in low-power Standby mode • The write enable latch is reset on power-up (CS=1) • A write enable instruction must be issued to set • The write enable latch is reset the write enable latch • SO is in high-impedance state • After a byte write, page write or STATUS register • A high-to-low-level transition on CS is required to write, the write enable latch is reset enter active state • CS must be set high after the proper number of clock cycles to start an internal write cycle • Access to the array during an internal write cycle is ignored and programming is continued TABLE 2-4: WRITE-PROTECT FUNCTIONALITY MATRIX WEL WPEN WP Protected Blocks Unprotected Blocks STATUS Register (SR bit 1) (SR bit 7) (pin 3) 0 x x Protected Protected Protected 1 0 x Protected Writable Writable 1 1 0 (low) Protected Writable Protected 1 1 1 (high) Protected Writable Writable x = don’t care DS20001836J-page 14  2007-2015 Microchip Technology Inc.

25AA1024 2.8 PAGE ERASE The Page Erase function will erase all bits (FFh) inside CS must then be driven high after the last bit if the the given page. A Write Enable (WREN) instruction address or the Page Erase will not execute. Once the must be given prior to attempting a Page Erase. This CS is driven high, the self-timed Page Erase cycle is is done by setting CS low and then clocking out the started. The WIP bit in the STATUS register can be proper instruction into the 25AA1024. After all eight read to determine when the Page Erase cycle is bits of the instruction are transmitted, the CS must be complete. brought high to set the write enable latch. If a Page Erase function is given to an address that The Page Erase function is entered by driving CS low, has been protected by the Block Protect bits (BP0, followed by the instruction code (Figure2-8), and BP1) then the sequence will be aborted and no erase three address bytes. Any address inside the page to will occur. be erased is a valid address. FIGURE 2-8: PAGE ERASE SEQUENCE CS 0 1 2 3 4 5 6 7 8 9 10 11 29 30 31 SCK Instruction 24-bit Address SI 0 1 0 0 0 0 1 0 23 22 21 20 2 1 0 High-Impedance SO  2007-2015 Microchip Technology Inc. DS20001836J-page 15

25AA1024 2.9 SECTOR ERASE The Sector Erase function will erase all bits (FFh) CS must then be driven high after the last bit if the inside the given sector. A Write Enable (WREN) address or the Sector Erase will not execute. Once the instruction must be given prior to executing a Sector CS is driven high, the self-timed Sector Erase cycle is Erase. This is done by setting CS low and then started. The WIP bit in the STATUS register can be clocking out the proper instruction into the 25AA1024. read to determine when the Sector Erase cycle is After all eight bits of the instruction are transmitted, the complete. CS must be brought high to set the write enable latch. If a SECTOR ERASE instruction is given to an address The Sector Erase function is entered by driving CS that has been protected by the Block Protect bits (BP0, low, followed by the instruction code (Figure2-9), and BP1) then the sequence will be aborted and no erase three address bytes. Any address inside the sector to will occur. be erased is a valid address. See Table2-3 for Sector Addressing. FIGURE 2-9: SECTOR ERASE SEQUENCE CS 0 1 2 3 4 5 6 7 8 9 10 11 29 30 31 SCK Instruction 24-bit Address SI 1 1 0 1 1 0 0 0 23 22 21 20 2 1 0 High-Impedance SO DS20001836J-page 16  2007-2015 Microchip Technology Inc.

25AA1024 2.10 CHIP ERASE The Chip Erase function will erase all bits (FFh) in the The CS pin must be driven high after the eighth bit of array. A Write Enable (WREN) instruction must be given the instruction code has been given or the Chip Erase prior to executing a Chip Erase. This is done by setting function will not be executed. Once the CS pin is CS low and then clocking out the proper instruction driven high, the self-timed Chip Erase function begins. into the 25AA1024. After all eight bits of the instruction While the device is executing the Chip Erase function are transmitted, the CS must be brought high to set the WIP bit in the STATUS register can be read to the write enable latch. determine when the Chip Erase function is complete. The Chip Erase function is entered by driving the CS The Chip Erase function is ignored if either of the low, followed by the instruction code (Figure2-10) Block Protect bits (BP0, BP1) are not 0, meaning ¼, onto the SI line. ½, or all of the array is protected. FIGURE 2-10: CHIP ERASE SEQUENCE CS 0 1 2 3 4 5 6 7 SCK SI 1 1 0 0 0 1 1 1 High-Impedance SO  2007-2015 Microchip Technology Inc. DS20001836J-page 17

25AA1024 2.11 DEEP POWER-DOWN MODE Deep Power-Down mode of the 25AA1024 is its All instructions given during Deep Power-Down mode lowest power consumption state. The device will not are ignored except the Read Electronic Signature respond to any of the Read or Write commands while Command (RDID). The RDID command will release in Deep Power-Down mode, and therefore it can be the device from Deep Power-down and outputs the used as an additional software write protection feature. electronic signature on the SO pin, and then returns The Deep Power-Down mode is entered by driving CS the device to Standby mode after delay (TREL). low, followed by the instruction code (Figure2-11) onto Deep Power-Down mode automatically releases at the SI line, followed by driving CS high. device power-down. Once power is restored to the device, it will power-up in the Standby mode. If the CS pin is not driven high after the eighth bit of the instruction code has been given, the device will not execute Deep Power-down. Once the CS line is driven high, there is a delay (TDP) before the current settles to its lowest consumption. FIGURE 2-11: DEEP POWER-DOWN SEQUENCE CS 0 1 2 3 4 5 6 7 SCK SI 1 0 1 1 1 0 0 1 High-Impedance SO DS20001836J-page 18  2007-2015 Microchip Technology Inc.

25AA1024 2.12 RELEASE FROM DEEP Release from Deep Power-Down mode and Read POWER-DOWN AND READ Electronic Signature is entered by driving CS low, followed by the RDID instruction code (Figure2-12) ELECTRONIC SIGNATURE and then a dummy address of 24 bits (A23-A0). After Once the device has entered Deep Power-Down the last bit of the dummy address is clocked in, the mode, all instructions are ignored except the release 8-bit electronic signature is clocked out on the SO from Deep Power-down and Read Electronic pin. Signature command. This command can also be used After the signature has been read out at least once, when the device is not in Deep Power-down, to read the sequence can be terminated by driving CS high. the electronic signature out on the SO pin unless After a delay of TREL, the device will then return to another command is being executed such as Erase, Standby mode and will wait to be selected so it can be Program or Write STATUS register. given new instructions. If additional clock cycles are sent after the electronic signature has been read once, it will continue to output the signature on the SO line until the sequence is terminated. FIGURE 2-12: RELEASE FROM DEEP POWER-DOWN AND READ ELECTRONIC SIGNATURE CS TREL 0 1 2 3 4 5 6 7 8 9 10 11 29 30 31 32 33 34 35 36 37 38 39 SCK Instruction 24-bit Address SI 1 0 1 0 1 0 1 1 23 22 21 20 2 1 0 Electronic Signature Out High-Impedance SO 7 6 5 4 3 2 1 0 0 0 1 0 1 0 0 1 Manufacturers ID 0x29 Driving CS high after the 8-bit RDID command, but before the electronic signature has been transmitted, will still ensure the device will be taken out of Deep Power-Down mode, as shown in Figure2-13. FIGURE 2-13: RELEASE FROM DEEP POWER-DOWN AND READ ELECTRONIC SIGNATURE CS 0 1 2 3 4 5 6 7 TREL SCK Instruction SI 1 0 1 0 1 0 1 1 High-Impedance SO  2007-2015 Microchip Technology Inc. DS20001836J-page 19

25AA1024 3.0 PIN DESCRIPTIONS The WP pin function is blocked when the WPEN bit in the STATUS register is low. This allows the user to The descriptions of the pins are listed in Table3-1. install the 25AA1024 in a system with WP pin grounded and still be able to write to the STATUS register. The TABLE 3-1: PIN FUNCTION TABLE WP pin functions will be enabled when the WPEN bit is set high. Name Pin Number Function 3.4 Serial Input (SI) Chip Select Input CS 1 The SI pin is used to transfer data into the device. It SO 2 Serial Data Output receives instructions, addresses and data. Data is WP 3 Write-Protect Pin latched on the rising edge of the serial clock. VSS 4 Ground 3.5 Serial Clock (SCK) SI 5 Serial Data Input The SCK is used to synchronize the communication SCK 6 Serial Clock Input between a master and the 25AA1024. Instructions, HOLD 7 Hold Input addresses or data present on the SI pin are latched on the rising edge of the clock input, while data on the SO VCC 8 Supply Voltage pin is updated after the falling edge of the clock input. 3.1 Chip Select (CS) 3.6 Hold (HOLD) A low level on this pin selects the device. A high level The HOLD pin is used to suspend transmission to the deselects the device and forces it into Standby mode. 25AA1024 while in the middle of a serial sequence However, a programming cycle which is already without having to retransmit the entire sequence again. initiated or in progress will be completed, regardless of It must be held high any time this function is not being the CS input signal. If CS is brought high during a used. Once the device is selected and a serial program cycle, the device will go into Standby mode as sequence is underway, the HOLD pin may be pulled soon as the programming cycle is complete. When the low to pause further serial communication without device is deselected, SO goes to the high-impedance resetting the serial sequence. The HOLD pin must be state, allowing multiple parts to share the same SPI brought low while SCK is low, otherwise the HOLD bus. A low-to-high transition on CS after a valid write function will not be invoked until the next SCK sequence initiates an internal write cycle. After high-to-low transition. The 25AA1024 must remain power-up, a low level on CS is required prior to any selected during this sequence. The SI, SCK and SO sequence being initiated. pins are in a high-impedance state during the time the 3.2 Serial Output (SO) device is paused and transitions on these pins will be ignored. To resume serial communication, HOLD must The SO pin is used to transfer data out of the be brought high while the SCK pin is low, otherwise 25AA1024. During a read cycle, data is shifted out on serial communication will not resume. Pulling the this pin after the falling edge of the serial clock. HOLD line low at any time will tri-state the SO line. 3.3 Write-Protect (WP) This pin is used in conjunction with the WPEN bit in the STATUS register to prohibit writes to the nonvolatile bits in the STATUS register. When WP is low and WPEN is high, writing to the nonvolatile bits in the STATUS register is disabled. All other operations function normally. When WP is high, all functions, including writes to the nonvolatile bits in the STATUS register, operate normally. If the WPEN bit is set, WP low during a STATUS register write sequence will disable writing to the STATUS register. If an internal write cycle has already begun, WP going low will have no effect on the write. DS20001836J-page 20  2007-2015 Microchip Technology Inc.

25AA1024 4.0 PACKAGING INFORMATION 4.1 Package Marking Information 8-Lead DFN Example: XXXXXXX 5AA1024 T/XXXXX I/MF e3 YYWW 1509 NNN 1L7 8-Lead PDIP Example: XXXXXXXX 25AA1024 T/XXXNNN I/P e 3 1L7 YYWW 1509 8-Lead SOIJ Example: XXXXXXXX 25AA1024 T/XXXXXX I/SM e 3 YYWWNNN 15091L7 Legend: XX...X Part number or part number code T Temperature (I, E) Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code (2 characters for small packages) e3 JEDEC® designator for Matte Tin (Sn) Note: For very small packages with no room for the JEDEC® designator e3 , the marking will only appear on the outer carton or reel label. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2007-2015 Microchip Technology Inc. DS20001836J-page 21

25AA1024 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)(cid:15)(cid:16)(cid:6)(cid:10)(cid:8)(cid:17)(cid:10)(cid:6)(cid:12)(cid:18)(cid:8)(cid:19)(cid:20)(cid:8)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:6)(cid:14)(cid:21)(cid:6)(cid:22)(cid:5)(cid:8)(cid:23)(cid:24)(cid:17)(cid:25)(cid:8)(cid:26)(cid:8)(cid:27)(cid:28)(cid:29)(cid:8)(cid:30)(cid:30)(cid:8)(cid:31)(cid:20)(cid:7) (cid:8)!(cid:15)(cid:17)(cid:19)(cid:3)"#(cid:8) (cid:9)$(cid:19)%& "’(cid:19)($(cid:4))*+(cid:15) (cid:19)(cid:20)(cid:12)(cid:5), 2(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)+(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)+(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)133***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’3(cid:12)(cid:28)(cid:8)+(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) D e D1 b L N N K E E2 E1 EXPOSED PAD NOTE1 1 2 2 1 NOTE1 D2 TOPVIEW BOTTOMVIEW φ A A2 A1 A3 NOTE2 4(cid:15)(cid:7)&! (cid:6)(cid:19)55(cid:19)(cid:6),(cid:13),(cid:26)(cid:22) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:2)5(cid:7)’(cid:7)&! (cid:6)(cid:19)6 67(cid:6) (cid:6)(cid:25)8 6"’)(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)(cid:31)(cid:7)(cid:15)! 6 9 (cid:31)(cid:7)&(cid:8)(cid:11) (cid:14) (cid:30)(cid:20)(cid:3)(cid:5)(cid:2)/(cid:22)0 7 (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2):(cid:14)(cid:7)(cid:17)(cid:11)& (cid:25) ; (cid:4)(cid:20)9. (cid:30)(cid:20)(cid:4)(cid:4) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)+(cid:28)(cid:17)(cid:14)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)+(cid:15)(cid:14)!! (cid:25)(cid:3) ; (cid:4)(cid:20)<. (cid:4)(cid:20)9(cid:4) (cid:22)&(cid:28)(cid:15)#(cid:10)%%(cid:2) (cid:25)(cid:30) (cid:4)(cid:20)(cid:4)(cid:4) (cid:4)(cid:20)(cid:4)(cid:30) (cid:4)(cid:20)(cid:4). /(cid:28)!(cid:14)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)+(cid:15)(cid:14)!! (cid:25)(cid:29) (cid:4)(cid:20)(cid:3)(cid:4)(cid:2)(cid:26),2 7 (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)5(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21) (cid:23)(cid:20)(cid:24)(cid:3)(cid:2)/(cid:22)0 (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)+(cid:28)(cid:17)(cid:14)(cid:2)5(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21)(cid:30) (cid:23)(cid:20)<(cid:5)(cid:2)/(cid:22)0 ,$(cid:12)(cid:10)!(cid:14)#(cid:2)(cid:31)(cid:28)#(cid:2)5(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21)(cid:3) (cid:29)(cid:20)9. (cid:23)(cid:20)(cid:4)(cid:4) (cid:23)(cid:20)(cid:30). 7 (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)=(cid:7)#&(cid:11) , .(cid:20)(cid:24)(cid:24)(cid:2)/(cid:22)0 (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)+(cid:28)(cid:17)(cid:14)(cid:2)=(cid:7)#&(cid:11) ,(cid:30) .(cid:20)(cid:5)(cid:23)(cid:2)/(cid:22)0 ,$(cid:12)(cid:10)!(cid:14)#(cid:2)(cid:31)(cid:28)#(cid:2)=(cid:7)#&(cid:11) ,(cid:3) (cid:3)(cid:20)(cid:30)< (cid:3)(cid:20)(cid:29)(cid:30) (cid:3)(cid:20)(cid:23)< 0(cid:10)(cid:15)&(cid:28)(cid:8)&(cid:2)=(cid:7)#&(cid:11) ) (cid:4)(cid:20)(cid:29). (cid:4)(cid:20)(cid:23)(cid:4) (cid:4)(cid:20)(cid:23)(cid:5) 0(cid:10)(cid:15)&(cid:28)(cid:8)&(cid:2)5(cid:14)(cid:15)(cid:17)&(cid:11) 5 (cid:4)(cid:20).(cid:4) (cid:4)(cid:20)<(cid:4) (cid:4)(cid:20)(cid:5). 0(cid:10)(cid:15)&(cid:28)(cid:8)&(cid:27)&(cid:10)(cid:27),$(cid:12)(cid:10)!(cid:14)#(cid:2)(cid:31)(cid:28)# > (cid:4)(cid:20)(cid:3)(cid:4) ; ; (cid:6)(cid:10)#(cid:14)(cid:16)(cid:2)(cid:21)(cid:9)(cid:28)%&(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14)(cid:2)(cid:13)(cid:10)(cid:12) (cid:3) ; ; (cid:30)(cid:3)? (cid:19)(cid:20)(cid:12)(cid:5)(cid:11), (cid:30)(cid:20) (cid:31)(cid:7)(cid:15)(cid:2)(cid:30)(cid:2) (cid:7)!"(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)#(cid:14)$(cid:2)%(cid:14)(cid:28)&"(cid:9)(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)((cid:2))"&(cid:2)’"!&(cid:2))(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)*(cid:7)&(cid:11)(cid:7)(cid:15)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)&(cid:8)(cid:11)(cid:14)#(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) (cid:31)(cid:28)(cid:8)+(cid:28)(cid:17)(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2)(cid:11)(cid:28) (cid:14)(cid:2)(cid:10)(cid:15)(cid:14)(cid:2)(cid:10)(cid:9)(cid:2)’(cid:10)(cid:9)(cid:14)(cid:2)(cid:14)$(cid:12)(cid:10)!(cid:14)#(cid:2)&(cid:7)(cid:14)(cid:2))(cid:28)(cid:9)!(cid:2)(cid:28)&(cid:2)(cid:14)(cid:15)#!(cid:20) (cid:29)(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)#(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6),(cid:2)-(cid:30)(cid:23)(cid:20).(cid:6)(cid:20) /(cid:22)01 /(cid:28)!(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)&(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)$(cid:28)(cid:8)&(cid:2) (cid:28)(cid:16)"(cid:14)(cid:2)!(cid:11)(cid:10)*(cid:15)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)!(cid:20) (cid:26),21 (cid:26)(cid:14)%(cid:14)(cid:9)(cid:14)(cid:15)(cid:8)(cid:14)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)((cid:2)"!"(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)((cid:2)%(cid:10)(cid:9)(cid:2)(cid:7)(cid:15)%(cid:10)(cid:9)’(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:12)"(cid:9)(cid:12)(cid:10)!(cid:14)!(cid:2)(cid:10)(cid:15)(cid:16)(cid:18)(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)0(cid:4)(cid:23)(cid:27)(cid:30)(cid:30)(cid:29)/ DS20001836J-page 22  2007-2015 Microchip Technology Inc.

25AA1024 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)(cid:15)(cid:16)(cid:6)(cid:10)(cid:8)(cid:17)(cid:10)(cid:6)(cid:12)(cid:18)(cid:8)(cid:19)(cid:20)(cid:8)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:6)(cid:14)(cid:21)(cid:6)(cid:22)(cid:5)(cid:8)(cid:23)(cid:24)(cid:17)(cid:25)(cid:8)(cid:26)(cid:8)(cid:27)(cid:28)(cid:29)(cid:8)(cid:30)(cid:30)(cid:8)(cid:31)(cid:20)(cid:7) (cid:8)!(cid:15)(cid:17)(cid:19)(cid:3)"# (cid:19)(cid:20)(cid:12)(cid:5), 2(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)+(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)+(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)133***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’3(cid:12)(cid:28)(cid:8)+(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) (cid:2) e D L b N N K E E2 EXPOSEDPAD NOTE1 NOTE1 1 2 2 1 D2 TOPVIEW BOTTOMVIEW A A3 A1 NOTE2 4(cid:15)(cid:7)&! (cid:6)(cid:19)55(cid:19)(cid:6),(cid:13),(cid:26)(cid:22) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:2)5(cid:7)’(cid:7)&! (cid:6)(cid:19)6 67(cid:6) (cid:6)(cid:25)8 6"’)(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)(cid:31)(cid:7)(cid:15)! 6 9 (cid:31)(cid:7)&(cid:8)(cid:11) (cid:14) (cid:30)(cid:20)(cid:3)(cid:5)(cid:2)/(cid:22)0 7 (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2):(cid:14)(cid:7)(cid:17)(cid:11)& (cid:25) (cid:4)(cid:20)9(cid:4) (cid:4)(cid:20)9. (cid:30)(cid:20)(cid:4)(cid:4) (cid:22)&(cid:28)(cid:15)#(cid:10)%%(cid:2) (cid:25)(cid:30) (cid:4)(cid:20)(cid:4)(cid:4) (cid:4)(cid:20)(cid:4)(cid:30) (cid:4)(cid:20)(cid:4). 0(cid:10)(cid:15)&(cid:28)(cid:8)&(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)+(cid:15)(cid:14)!! (cid:25)(cid:29) (cid:4)(cid:20)(cid:3)(cid:4)(cid:2)(cid:26),2 7 (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)5(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21) .(cid:20)(cid:4)(cid:4)(cid:2)/(cid:22)0 7 (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)=(cid:7)#&(cid:11) , <(cid:20)(cid:4)(cid:4)(cid:2)/(cid:22)0 ,$(cid:12)(cid:10)!(cid:14)#(cid:2)(cid:31)(cid:28)#(cid:2)5(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21)(cid:3) (cid:29)(cid:20)(cid:24)(cid:4) (cid:23)(cid:20)(cid:4)(cid:4) (cid:23)(cid:20)(cid:30)(cid:4) ,$(cid:12)(cid:10)!(cid:14)#(cid:2)(cid:31)(cid:28)#(cid:2)=(cid:7)#&(cid:11) ,(cid:3) (cid:3)(cid:20)(cid:3)(cid:4) (cid:3)(cid:20)(cid:29)(cid:4) (cid:3)(cid:20)(cid:23)(cid:4) 0(cid:10)(cid:15)&(cid:28)(cid:8)&(cid:2)=(cid:7)#&(cid:11) ) (cid:4)(cid:20)(cid:29). (cid:4)(cid:20)(cid:23)(cid:4) (cid:4)(cid:20)(cid:23)9 0(cid:10)(cid:15)&(cid:28)(cid:8)&(cid:2)5(cid:14)(cid:15)(cid:17)&(cid:11) 5 (cid:4)(cid:20).(cid:4) (cid:4)(cid:20)<(cid:4) (cid:4)(cid:20)(cid:5). 0(cid:10)(cid:15)&(cid:28)(cid:8)&(cid:27)&(cid:10)(cid:27),$(cid:12)(cid:10)!(cid:14)#(cid:2)(cid:31)(cid:28)# > (cid:4)(cid:20)(cid:3)(cid:4) ; ; (cid:19)(cid:20)(cid:12)(cid:5)(cid:11), (cid:30)(cid:20) (cid:31)(cid:7)(cid:15)(cid:2)(cid:30)(cid:2) (cid:7)!"(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)#(cid:14)$(cid:2)%(cid:14)(cid:28)&"(cid:9)(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)((cid:2))"&(cid:2)’"!&(cid:2))(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)*(cid:7)&(cid:11)(cid:7)(cid:15)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)&(cid:8)(cid:11)(cid:14)#(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) (cid:31)(cid:28)(cid:8)+(cid:28)(cid:17)(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2)(cid:11)(cid:28) (cid:14)(cid:2)(cid:10)(cid:15)(cid:14)(cid:2)(cid:10)(cid:9)(cid:2)’(cid:10)(cid:9)(cid:14)(cid:2)(cid:14)$(cid:12)(cid:10)!(cid:14)#(cid:2)&(cid:7)(cid:14)(cid:2))(cid:28)(cid:9)!(cid:2)(cid:28)&(cid:2)(cid:14)(cid:15)#!(cid:20) (cid:29)(cid:20) (cid:31)(cid:28)(cid:8)+(cid:28)(cid:17)(cid:14)(cid:2)(cid:7)!(cid:2)!(cid:28)*(cid:2)!(cid:7)(cid:15)(cid:17)"(cid:16)(cid:28)&(cid:14)#(cid:20) (cid:23)(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)#(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6),(cid:2)-(cid:30)(cid:23)(cid:20).(cid:6)(cid:20) /(cid:22)01 /(cid:28)!(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)&(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)$(cid:28)(cid:8)&(cid:2) (cid:28)(cid:16)"(cid:14)(cid:2)!(cid:11)(cid:10)*(cid:15)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)!(cid:20) (cid:26),21 (cid:26)(cid:14)%(cid:14)(cid:9)(cid:14)(cid:15)(cid:8)(cid:14)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)((cid:2)"!"(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)((cid:2)%(cid:10)(cid:9)(cid:2)(cid:7)(cid:15)%(cid:10)(cid:9)’(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:12)"(cid:9)(cid:12)(cid:10)!(cid:14)!(cid:2)(cid:10)(cid:15)(cid:16)(cid:18)(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)0(cid:4)(cid:23)(cid:27)(cid:30)(cid:3)(cid:3)/  2007-2015 Microchip Technology Inc. DS20001836J-page 23

25AA1024 (cid:19)(cid:20)(cid:12)(cid:5), 2(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)+(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)+(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)133***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’3(cid:12)(cid:28)(cid:8)+(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) DS20001836J-page 24  2007-2015 Microchip Technology Inc.

25AA1024 8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D A N B E1 NOTE 1 1 2 TOP VIEW E C A A2 PLANE L c A1 e eB 8X b1 8X b .010 C SIDE VIEW END VIEW Microchip Technology Drawing No. C04-018D Sheet 1 of 2  2007-2015 Microchip Technology Inc. DS20001836J-page 25

25AA1024 8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging ALTERNATE LEAD DESIGN (VENDOR DEPENDENT) DATUM A DATUM A b b e e 2 2 e e Units INCHES Dimension Limits MIN NOM MAX Number of Pins N 8 Pitch e .100 BSC Top to Seating Plane A - - .210 Molded Package Thickness A2 .115 .130 .195 Base to Seating Plane A1 .015 - - Shoulder to Shoulder Width E .290 .310 .325 Molded Package Width E1 .240 .250 .280 Overall Length D .348 .365 .400 Tip to Seating Plane L .115 .130 .150 Lead Thickness c .008 .010 .015 Upper Lead Width b1 .040 .060 .070 Lower Lead Width b .014 .018 .022 Overall Row Spacing § eB - - .430 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side. 4. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing No. C04-018D Sheet 2 of 2 DS20001836J-page 26  2007-2015 Microchip Technology Inc.

25AA1024 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2007-2015 Microchip Technology Inc. DS20001836J-page 27

25AA1024 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS20001836J-page 28  2007-2015 Microchip Technology Inc.

25AA1024 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2007-2015 Microchip Technology Inc. DS20001836J-page 29

25AA1024 APPENDIX A: REVISION HISTORY Revision C (02/2007) Revised Features Section (Self-timed Erase and Write Cycles); Revised Table 1-1 (parameters D012 and D13); Table 1-2 (parameters 20-24); Revised Package Marking Information; Replaced Package Drawings; Revised Product ID System Section (SM package); Changed PICmicro to PIC. Revision D (07/2007) Revised Features; Revised Tables 1-1 and 1-2 (added Industrial temp. and revised parameters 22-23); Replaced Package Drawings (Rev. AP); Revised Product ID System; Changed Flash to EEPROM. Revision E (10/2007) Removed 25LC1024 part number; New data sheet created for 25LC1024 (DS22064); Revised Tables; Updates throughout. Revision F (05/2008) Modified parameter D006 in Table 1-1; Revised Package Marking Information; Replaced Package Drawings. Revision G (01/2010) Added 8-Lead (MF) DFN-S Land Pattern; Replaced 8-Lead (SM) SOIJ Land Pattern. Revision H (05/2010) Revised Table 1-2, Param. No 25 Conditions; Revised Section 2.2; Added note. Revision J (04/2015) Corrected Features section; Revised Table1-2, updated ‘Conditions’; Revised Figure2-12, added parameter TREL; Revised Section2-12, clarified condition for existing Deep Power-Down mode. DS20001836J-page 30  2007-2015 Microchip Technology Inc.

25AA1024 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our web site at Users of Microchip products can receive assistance www.microchip.com. This web site is used as a means through several channels: to make files and information easily available to • Distributor or Representative customers. Accessible by using your favorite Internet • Local Sales Office browser, the web site contains the following • Field Application Engineer (FAE) information: • Technical Support • Product Support – Data sheets and errata, application notes and sample programs, design Customers should contact their distributor, resources, user’s guides and hardware support representative or Field Application Engineer (FAE) for documents, latest software releases and archived support. Local sales offices are also available to help software customers. A listing of sales offices and locations is included in the back of this document. • General Technical Support – Frequently Asked Questions (FAQ), technical support requests, Technical support is available through the web site online discussion groups, Microchip consultant at: http://www.microchip.com/support program member listing • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions.  2007-2015 Microchip Technology Inc. DS20001836J-page 31

25AA1024 NOTES: DS20001836J-page 32  2007-2015 Microchip Technology Inc.

25AA1024 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. [X](1) X /XX Examples: a) 25AA1024T-I/SM = 1 Mbit, 1.8V Serial Device Tape and Reel Temperature Package EEPROM, Industrial temp., Tape & Reel, SOIJ Option Range package b) 25AA1024T-I/MF = 1 Mbit, 1.8V Serial EEPROM, Industrial temp., Tape & Reel, DFN Device: 25AA1024 1 Mbit, 1.8V, 256-Byte Page SPI Serial EEPROM package Tape & Reel Blank = Standard packaging (tube) Option: T = Tape & Reel Note 1: Tape and Reel identifier only appears in the catalog part number description. This Temperature I = -40C to+85C identifier is used for ordering purposes Range: and is not printed on the device package. Check with your Microchip Sales Office Package: MF = Micro Lead Frame (6 x 5 mm body), 8-lead for package availability with the Tape and P = Plastic DIP (300 mil body), 8-lead Reel option. SM = Plastic SOIJ (5.28 mm), 8-lead  2007-2015 Microchip Technology Inc. DS20001836J-page 33

25AA1024 NOTES: DS20001836J-page 34  2007-2015 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC, and may be superseded by updates. It is your responsibility to FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer, ensure that your application meets with your specifications. LANCheck, MediaLB, MOST, MOST logo, MPLAB, MICROCHIP MAKES NO REPRESENTATIONS OR OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC, WARRANTIES OF ANY KIND WHETHER EXPRESS OR SST, SST Logo, SuperFlash and UNI/O are registered IMPLIED, WRITTEN OR ORAL, STATUTORY OR trademarks of Microchip Technology Incorporated in the OTHERWISE, RELATED TO THE INFORMATION, U.S.A. and other countries. INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR The Embedded Control Solutions Company and mTouch are FITNESS FOR PURPOSE. Microchip disclaims all liability registered trademarks of Microchip Technology Incorporated arising from this information and its use. Use of Microchip in the U.S.A. devices in life support and/or safety applications is entirely at Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo, the buyer’s risk, and the buyer agrees to defend, indemnify and CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit hold harmless Microchip from any and all damages, claims, Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet, suits, or expenses resulting from such use. No licenses are KleerNet logo, MiWi, MPASM, MPF, MPLAB Certified logo, conveyed, implicitly or otherwise, under any Microchip MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code intellectual property rights. Generation, PICDEM, PICDEM.net, PICkit, PICtail, RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2007-2015, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. ISBN: 978-1-63277-265-7 QUALITY MANAGEMENT SYSTEM Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and CERTIFIED BY DNV Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures == ISO/TS 16949 == are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.  2007-2015 Microchip Technology Inc. DS20001836J-page 35

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