25AA02E48/25AA02E64 2K SPI Bus Serial EEPROMs with EUI-48™ or EUI-64™ Node Identity Device Selection Table Part Number VCC Range Page Size Temp. Ranges Packages Node Address 25AA02E48 1.8V-5.5V 16 Bytes I SN, OT EUI-48™ 25AA02E64 1.8V-5.5V 16 Bytes I SN, OT EUI-64™ Features Description • Preprogrammed Globally Unique, 48-bit or 64-bit The Microchip Technology Inc. Node Address 25AA02E48/25AA02E64 (25AA02EXX) is a 2Kbit • Compatible with EUI-48™ and EUI-64™ Serial Electrically Erasable Programmable Read-Only Memory (EEPROM). The memory is accessed via a • 10MHz Maximum Clock Frequency simple Serial Peripheral Interface (SPI) compatible • Low-Power CMOS Technology: serial bus. The bus signals required are a clock input - Maximum Write Current: 5mA at 5.5V (SCK) plus separate data in (SI) and data out (SO) - Read Current: 5mA at 5.5V, 10MHz lines. Access to the device is controlled through a Chip - Standby Current: 1µA at 2.5V Select (CS) input. • 256x8-bit Organization Note: 25AA02EXX is used in this document as a • Write Page Mode (up to 16 bytes) generic part number for the • Sequential Read 25AA02E48/25AA02E64 devices. • Self-Timed Erase and Write Cycles (5ms maximum) Communication to the device can be paused via the • Block Write Protection: hold pin (HOLD). While the device is paused, - Protect none, 1/4, 1/2 or all of array transitions on its inputs will be ignored, with the exception of Chip Select, allowing the host to service • Built-in Write Protection: higher priority interrupts. - Power-on/off data protection circuitry The 25AA02EXX is available in the standard 8-lead - Write enable latch SOIC and 6-lead SOT-23 packages. - Write-protect pin Pin Function Table • High Reliability: - Endurance: 1,000,000erase/write cycles Name Function - Data retention: >200 years CS Chip Select Input - ESD protection: >4000V • Temperature Ranges Supported: SO Serial Data Output - Industrial (I): -40C to +85C WP Write-Protect • Pb-Free and RoHS Compliant VSS Ground Package Types (not to scale) SI Serial Data Input SCK Serial Clock Input 6-Lead SOT-23 SOIC (OT) (SN) HOLD Hold Input VCC Supply Voltage SCK 1 6 VDD CS 1 8 VCC SO 2 7 HOLD VSS 2 5 CS WP 3 6 SCK SI 3 4 SO VSS 4 5 SI  2008-2018 Microchip Technology Inc. DS20002123G-page 1

25AA02E48/25AA02E64 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings(†) VCC.............................................................................................................................................................................6.5V All inputs and outputs w.r.t. VSS..........................................................................................................-0.6V to VCC +1.0V Storage temperature.................................................................................................................................-65°C to 150°C Ambient temperature under bias.................................................................................................................-40°C to 85°C ESD protection on all pins..........................................................................................................................................4kV † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an extended period of time may affect device reliability. TABLE 1-1: DC CHARACTERISTICS DC CHARACTERISTICS Industrial (I): TA = -40°C to +85°C VCC = 1.8V to 5.5V Param. Symbol Characteristic Min. Max. Units Test Conditions No. D1 VIH1 High-Level Input Voltage 0.7 VCC VCC +1 V D2 VIL1 Low-Level Input Voltage -0.3 0.3VCC V VCC2.7V (Note 1) D3 VIL2 Low-Level Input Voltage -0.3 0.2VCC V VCC < 2.7V (Note 1) D4 VOL Low-Level Output Voltage — 0.4 V IOL = 2.1mA D5 VOL Low-Level Output Voltage — 0.2 V IOL = 1.0mA, VCC < 2.5V D6 VOH High-Level Output Voltage VCC -0.5 — V IOH = -400µA D7 ILI Input Leakage Current — ±1 µA CS=VCC, VIN=VSS or VCC D8 ILO Output Leakage Current — ±1 µA CS = VCC, VOUT = VSS or VCC D9 CINT Internal Capacitance — 7 pF TA = 25°C, CLK = 1.0MHz, (all inputs and outputs) VCC=5.0V (Note 1) D10 ICCREAD Operating Current — 5 mA VCC = 5.5V; FCLK=10.0MHz, SO=Open — 2.5 mA VCC = 2.5V; FCLK=5.0MHz, SO=Open D11 ICCWRITE Operating Current — 5 mA VCC = 5.5V — 3 mA VCC = 2.5V D12 ICCS Standby Current — 1 µA CS = VCC = 2.5V, Inputs tied to VCC or VSS, TA = +85°C Note1: This parameter is periodically sampled and not 100% tested.  2008-2018 Microchip Technology Inc. DS20002123G-page 2

25AA02E48/25AA02E64 TABLE 1-2: AC CHARACTERISTICS AC CHARACTERISTICS Industrial (I): TA = -40°C to +85°C VCC = 1.8V to 5.5V Param. Symbol Characteristic Min. Max. Units Test Conditions No. 1 FCLK Clock Frequency — 10 MHz 4.5V VCC  5.5V — 5 MHz 2.5V VCC  4.5V — 3 MHz 1.8V VCC  2.5V 2 TCSS CS Setup Time 50 — ns 4.5V VCC  5.5V 100 — ns 2.5V VCC  4.5V 150 — ns 1.8V VCC  2.5V 3 TCSH CS Hold Time 100 — ns 4.5V VCC  5.5V 200 — ns 2.5V VCC  4.5V 250 — ns 1.8V VCC  2.5V 4 TCSD CS Disable Time 50 — ns 5 TSU Data Setup Time 10 — ns 4.5V VCC  5.5V 20 — ns 2.5V VCC  4.5V 30 — ns 1.8V VCC  2.5V 6 THD Data Hold Time 20 — ns 4.5V VCC  5.5V 40 — ns 2.5V VCC  4.5V 50 — ns 1.8V VCC  2.5V 7 TR CLK Rise Time — 100 ns Note1 8 TF CLK Fall Time — 100 ns Note1 9 THI Clock High Time 50 — ns 4.5V VCC  5.5V 100 — ns 2.5V VCC  4.5V 150 — ns 1.8V VCC  2.5V 10 TLO Clock Low Time 50 — ns 4.5V VCC  5.5V 100 — ns 2.5V VCC  4.5V 150 — ns 1.8V VCC  2.5V 11 TCLD Clock Delay Time 50 — ns 12 TCLE Clock Enable Time 50 — ns 13 TV Output Valid from Clock — 50 ns 4.5V VCC  5.5V Low — 100 ns 2.5V VCC  4.5V — 160 ns 1.8V VCC  2.5V 14 THO Output Hold Time 0 — ns Note1 Note1: This parameter is periodically sampled and not 100% tested. 2: TWC begins on the rising edge of CS after a valid write sequence and ends when the internal write cycle is complete. 3: This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total Endurance™ Model which can be obtained from Microchip’s website at www.microchip.com.  2008-2018 Microchip Technology Inc. DS20002123G-page 3

25AA02E48/25AA02E64 TABLE 1-2: AC CHARACTERISTICS (CONTINUED) AC CHARACTERISTICS Industrial (I): TA = -40°C to +85°C VCC = 1.8V to 5.5V Param. Symbol Characteristic Min. Max. Units Test Conditions No. 15 TDIS Output Disable Time — 40 ns 4.5V VCC  5.5V (Note1) — 80 ns 2.5V VCC  4.5V (Note1) — 160 ns 1.8V VCC  2.5V (Note1) 16 THS HOLD Setup Time 20 — ns 4.5V VCC  5.5V 40 — ns 2.5V VCC  4.5V 80 — ns 1.8V VCC  2.5V 17 THH HOLD Hold Time 20 — ns 4.5V VCC  5.5V 40 — ns 2.5V VCC  4.5V 80 — ns 1.8V VCC  2.5V 18 THZ HOLD Low to Output 30 — ns 4.5V VCC  5.5V (Note1) High-Z 60 — ns 2.5V VCC  4.5V (Note1) 160 — ns 1.8V VCC  2.5V (Note1) 19 THV HOLD High to Output 30 — ns 4.5V VCC  5.5V Valid 60 — ns 2.5V VCC  4.5V 160 — ns 1.8V VCC  2.5V 20 TWC Internal Write Cycle Time — 5 ms Note2 (byte or page) 21 Endurance 1M — E/W 25°C, VCC = 5.5V (Note3) cycles Note1: This parameter is periodically sampled and not 100% tested. 2: TWC begins on the rising edge of CS after a valid write sequence and ends when the internal write cycle is complete. 3: This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total Endurance™ Model which can be obtained from Microchip’s website at www.microchip.com. TABLE 1-3: AC TEST CONDITIONS AC Waveform VLO = 0.2V VHI = VCC - 0.2V Note 1 VHI = 4.0V Note 2 CL = 100pF Timing Measurement Reference Level Input 0.5 VCC Output 0.5 VCC Note1: For VCC  4.0V 2: For VCC  4.0V  2008-2018 Microchip Technology Inc. DS20002123G-page 4

25AA02E48/25AA02E64 FIGURE 1-1: HOLD TIMING CS 17 17 16 16 SCK 18 19 High-Impedance SO n + 2 n + 1 n n n - 1 Don’t Care 5 SI n + 2 n + 1 n n n - 1 HOLD FIGURE 1-2: SERIAL INPUT TIMING 4 CS 12 2 11 7 Mode 1,1 8 3 SCK Mode 0,0 5 6 SI MSB In LSB In High-Impedance SO FIGURE 1-3: SERIAL OUTPUT TIMING CS 9 10 3 Mode 1,1 SCK Mode 0,0 13 15 14 SO MSB Out ISB Out Don’t Care SI  2008-2018 Microchip Technology Inc. DS20002123G-page 5

25AA02E48/25AA02E64 2.0 FUNCTIONAL DESCRIPTION After setting the write enable latch, the user may proceed by driving CS low, issuing a WRITE instruction, followed by the remainder of the address, and then the 2.1 Principles of Operation data to be written. Up to 16 bytes of data can be sent to The 25AA02EXX is a 256-byte Serial EEPROM the device before a write cycle is necessary. The only designed to interface directly with the Serial Peripheral restriction is that all of the bytes must reside in the Interface (SPI) port of many of today’s popular same page. Additionally, a page address begins with microcontroller families, including Microchip’s PIC® XXXX 0000 and ends with XXXX 1111. If the internal microcontrollers. It may also interface with address counter reaches XXXX 1111 and clock signals microcontrollers that do not have a built-in SPI port by continue to be applied to the chip, the address counter using discrete I/O lines programmed properly in will roll back to the first address of the page and software to match the SPI protocol. over-write any data that previously existed in those locations. The 25AA02EXX contains an 8-bit instruction register. The device is accessed via the SI pin, with data being Note: Page write operations are limited to clocked in on the rising edge of SCK. The CS pin must writing bytes within a single physical page, be low and the HOLD pin must be high for the entire regardless of the number of bytes operation. actually being written. Physical page Table2-1 contains a list of the possible instruction boundaries start at addresses that are bytes and format for device operation. All instructions, integer multiples of the page buffer size addresses, and data are transferred MSb first, LSb last. (or ‘page size’) and, end at addresses that are integer multiples of page size – 1. If a Data (SI) is sampled on the first rising edge of SCK Page Write command attempts to write after CS goes low. If the clock line is shared with other across a physical page boundary, the peripheral devices on the SPI bus, the user can assert result is that the data wraps around to the the HOLD input and place the 25AA02EXX in ‘HOLD’ beginning of the current page (overwriting mode. After releasing the HOLD pin, operation will data previously stored there), instead of resume from the point when the HOLD was asserted. being written to the next page as might be expected. It is, therefore, necessary for 2.2 Read Sequence the application software to prevent page write operations that would attempt to The device is selected by pulling CS low. The 8-bit cross a page boundary. READ instruction is transmitted to the 25AA02EXX followed by an 8-bit address. See Figure2-1 for more details. For the data to be actually written to the array, the CS must be brought high after the Least Significant bit (D0) After the correct READ instruction and address are sent, of the nth data byte has been clocked in. If CS is driven the data stored in the memory at the selected address high at any other time, the write operation will not be is shifted out on the SO pin. Data stored in the memory completed. Refer to Figure2-2 and Figure2-3 for more at the next address can be read sequentially by detailed illustrations on the byte write sequence and continuing to provide clock pulses to the slave. The the page write sequence, respectively. While the write internal Address Pointer automatically increments to is in progress, the STATUS register may be read to the next higher address after each byte of data is check the status of the WIP, WEL, BP1 and BP0 bits shifted out. When the highest address is reached (Figure2-6). Attempting to read a memory array (FFh), the address counter rolls over to address 00h location will not be possible during a write cycle. Polling allowing the read cycle to be continued indefinitely. The the WIP bit in the STATUS register is recommended in read operation is terminated by raising the CS pin order to determine if a write cycle is in progress. When (Figure2-1). the write cycle is completed, the write enable latch is reset. 2.3 Write Sequence Prior to any attempt to write data to the 25AA02EXX, the write enable latch must be set by issuing the WREN instruction (Figure2-4). This is done by setting CS low and then clocking out the proper instruction into the 25AA02EXX. After all eight bits of the instruction are transmitted, CS must be driven high to set the write enable latch. If the write operation is initiated immediately after the WREN instruction without CS driven high, data will not be written to the array since the write enable latch was not properly set.  2008-2018 Microchip Technology Inc. DS20002123G-page 6

25AA02E48/25AA02E64 BLOCK DIAGRAM STATUS HV Generator Register EEPROM I/O Control Memory X Array Control Logic Logic Dec Page Latches SI SO Y Decoder CS SCK Sense Amp. HOLD R/W Control WP VCC VSS TABLE 2-1: INSTRUCTION SET Instruction Name Instruction Format Description READ 0000 x011 Read data from memory array beginning at selected address WRITE 0000 x010 Write data to memory array beginning at selected address WRDI 0000 x100 Reset the write enable latch (disable write operations) WREN 0000 x110 Set the write enable latch (enable write operations) RDSR 0000 x101 Read STATUS register WRSR 0000 x001 Write STATUS register x = don’t care FIGURE 2-1: READ SEQUENCE CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 SCK Instruction Address Byte SI 0 0 0 0 0 0 1 1 A7 A6 A5 A4 A3 A2 A1 A0 Data Out High-Impedance SO 7 6 5 4 3 2 1 0  2008-2018 Microchip Technology Inc. DS20002123G-page 7

25AA02E48/25AA02E64 FIGURE 2-2: BYTE WRITE SEQUENCE CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Twc SCK Instruction Address Byte Data Byte SI 0 0 0 0 0 0 1 0 A7 A6 A5 A4 A3 A2 A1 A0 7 6 5 4 3 2 1 0 High-Impedance SO FIGURE 2-3: PAGE WRITE SEQUENCE CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 SCK Instruction Address Byte Data Byte 1 SI 0 0 0 0 0 0 1 0 A7 A6 A5 A4 A3 A2 A1 A0 7 6 5 4 3 2 1 0 CS 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 SCK Data Byte 2 Data Byte 3 Data Byte n (16 max) SI 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0  2008-2018 Microchip Technology Inc. DS20002123G-page 8

25AA02E48/25AA02E64 2.4 Write Enable (WREN) and Write The following is a list of conditions under which the Disable (WRDI) write enable latch will be reset: • Power-up The 25AA02EXX contains a write enable latch. See • WRDI instruction successfully executed Table2-4 for the Write-Protect Functionality Matrix. This latch must be set before any write operation will be • WRSR instruction successfully executed completed internally. The WREN instruction will set the • WRITE instruction successfully executed latch, and the WRDI will reset the latch. • WP pin is brought low FIGURE 2-4: WRITE ENABLE SEQUENCE (WREN) CS 0 1 2 3 4 5 6 7 SCK SI 0 0 0 0 0 1 1 0 High-Impedance SO FIGURE 2-5: WRITE DISABLE SEQUENCE (WRDI) CS 0 1 2 3 4 5 6 7 SCK SI 0 0 0 0 0 1 0 0 High-Impedance SO  2008-2018 Microchip Technology Inc. DS20002123G-page 9

25AA02E48/25AA02E64 2.5 Read Status Register Instruction The Write Enable Latch (WEL) bit indicates the status (RDSR) of the write enable latch and is read-only. When set to a ‘1’, the latch allows writes to the array, when set to a The Read Status Register instruction (RDSR) provides ‘0’, the latch prohibits writes to the array. The state of access to the STATUS register. See Figure2-6 for the this bit can always be updated via the WREN or WRDI RDSR timing sequence. The STATUS register may be commands regardless of the state of write protection read at any time, even during a write cycle. The on the STATUS register. These commands are shown STATUS register is formatted as follows: in Figure2-4 and Figure2-5. The Block Protection (BP0 and BP1) bits indicate TABLE 2-2: STATUS REGISTER which blocks are currently write-protected. These bits 7 6 5 4 3 2 1 0 are set by the user issuing the WRSR instruction, which is shown in Figure2-7. These bits are nonvolatile and – – – – W/R W/R R R are described in more detail in Table2-3. X X X X BP1 BP0 WEL WIP W/R = writable/readable. R = read-only. The Write-In-Process (WIP) bit indicates whether the 25AA02EXX is busy with a write operation. When set to a ‘1’, a write is in progress, when set to a ‘0’, no write is in progress. This bit is read-only. FIGURE 2-6: READ STATUS REGISTER TIMING SEQUENCE (RDSR) CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCK Instruction SI 0 0 0 0 0 1 0 1 Data from STATUS register High-Impedance SO 7 6 5 4 3 2 1 0  2008-2018 Microchip Technology Inc. DS20002123G-page 10

25AA02E48/25AA02E64 2.6 Write Status Register Instruction TABLE 2-3: ARRAY PROTECTION (WRSR) Array Addresses BP1 BP0 Write-Protected The Write Status Register instruction (WRSR) allows the user to write to the nonvolatile bits in the STATUS 0 0 none register as shown in Table2-2. See Figure2-7 for the 0 1 upper 1/4 WRSR timing sequence. Four levels of protection for (C0h-FFh) the array are selectable by writing to the appropriate bits in the STATUS register. The user has the ability to 1 0 upper 1/2 write-protect none, one, two, or all four of the (80h-FFh) segments of the array as shown in Table2-3. 1 1 all (00h-FFh) FIGURE 2-7: WRITE STATUS REGISTER TIMING SEQUENCE (WRSR) CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCK Instruction Data to STATUS register SI 0 0 0 0 0 0 0 1 7 6 5 4 3 2 1 0 High-Impedance SO  2008-2018 Microchip Technology Inc. DS20002123G-page 11

25AA02E48/25AA02E64 2.7 Data Protection 2.8 Power-On State The following protection has been implemented to The 25AA02EXX powers on in the following state: prevent inadvertent writes to the array: • The device is in low-power Standby mode • The write enable latch is reset on power-up (CS=1) • A write enable instruction must be issued to set • The write enable latch is reset the write enable latch • SO is in high-impedance state • After a byte write, page write or STATUS register • A high-to-low-level transition on CS is required to write, the write enable latch is reset enter active state • CS must be set high after the proper number of clock cycles to start an internal write cycle • Access to the array during an internal write cycle is ignored and programming is continued TABLE 2-4: WRITE-PROTECT FUNCTIONALITY MATRIX WP WEL Protected Blocks Unprotected Blocks STATUS Register (pin 3) (SR bit 1) 0 (low) x Protected Protected Protected 1 (high) 0 Protected Protected Protected 1 (high) 1 Protected Writable Writable x = don’t care  2008-2018 Microchip Technology Inc. DS20002123G-page 12

25AA02E48/25AA02E64 3.0 PREPROGRAMMED EUI-48™ 3.2 EUI-48™ Node Address OR EUI-64™ NODE ADDRESS (25AA02E48) The 25AA02EXX is programmed at the factory with a The 6-byte EUI-48™ node address value of the globally unique node address stored in the upper 1/4 of 25AA02E48 is stored in array locations 0xFA through the array and write-protected through the STATUS 0xFF, as shown in Figure3-2. The first three bytes are register. The remaining 1,536 bits are available for the Organizationally Unique Identifier (OUI) assigned application use. to Microchip by the IEEE Registration Authority. The remaining three bytes are the Extension Identifier, and FIGURE 3-1: MEMORY ORGANIZATION are generated by Microchip to ensure a globally unique, 48-bit value. 00h 3.2.1 ORGANIZATIONALLY UNIQUE Standard IDENTIFIERS (OUIs) EEPROM Each OUI provides roughly 16M (224) addresses. Once the address pool for an OUI is exhausted, Microchip C0h will acquire a new OUI from IEEE to use for Write-Protected Node Address Block programming this model. For more information on past FFh and current OUIs see “Organizationally Unique Identifiers For Preprogrammed EUI-48 and EUI-64 3.1 Factory-Programmed Write Address Devices” Technical Brief (DS90003187). Protection Note: The OUI will change as addresses are In order to help guard against accidental corruption of exhausted. Customers are not guaran- the node address, the BP1 and BP0 bits of the STATUS teed to receive a specific OUI and should register are programmed at the factory to ‘0’ and ‘1’, design their application to accept new respectively, as shown in the following table: OUIs as they are introduced. 7 6 5 4 3 2 1 0 3.2.2 EUI-64™ SUPPORT USING THE X X X X BP1 BP0 WEL WIP 25AA02E48 — — — — 0 1 — — The preprogrammed EUI-48 node address of the This protects the upper 1/4 of the array (0xC0 to 0xFF) 25AA02E48 can easily be encapsulated at the from write operations. This array block can be utilized application level to form a globally unique, 64-bit node for writing by clearing the BP bits with a Write Status address for systems utilizing the EUI-64 standard. This Register (WRSR) instruction. Note that if this is is done by adding 0xFFFE between the OUI and the performed, care must be taken to prevent overwriting Extension Identifier, as shown below. the node address value. Note: As an alternative, the 25AA02E64 features an EUI-64 node address that can be used in EUI-64 applications directly without the need for encapsulation, thereby simplifying system software. See Section3.3 “EUI-64™ Node Address (25AA02E64)” for details.  2008-2018 Microchip Technology Inc. DS20002123G-page 13

25AA02E48/25AA02E64 FIGURE 3-2: EUI-48 NODE ADDRESS PHYSICAL MEMORY MAP EXAMPLE (25AA02E48) 24-bit Organizationally 24-bit Extension Description Unique Identifier Identifier Data 00h 04h A3h 12h 34h 56h Array FAh FFh Address Corresponding EUI-48™ Node Address: 00-04-A3-12-34-56 Corresponding EUI-64™ Node Address After Encapsulation: 00-04-A3-FF-FE-12-34-56  2008-2018 Microchip Technology Inc. DS20002123G-page 14

25AA02E48/25AA02E64 3.3 EUI-64™ Node Address (25AA02E64) The 8-byte EUI-64™ node address value of the 25AA02E64 is stored in array locations 0xF8 through 0xFF, as shown in Figure3-3. The first three bytes are the Organizationally Unique Identifier (OUI) assigned to Microchip by the IEEE Registration Authority. The remaining five bytes are the Extension Identifier, and are generated by Microchip to ensure a globally unique, 64-bit value. Note: In conformance with IEEE guidelines, Microchip will not use the values 0xFFFE and 0xFFFF for the first two bytes of the EUI-64 Extension Identifier. These two values are specifically reserved to allow applications to encapsulate EUI-48 addresses into EUI-64 addresses. FIGURE 3-3: EUI-64 NODE ADDRESS PHYSICAL MEMORY MAP EXAMPLE (25AA02E64) 24-bit Organizationally 40-bit Extension Description Unique Identifier Identifier Data 00h 04h A3h 12h 34h 56h 78h 90h Array F8h FFh Address Corresponding EUI-64™ Node Address: 00-04-A3-12-34-56-78-90  2008-2018 Microchip Technology Inc. DS20002123G-page 15

25AA02E48/25AA02E64 4.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table4-1. TABLE 4-1: PIN FUNCTION TABLE Name SOIC SOT-23 Function CS 1 5 Chip Select Input SO 2 4 Serial Data Output WP 3 — Write-Protect Pin VSS 4 2 Ground SI 5 3 Serial Data Input SCK 6 1 Serial Clock Input HOLD 7 — Hold Input VCC 8 6 Supply Voltage 4.1 Chip Select (CS) 4.5 Serial Clock (SCK) A low level on this pin selects the device. A high level The SCK is used to synchronize the communication deselects the device and forces it into Standby mode. between a master and the 25AA02EXX. Instructions, However, a programming cycle which is already addresses or data present on the SI pin are latched on initiated or in progress will be completed, regardless of the rising edge of the clock input, while data on the SO the CS input signal. If CS is brought high during a pin is updated after the falling edge of the clock input. program cycle, the device will go into Standby mode as soon as the programming cycle is complete. When the 4.6 Hold (HOLD) device is deselected, SO goes to the high-impedance The HOLD pin is used to suspend transmission to the state, allowing multiple parts to share the same SPI 25AA02EXX while in the middle of a serial sequence bus. A low-to-high transition on CS after a valid write without having to retransmit the entire sequence again. sequence initiates an internal write cycle. After It must be held high any time this function is not being power-up, a low level on CS is required prior to any used. Once the device is selected and a serial sequence being initiated. sequence is underway, the HOLD pin may be pulled 4.2 Serial Output (SO) low to pause further serial communication without resetting the serial sequence. The HOLD pin must be The SO pin is used to transfer data out of the brought low while SCK is low, otherwise the HOLD 25AA02EXX. During a read cycle, data is shifted out on function will not be invoked until the next SCK this pin after the falling edge of the serial clock. high-to-low transition. The 25AA02EXX must remain selected during this sequence. The SI, SCK and SO 4.3 Write-Protect (WP) pins are in a high-impedance state during the time the device is paused and transitions on these pins will be The WP pin is a hardware write-protect input pin. ignored. To resume serial communication, HOLD must When it is low, all writes to the array or STATUS be brought high while the SCK pin is low, otherwise register are disabled, but any other operations serial communication will not resume. Lowering the function normally. When WP is high, all functions, HOLD line at any time will tri-state the SO line. including nonvolatile writes, operate normally. At any time when WP is low, the write enable Reset latch will be reset and programming will be inhibited. However, if a write cycle is already in progress, WP going low will not change or disable the write cycle. See Table2-4 for the Write-Protect Functionality Matrix. 4.4 Serial Input (SI) The SI pin is used to transfer data into the device. It receives instructions, addresses and data. Data is latched on the rising edge of the serial clock.  2008-2018 Microchip Technology Inc. DS20002123G-page 16

25AA02E48/25AA02E64 5.0 PACKAGING INFORMATION 5.1 Package Marking Information* 8-Lead SOIC Example XXXXXXXT 25A2E48I XXXXYYWW SN e 3 1627 NNN 1L7 6-Lead SOT-23 (25AA02E48) Example XXNN 20L7 6-Lead SOT-23 (25AA02E64) Example XXXXY AAAA6 WWNNN 271L7 1st Line Marking Code Part Number SOIC SOT-23 25AA02E48 25A2E48I 20NN 25AA02E64 25A2E64I AAAAY Legend: XX...X Part number or part number code T Temperature (I, E) Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code (2 characters for small packages) e3 Pb-free** JEDEC® designator for Matte Tin (Sn) * Standard OTP marking consists of Microchip part number, year code, week code, and traceability code. ** Please visit www.microchip.com/Pbfree for the latest information on Pb-free conversion. Note: For very small packages with no room for the Pb-free JEDEC designator e 3 , the marking will only appear on the outer carton or reel label. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2008-2018 Microchip Technology Inc. DS20002123G-page 17

25AA02E48/25AA02E64 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2X 0.10 C A–B D A D NOTE 5 N E 2 E1 2 E1 E NOTE 1 1 2 e NX b B 0.25 C A–B D NOTE 5 TOP VIEW 0.10 C C A A2 SEATING PLANE 8X 0.10 C A1 SIDE VIEW h R0.13 h R0.13 H 0.23 L SEE VIEW C (L1) VIEW A–A VIEW C Microchip Technology Drawing No. C04-057-SN Rev D Sheet 1 of 2  2008-2018 Microchip Technology Inc. DS20002123G-page 18

25AA02E48/25AA02E64 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Pins N 8 Pitch e 1.27 BSC Overall Height A - - 1.75 Molded Package Thickness A2 1.25 - - Standoff § A1 0.10 - 0.25 Overall Width E 6.00 BSC Molded Package Width E1 3.90 BSC Overall Length D 4.90 BSC Chamfer (Optional) h 0.25 - 0.50 Foot Length L 0.40 - 1.27 Footprint L1 1.04 REF Foot Angle 0° - 8° Lead Thickness c 0.17 - 0.25 Lead Width b 0.31 - 0.51 Mold Draft Angle Top 5° - 15° Mold Draft Angle Bottom 5° - 15° Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. 5. Datums A & B to be determined at Datum H. Microchip Technology Drawing No. C04-057-SN Rev D Sheet 2 of 2  2008-2018 Microchip Technology Inc. DS20002123G-page 19

25AA02E48/25AA02E64 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging SILK SCREEN C Y1 X1 E RECOMMENDED LAND PATTERN Units MILLIMETERS Dimension Limits MIN NOM MAX Contact Pitch E 1.27 BSC Contact Pad Spacing C 5.40 Contact Pad Width (X8) X1 0.60 Contact Pad Length (X8) Y1 1.55 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing C04-2057-SN Rev B  2008-2018 Microchip Technology Inc. DS20002123G-page 20

25AA02E48/25AA02E64 6-Lead Plastic Small Outline Transistor (OT, OTY) [SOT-23] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2X 0.15 C A-B D e1 A D E 2 E1 E E1 2 2X 0.15 C D 2X 0.20 C A-B e B 6X b 0.20 C A-B D TOP VIEW A2 A C SEATING PLANE 6X A1 0.10 C SIDE VIEW R1 R L2 c GAUGE PLANE L (cid:300) (L1) END VIEW Microchip Technology Drawing C04-028C (OT) Sheet 1 of 2  2008-2018 Microchip Technology Inc. DS20002123G-page 21

25AA02E48/25AA02E64 6-Lead Plastic Small Outline Transistor (OT, OTY) [SOT-23] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Leads N 6 Pitch e 0.95 BSC Outside lead pitch e1 1.90 BSC Overall Height A 0.90 - 1.45 Molded Package Thickness A2 0.89 1.15 1.30 Standoff A1 0.00 - 0.15 Overall Width E 2.80 BSC Molded Package Width E1 1.60 BSC Overall Length D 2.90 BSC Foot Length L 0.30 0.45 0.60 Footprint L1 0.60 REF Seating Plane to Gauge Plane L1 0.25 BSC φ Foot Angle 0° - 10° Lead Thickness c 0.08 - 0.26 Lead Width b 0.20 - 0.51 Notes: 1. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25mm per side. 2. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-028C (OT) Sheet 2 of 2  2008-2018 Microchip Technology Inc. DS20002123G-page 22

25AA02E48/25AA02E64 6-Lead Plastic Small Outline Transistor (OT, OTY) [SOT-23] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging GX Y Z C G G SILK SCREEN X E RECOMMENDED LAND PATTERN Units MILLIMETERS Dimension Limits MIN NOM MAX Contact Pitch E 0.95 BSC Contact Pad Spacing C 2.80 Contact Pad Width (X3) X 0.60 Contact Pad Length (X3) Y 1.10 Distance Between Pads G 1.70 Distance Between Pads GX 0.35 Overall Width Z 3.90 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing No. C04-2028B (OT)  2008-2018 Microchip Technology Inc. DS20002123G-page 23

25AA02E48/25AA02E64 APPENDIX A: REVISION HISTORY Revision A (12/08) Initial release of this document. Revision B (04/10) Removed Preliminary status; Revised Section 2.0; Add sentence to Section 3.0; Add SOT-23 Land Pattern. Revision C (12/2012) Revised Table 1-2, Parameter 21. Revision D (4/2013) Added 25AA02E64 part number. Revision E (01/2015) Updated Section 3.0; Updated Product Identification System. Revision F (07/2016) Added new OUI (54-10-EC) to list. Revision G (02/2018) Added detailed description of OUIs.  2008-2018 Microchip Technology Inc. DS20002123G-page 24

25AA02E48/25AA02E64 THE MICROCHIP WEBSITE CUSTOMER SUPPORT Microchip provides online support via our website at Users of Microchip products can receive assistance www.microchip.com. This website is used as a means through several channels: to make files and information easily available to • Distributor or Representative customers. Accessible by using your favorite Internet • Local Sales Office browser, the website contains the following information: • Field Application Engineer (FAE) • Product Support – Data sheets and errata, • Technical Support application notes and sample programs, design resources, user’s guides and hardware support Customers should contact their distributor, documents, latest software releases and archived representative or Field Application Engineer (FAE) for software support. Local sales offices are also available to help customers. A listing of sales offices and locations is • General Technical Support – Frequently Asked included in the back of this document. Questions (FAQ), technical support requests, online discussion groups, Microchip consultant Technical support is available through the website program member listing at: http://microchip.com/support • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip website at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions.  2008-2018 Microchip Technology Inc. DS20002123G-page 25

25AA02E48/25AA02E64 NOTES:  2008-2018 Microchip Technology Inc. DS20002123G-page 26

25AA02E48/25AA02E64 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. [X]((11)) X /XX Examples: a) 25AA02E48-I/SN = 2Kbit, 16-byte page, 1.8V Device Tape and Reel Temperature Package Serial EEPROM with EUI-48 Option Range Node Identity, Industrial tem- perature, SOIC package. b) 25AA02E48T-I/SN = 2Kbit, 16-byte page, 1.8V Device: 25AA02E48 = 2Kbit, 1.8V, 16-Byte Page, SPI Serial EEPROM Serial EEPROM with EUI-48 with EUI-48™ Node Identity Node Identity, Tape & Reel, Industrial temp., 25AA02E64 = 2Kbit, 1.8V, 16-Byte Page, SPI Serial EEPROM SOIC package. with EUI-64™ Node Identity c) 25AA02E48T-I/OT = 2Kbit, 16-byte page, 1.8V Serial EEPROM with EUI-48 Tape and Reel Blank = Standard packaging (tube or tray) Node Identity, Tape & Reel, Option: T = Tape and Reel(1) Industrial temp., SOT-23 package. d) 25AA02E64-I/SN = 2Kbit, 16-byte page, 1.8V Temperature I = -40C to+85C Serial EEPROM with EUI-64 Range: Node Identity, Industrial temp., SOIC package. e) 25AA02E64T-I/SN = 2Kbit, 16-byte page, 1.8V Package: SN = Plastic SOIC (3.90 mm body), 8-lead Serial EEPROM with EUI-64 OT = SOT-23, 6-lead (Tape and Reel only) Node Identity, Tape & Reel, Industrial temp., SOIC pack- age. f) 25AA02E64T-I/OT = 2Kbit, 16-byte page, 1.8V Serial EEPROM with EUI-64 Node Identity, Tape & Reel, Industrial temp., SOT-23 package. Note 1: Tape and Reel identifier only appears in the catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. Check with your Microchip Sales Office for package availability with the Tape and Reel option.  2008-2018 Microchip Technology Inc. DS20002123G-page 27

25AA02E48/25AA02E64 NOTES:  2008-2018 Microchip Technology Inc. DS20002123G-page 28

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, AnyRate, AVR, and may be superseded by updates. It is your responsibility to AVR logo, AVR Freaks, BeaconThings, BitCloud, chipKIT, chipKIT ensure that your application meets with your specifications. logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, MICROCHIP MAKES NO REPRESENTATIONS OR Heldo, JukeBlox, KEELOQ, KEELOQ logo, Kleer, LANCheck, LINK WARRANTIES OF ANY KIND WHETHER EXPRESS OR MD, maXStylus, maXTouch, MediaLB, megaAVR, MOST, MOST IMPLIED, WRITTEN OR ORAL, STATUTORY OR logo, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, PIC32 OTHERWISE, RELATED TO THE INFORMATION, logo, Prochip Designer, QTouch, RightTouch, SAM-BA, SpyNIC, INCLUDING BUT NOT LIMITED TO ITS CONDITION, SST, SST Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are QUALITY, PERFORMANCE, MERCHANTABILITY OR registered trademarks of Microchip Technology Incorporated in FITNESS FOR PURPOSE. Microchip disclaims all liability the U.S.A. and other countries. arising from this information and its use. Use of Microchip ClockWorks, The Embedded Control Solutions Company, devices in life support and/or safety applications is entirely at EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS, the buyer’s risk, and the buyer agrees to defend, indemnify and mTouch, Precision Edge, and Quiet-Wire are registered hold harmless Microchip from any and all damages, claims, trademarks of Microchip Technology Incorporated in the U.S.A. suits, or expenses resulting from such use. No licenses are Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any conveyed, implicitly or otherwise, under any Microchip Capacitor, AnyIn, AnyOut, BodyCom, CodeGuard, intellectual property rights unless otherwise stated. CryptoAuthentication, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, Inter- Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, Mindi, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PureSilicon, QMatrix, RightTouch logo, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Silicon Storage Technology is a registered trademark of Microchip Tempe, Arizona; Gresham, Oregon and design centers in California Technology Inc. in other countries. and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping GestIC is a registered trademark of Microchip Technology devices, Serial EEPROMs, microperipherals, nonvolatile memory and Germany II GmbH & Co. KG, a subsidiary of Microchip Technology analog products. In addition, Microchip’s quality system for the design Inc., in other countries. and manufacture of development systems is ISO 9001:2000 certified. All other trademarks mentioned herein are property of their respective companies. QUALITY MANAGEMENT SYSTEM © 2008-2018, Microchip Technology Incorporated, All Rights Reserved. CERTIFIED BY DNV ISBN: 978-1-5224-2725-4 == ISO/TS 16949 ==  2008-2018 Microchip Technology Inc. DS20002123G-page 29

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