24AA65/24LC65/24C65 2 64K I C™ Smart Serial™ EEPROM Device Selection Table Part Number VCC Range Page Size Temp. Ranges Packages 24AA65 1.8-6.0V 64 Bytes C P, SM 24LC65 2.5-6.0V 64 Bytes C, I P, SM 24C65 4.5-6.0V 64 Bytes C, I, E P, SM Features Description • Voltage operating range: 1.8V to 6.0V The Microchip Technology Inc. 24AA65/24LC65/ - Peak write current 3 mA at 6.0V 24C65 (24XX65)* is a “smart” 8K x 8 Serial Electrically - Maximum read current 150 µA at 6.0V Erasable PROM. This device has been developed for advanced, low-power applications such as personal - Standby current 1 µA typical communications, and provides the systems designer (cid:127) Industry standard two-wire bus protocol I 2C™ with flexibility through the use of many new user-pro- compatible grammable features. The 24XX65 offers a relocatable (cid:127) 8-byte page, or byte modes available 4K bit block of ultra-high-endurance memory for data (cid:127) 2 ms typical write cycle time, byte or page that changes frequently. The remainder of the array, or (cid:127) 64-byte input cache for fast write loads 60K bits, is rated at 1,000,000 erase/write (E/W) cycles ensured. The 24XX65 features an input cache for fast (cid:127) Up to 8 devices may be connected to the same write loads with a capacity of eight pages, or 64 bytes. bus for up to 512K bits total memory This device also features programmable security (cid:127) Including 100 kHz (1.8V ≤ Vcc < 4.5V) and 400 options for E/W protection of critical data and/or code kHz (4.5V ≤ VCC ≤ 6.0V) compatibility of up to fifteen 4K blocks. Functional address lines (cid:127) Programmable block security options allow the connection of up to eight 24XX65's on the (cid:127) Programmable endurance options same bus for up to 512K bits contiguous EEPROM (cid:127) Schmitt Trigger, filtered inputs for noise memory. Advanced CMOS technology makes this suppression device ideal for low-power nonvolatile code and data applications. The 24XX65 is available in the standard (cid:127) Output slope control to eliminate ground bounce 8-pin plastic DIP and 8-pin surface mount SOIC (cid:127) Self-timed erase and write cycles package. (cid:127) Power-on/off data protection circuitry (cid:127) Endurance: Package Types - 10,000,000 E/W cycles for a High Endurance Block PDIP A0 1 8 VCC - 1,000,000 E/W cycles for a Standard Endurance Block A1 2 2 7 NC 4 X (cid:127) Electrostatic discharge protection > 4000V X A2 3 6 6 SCL (cid:127) Data retention > 200 years 5 (cid:127) 8-pin PDIP/SOIC packages VSS 4 5 SDA (cid:127) Temperature ranges - Commercial (C): 0°C to +70°C SOIC - Industrial (I) -40°C to +85°C A0 1 8 VCC - Automotive (E) -40°C to +125°C A1 2 24 7 NC X X A2 3 65 6 SCL VSS 4 5 SDA *24XX65 is used in this document as a generic part number for the 24AA65/24LC65/24C65 devices.  2003 Microchip Technology Inc. DS21073J-page 1

24AA65/24LC65/24C65 Block Diagram Pin Function Table A0A1A2 HV Generator Name Function A0, A1, A2 User Configurable Chip Selects VSS Ground I/O Memory EEPROM SDA Serial Address/Data/I/O Control Control XDEC Array Logic Logic SCL Serial Clock Page Latches VCC +1.8V to 6.0V Power Supply NC No Internal Connection I/O SCL Cache SDA YDEC VCC VSS Sense Amp. R/W Control DS21073J-page 2  2003 Microchip Technology Inc.

24AA65/24LC65/24C65 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings(†) VCC.............................................................................................................................................................................7.0V All inputs and outputs w.r.t. VSS..........................................................................................................-0.6V to VCC +1.0V Storage temperature...............................................................................................................................-65°C to +150°C Ambient temperature with power applied................................................................................................-65°C to +125°C ESD protection on all pins......................................................................................................................................................≥ 4 kV † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an extended period of time may affect device reliability. TABLE 1-1: DC CHARACTERISTICS VCC = +1.8V to +6.0V Commercial (C): TA = 0°C to +70°C DC CHARACTERISTICS Industrial (I): TA = -40°C to +85°C Automotive (E): TA = -40°C to +125°C Parameter Sym Min Max Units Conditions A0, A1, A2, SCL and SDA pins: High-level input voltage VIH .7 VCC — V Low-level input voltage VIL — .3 VCC V Hysteresis of Schmitt Trigger inputs VHYS .05 VCC — V (Note 1) Low-level output voltage VOL — .40 V IOL = 3.0 mA Input leakage current ILI — ±1 µA VIN = .1V to VCC Output leakage current ILO — ±1 µA VOUT = .1V to VCC Pin capacitance CIN, COUT — 10 pF VCC = 5.0V (Note 1) (all inputs/outputs) TA = 25°C, FCLK = 1 MHz Operating current ICC Write — 3 mA VCC = 6.0V, SCL = 400 kHz ICC Read — 150 µA VCC = 6.0V, SCL = 400 kHz Standby current ICCS — 5 µA VCC = 5.0V, SCL = SDA = VCC A0, A1, A2 = VSS Note 1: This parameter is periodically sampled and not 100% tested. FIGURE 1-1: BUS TIMING START/STOP VHYS SCL THD:STA TSU:STA TSU:STO SDA START STOP  2003 Microchip Technology Inc. DS21073J-page 3

24AA65/24LC65/24C65 TABLE 1-2: AC CHARACTERISTICS VCC = 1.8V-6.0V VCC = 4.5-6.0V Parameter Symbol STD. Mode FAST Mode Units Remarks Min Max Min Max Clock frequency FCLK — 100 — 400 kHz Clock high time THIGH 4000 — 600 — ns Clock low time TLOW 4700 — 1300 — ns SDA and SCL rise time TR — 1000 — 300 ns (Note 1) SDA and SCL fall time TF — 300 — 300 ns (Note 1) Start condition setup time THD:STA 4000 — 600 — ns After this period the first clock pulse is generated Start condition setup time TSU:STA 4700 — 600 — ns Only relevant for repeated Start condition Data input hold time THD:DAT 0 — 0 — ns Data input setup time TSU:DAT 250 — 100 — ns Stop condition setup time TSU:STO 4000 — 600 — ns Output valid from clock TAA — 3500 — 900 ns (Note 2) Bus free time TBUF 4700 — 1300 — ns Time the bus must be free before a new transmission can start Output fall time from VIH min to TOF — 250 20 + 0.1 250 ns (Note 1), CB ≤ 100 pF VIL max CB Input filter spike suppression TSP 50 — 50 — ns (Note 3) (SDA and SCL pins) Write cycle time TWR — 5 — 5 ms/page (Note 4) Endurance High Endurance Block 10M — 10M — cycles 25°C, (Note5) Rest of Array 1M — 1M — Note 1: Not 100 percent tested. CB = total capacitance of one bus line in pF. 2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. 3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs which provide improved noise and spike suppression. This eliminates the need for a Ti specification for standard operation. 4: The times shown are for a single page of 8 bytes. Multiply by the number of pages loaded into the write cache for total time. 5: This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total Endurance™ Model which can be downloaded at www.microchip.com. FIGURE 1-2: BUS TIMING DATA TF TR THIGH TLOW SCL TSU:STA THD:DAT TSU:DAT TSU:STO THD:STA SDA IN TSP TBUF TAA TAA SDA OUT DS21073J-page 4  2003 Microchip Technology Inc.

24AA65/24LC65/24C65 2.0 FUNCTIONAL DESCRIPTION 3.3 Stop Data Transfer (C) The 24XX65 supports a bidirectional two-wire bus and A low-to-high transition of the SDA line while the clock data transmission protocol. A device that sends data (SCL) is high determines a Stop condition. All onto the bus is defined as transmitter, and a device operations must be ended with a Stop condition. receiving data as receiver. The bus must be controlled by a master device which generates the serial clock 3.4 Data Valid (D) (SCL), controls the bus access and generates the Start and Stop conditions, while the 24XX65 works as slave. The state of the data line represents valid data when, after a Start condition, the data line is stable for the Both master and slave can operate as transmitter or receiver, but the master device determines which mode duration of the high period of the clock signal. is activated. The data on the line must be changed during the low period of the clock signal. There is one clock pulse per 3.0 BUS CHARACTERISTICS bit of data. Each data transfer is initiated with a Start condition and The following bus protocol has been defined: terminated with a Stop condition. The number of the (cid:127) Data transfer may be initiated only when the bus data bytes transferred between the Start and Stop is not busy. conditions is determined by the master device. (cid:127) During data transfer, the data line must remain stable whenever the clock line is high. Changes in 3.5 Acknowledge the data line while the clock line is high will be Each receiving device, when addressed, is obliged to interpreted as a Start or Stop condition. generate an acknowledge after the reception of each Accordingly, the following bus conditions have been byte. The master device must generate an extra clock defined (Figure3-1). pulse which is associated with this Acknowledge bit. 3.1 Bus not Busy (A) Note: The 24XX65 does not generate any Acknowledge bits if an internal program- Both data and clock lines remain high. ming cycle is in progress. A device that acknowledges must pull down the SDA 3.2 Start Data Transfer (B) line during the Acknowledge clock pulse in such a way that the SDA line is stable low during the high period of A high-to-low transition of the SDA line while the clock the acknowledge related clock pulse. Of course, setup (SCL) is high determines a Start condition. All and hold times must be taken into account. During commands must be preceded by a Start condition. reads, a master must signal an end of data to the slave by NOT generating an Acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave (24XX65) must leave the data line high to enable the master to generate the Stop condition. FIGURE 3-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS (A) (B) (D) (D) (C) (A) SCL SDA Start Address or Data Stop Condition Acknowledge Allowed Condition Valid To Change  2003 Microchip Technology Inc. DS21073J-page 5

24AA65/24LC65/24C65 3.6 Device Addressing 4.0 WRITE OPERATION A control byte is the first byte received following the 4.1 Byte Write Start condition from the master device. The control byte consists of a four-bit control code, for the 24XX65 this Following the Start condition from the master, the con- is set as ‘1010’ binary for read and write operations. trol code (four bits), the device select (three bits), and The next three bits of the control byte are the device the R/W bit which is a logic low, is placed onto the bus select bits (A2, A1, A0). They are used by the master by the master transmitter. This indicates to the device to select which of the eight devices are to be addressed slave receiver (24XX65) that a byte with a accessed. These bits are in effect the three Most word address will follow after it has generated an Significant bits of the word address. The last bit of the Acknowledge bit during the ninth clock cycle. There- control byte defines the operation to be performed. fore, the next byte transmitted by the master is the When set to a one a read operation is selected, when high-order byte of the word address and will be written set to a zero a write operation is selected. The next two into the address pointer of the 24XX65. The next byte bytes received define the address of the first data byte is the Least Significant Address Byte. After receiving (Figure4-1). Because only A12..A0 are used, the another Acknowledge signal from the 24XX65, the upper three address bits must be zeros. The Most master device will transmit the data word to be written Significant bit of the Most Significant Byte is transferred into the addressed memory location. The 24XX65 first. Following the Start condition, the 24XX65 acknowledges again and the master generates a Stop monitors the SDA bus checking the device type condition. This initiates the internal write cycle, and identifier being transmitted. Upon receiving a ‘1010’ during this time the 24XX65 will not generate code and appropriate device select bits, the slave Acknowledge signals (Figure4-1). device (24XX65) outputs an Acknowledge signal on the SDA line. Depending upon the state of the R/W bit, the 4.2 Page Write 24XX65 will select a read or write operation. The write control byte, word address and the first data Operation Control Code Device Select R/W byte are transmitted to the 24XX65 in the same way as in a byte write. But instead of generating a Stop Read 1010 Device Address 1 condition, the master transmits up to eight pages of Write 1010 Device Address 0 eight data bytes each (64 bytes total), which are temporarily stored in the on-chip page cache of the FIGURE 3-2: CONTROL BYTE 24XX65. They will be written from the cache into the EEPROM array after the master has transmitted a Stop ALLOCATION condition. After the receipt of each word, the six lower START READ/WRITE order address pointer bits are internally incremented by one. The higher order seven bits of the word address remain constant. If the master should transmit more SLAVE ADDRESS R/W A than eight bytes prior to generating the Stop condition (writing across a page boundary), the address counter (lower three bits) will roll over and the pointer will be incremented to point to the next line in the cache. This can continue to occur up to eight times or until the cache 1 0 1 0 A2 A1 A0 is full, at which time a Stop condition should be generated by the master. If a Stop condition is not received, the cache pointer will roll over to the first line (byte 0) of the cache, and any further data received will overwrite previously captured data. The Stop condition can be sent at any time during the transfer. As with the byte write operation, once the Stop condition is received an internal write cycle will begin. The 64-byte cache will continue to capture data until a Stop condition occurs or the operation is aborted (Figure4-2). DS21073J-page 6  2003 Microchip Technology Inc.

24AA65/24LC65/24C65 FIGURE 4-1: BYTE WRITE S T S BUS ACTIVITY A CONTROL WORD WORD T MASTER R BYTE ADDRESS (1) ADDRESS (0) DATA O T P SDA LINE S 0 0 0 P A A A A BUS ACTIVITY C C C C K K K K FIGURE 4-2: PAGE WRITE (FOR CACHE WRITE, SEE FIGURE8-2) S T S BUS A CONTROL WORD WORD T ACTIVITY R BYTE ADDRESS (1) ADDRESS (0) DATA n DATA n + 7 O MASTER T P SDA LINES 0 0 0 P A A A A A BUS C C C C C ACTIVITY: K K K K K FIGURE 4-3: CURRENT ADDRESS READ S T S BUS ACTIVITY CONTROL MASTER A BYTE DATA n T R O T P SDA LINE S P A N BUS ACTIVITY C O K A C K  2003 Microchip Technology Inc. DS21073J-page 7

24AA65/24LC65/24C65 FIGURE 4-4: RANDOM READ S S T T S A CONTROL WORD WORD A CONTROL T R BYTE ADDRESS (1) ADDRESS (0) R BYTE DATA n O T T P SDA LINES 0 0 0 S P A A A A N BUS C C C C O ACTIVITY K K K K A C K FIGURE 4-5: SEQUENTIAL READ S T BUS ACTIVITYCONTROL O MASTER BYTE DATA n DATA n + 1 DATA n + 2 DATA n + X P SDA LINE P A A A A N BUS ACTIVITY C C C C O K K K K A C K DS21073J-page 8  2003 Microchip Technology Inc.

24AA65/24LC65/24C65 5.0 READ OPERATION 5.4 Contiguous Addressing Across Multiple Devices Read operations are initiated in the same way as write operations with the exception that the R/W bit of the The device select bits A2, A1, A0 can be used to slave address is set to one. There are three basic types expand the contiguous address space for up to 512K of read operations: current address read, random read bits by adding up to eight 24XX65's on the same bus. and sequential read. In this case, software can use A0 of the control byte as address bit A13, A1 as address bit A14 and A2 as 5.1 Current Address Read address bit A15. The 24XX65 contains an address counter that main- 5.5 Noise Protection tains the address of the last word accessed, internally incremented by one. Therefore, if the previous access The SCL and SDA inputs have filter circuits which (either a read or write operation) was to address n (n is suppress noise spikes to assure proper device any legal address), the next current address read operation even on a noisy bus. All I/O lines incorporate operation would access data from address n + 1. Upon Schmitt Triggers for 400 kHz (Fast mode) compatibility. receipt of the slave address with R/W bit set to one, the 24XX65 issues an acknowledge and transmits the 5.6 High Endurance Block eight-bit data word. The master will not acknowledge the transfer but does generate a Stop condition and the The location of the high endurance block within the 24XX65 discontinues transmission (Figure4-3). memory map is programmed by setting the leading bit 7 (S/HE) of the configuration byte to ‘0’. The upper bits 5.2 Random Read of the address loaded in this command will determine which 4K block within the memory map will be set to Random read operations allow the master to access high endurance. This block will be capable of any memory location in a random manner. To perform 10,000,000 erase/write cycles typical (Figure8-1). this type of read operation, first the word address must The high endurance block will retain its value as the be set. This is done by sending the word address to the high endurance block even if it resides within the 24XX65 as part of a write operation (R/W bit set to ‘0’). security block range. The high endurance setting After the word address is sent, the master generates a always takes precedence to the security setting. Start condition following the acknowledge. This terminates the write operation, but not before the Note: The high endurance block cannot be internal address pointer is set. Then the master issues changed after the security option has been the control byte again, but with the R/W bit set to a one. set with a length greater than zero. If the The 24XX65 will then issue an acknowledge and H.E. block is not programmed by the user, transmit the eight-bit data word. The master will not the default location is the highest block of acknowledge the transfer, but does generate a Stop memory which starts at location 0x1E00 condition which causes the 24XX65 to discontinue and ends at 0x1FFF. transmission (Figure4-4). 5.3 Sequential Read Sequential reads are initiated in the same way as a random read except that after the 24XX65 transmits the first data byte, the master issues an acknowledge as opposed to the Stop condition used in a random read. This acknowledge directs the 24XX65 to transmit the next sequentially addressed 8-bit word (Figure4-5). Following the final byte transmitted to the master, the master will NOT generate an acknowledge, but will generate a Stop condition. To provide sequential reads the 24XX65 contains an internal address pointer which is incremented by one at the completion of each operation. This address pointer allows the entire memory contents to be serially read during one operation.  2003 Microchip Technology Inc. DS21073J-page 9

24AA65/24LC65/24C65 5.7 Security Options acknowledge the second, and then send a Stop bit to end the sequence. The upper four bits of both of these The 24XX65 has a sophisticated mechanism for write bytes will always be read as ‘1’s. The lower four bits of protecting portions of the array. This write-protect the first byte contains the starting secure block. The function is programmable and allows the user to protect lower four bits of the second byte contains the number 0-15 contiguous 4K blocks. The user sets the security of secure blocks. The default starting secure block is option by sending to the device the starting block fifteen and the default number of secure blocks is zero number for the protected region and the number of (Figure8-1). blocks to be protected. All parts will come from the factory in the default configuration with the starting 6.0 ACKNOWLEDGE POLLING block number set to 15 and the number of protected blocks set to zero. THE SECURITY OPTION CAN BE Since the device will not acknowledge during a write SET ONLY ONCE WITH A LENGTH GREATER THAN cycle, this can be used to determine when the cycle is ZERO. complete (this feature can be used to maximize bus To invoke the security option, a Write command is sent throughput). Once the Stop condition for a Write to the device with the leading bit (bit 7) of the first command has been issued from the master, the device address byte set to a ‘1’ (Figure8-1). Bits 1-4 of the first initiates the internally timed write cycle. ACK polling address byte define the starting block number for the can be initiated immediately. This involves the master protected region. sending a Start condition followed by the control byte for a Write command (R/W = 0). If the device is still For example, if the starting block number is to be set to busy with the write cycle, then no ACK will be returned. 5, the first address byte would be 1XX0101X. Bits 0, 5 If the cycle is complete, then the device will return the and 6 of the first address byte are disregarded by the ACK and the master can then proceed with the next device and can be either high or low. The device will Read or Write command. See Figure6-1 for flow acknowledge after the first address byte. A byte of don’t diagram. care bits is then sent by the master, with the device acknowledging afterwards. The third byte sent to the FIGURE 6-1: ACKNOWLEDGE device has bit 7 (S/HE) set high and bit 6 (R) set low. Bits 4 and 5 are don’t cares and bits 0-3 define the POLLING FLOW number of blocks to be write-protected. For example, if three blocks are to be protected, the third byte would be 10XX0011. After the third byte is sent to the device, it Send will acknowledge and a Stop bit is then sent by the mas- Write Command ter to complete the command. If one of the security blocks coincides with the high endurance block, the high endurance setting will take Send Stop precedence. Also, if the range of the security blocks Condition to encompass the high endurance block when the secu- Initiate Write Cycle rity option is set, the security block range will be set accordingly, but the high endurance block will continue to retain the high endurance setting. As a result, the memory blocks preceding the high endurance block will Send Start be set as secure sections. During a normal write sequence, if an attempt is made to write to a protected address, no data will be written Send Control Byte and the device will not report an error or abort the with R/W = 0 command. If a Write command is attempted across a secure boundary, unprotected addresses will be written and protected addresses will not. Did Device NO 5.8 Security Configuration Read Acknowledge (ACK = 0)? The status of the secure portion of memory can be read YES by using the same technique as programming this option except the read bit (bit 6) of the configuration Next byte is set to a one. After the configuration byte is sent, Operation the device will acknowledge and then send two bytes of data to the master just as in a normal read sequence. The master must acknowledge the first byte and not DS21073J-page 10  2003 Microchip Technology Inc.

24AA65/24LC65/24C65 7.0 PAGE CACHE AND ARRAY fully loaded cache of 64 bytes. Since the cache started MAPPING loading at byte 2, the last two bytes loaded into the cache will ‘roll over' and be loaded into the first two The cache is a 64-byte (8 pages x 8 bytes) FIFO buffer. bytes of page 0 (of the cache). When the Stop bit is The cache allows the loading of up to 64 bytes of data sent, page 0 of the cache is written to page 3 of the before the write cycle is actually begun, effectively array. The remaining pages in the cache are then providing a 64-byte burst write at the maximum bus loaded sequentially to the array. A write cycle is rate. Whenever a Write command is initiated, the cache executed after each page is written. If a partially loaded starts loading and will continue to load until a Stop bit is page in the cache remains when the Stop bit is sent, received to start the internal write cycle. The total only the bytes that have been loaded will be written to length of the write cycle will depend on how many the array. pages are loaded into the cache before the Stop bit is given. Maximum cycle time for each page is 5 ms. Even 7.3 Power Management if a page is only partially loaded, it will still require the The design incorporates a power Standby mode when same cycle time as a full page. If more than 64 bytes of not in use and automatically powers off after the normal data are loaded before the Stop bit is given, the termination of any operation when a Stop bit is received address pointer will ‘wrap around’ to the beginning of and all internal functions are complete. This includes cache page 0 and existing bytes in the cache will be any error conditions (i.e., not receiving an Acknowl- overwritten. The device will not respond to any edge or Stop condition per the two-wire bus specifica- commands while the write cycle is in progress. tion). The device also incorporates VDD monitor circuitry to prevent inadvertent writes (data corruption) 7.1 Cache Write Starting at a Page during low voltage conditions. The VDD monitor circuitry Boundary is powered off when the device is in Standby mode in If a Write command begins at a page boundary order to further reduce power consumption. (address bits A2, A1 and A0 are zero), then all data loaded into the cache will be written to the array in 8.0 PIN DESCRIPTIONS sequential addresses. This includes writing across a 4K block boundary. In the example shown below, 8.1 A0, A1, A2 Chip Address Inputs (Figure8-2) a Write command is initiated starting at byte 0 of page 3 with a fully loaded cache (64 bytes). The A0..A2 inputs are used by the 24XX65 for multiple The first byte in the cache is written to byte 0 of page 3 device operation and conform to the two-wire bus (of the array), with the remaining pages in the cache standard. The levels applied to these pins define the written to sequential pages in the array. A write cycle is address block occupied by the device in the address executed after each page is written. Since the write map. A particular device is selected by transmitting the begins at page 3 and 8 pages are loaded into the corresponding bits (A2, A1, A0) in the control byte cache, the last 3 pages of the cache are written to the (Figure3-2 and Figure8-1). next row in the array. 8.2 SDA Serial Address/Data Input/ 7.2 Cache Write Starting at a Output Non-Page Boundary This is a bidirectional pin used to transfer addresses When a Write command is initiated that does not begin and data into and data out of the device. It is an open at a page boundary (i.e., address bits A2, A1 and A0 drain terminal, therefore the SDA bus requires a pull-up are not all zero), it is important to note how the data is resistor to VCC (typical 10 KΩ for 100 kHz, 2 KΩ for 400 loaded into the cache, and how the data in the cache is kHz). written to the array. When a Write command begins, the For normal data transfer SDA is allowed to change only first byte loaded into the cache is always loaded into during SCL low. Changes during SCL high are page 0. The byte within page 0 of the cache where the reserved for indicating the Start and Stop conditions. load begins is determined by the three Least Significant Address bits (A2, A1, A0) that were sent as part of the 8.3 SCL Serial Clock Write command. If the Write command does not start at byte 0 of a page and the cache is fully loaded, then the This input is used to synchronize the data transfer from last byte(s) loaded into the cache will roll around to and to the device. page 0 of the cache and fill the remaining empty bytes. If more than 64 bytes of data are loaded into the cache, data already loaded will be overwritten. In the example shown in Figure8-3, a Write command has been initiated starting at byte 2 of page 3 in the array with a  2003 Microchip Technology Inc. DS21073J-page 11

24AA65/24LC65/24C65 FIGURE 8-1: CONTROL SEQUENCE BIT ASSIGNMENTS Control Byte Address Byte 1 Address Byte 0 Configuration Byte 1 0 1 0 A2 A1 A0 R/W S 0 01A21A11A0A9 A8 A7 (cid:127) (cid:127) (cid:127) (cid:127) (cid:127) (cid:127) A0 R X X B3 B2 B1 B0 S/HE Slave Device Block Address Select Count Bits Security Read Acknowledge No from ACK S t Master S a Acknowledges from Device t r Data from Device Data from Device o t R p 1 0 1 0 A A A 0 CA 1 X X X X X X X CA X X X X X X X X CA 1 1 X X X X X X CA 1 1 1 1 B B B B CA 1 1 1 1 N N N N 2 1 0 K K K K 3 2 1 0 K 3 2 1 0 S/HE Starting Block Number of Number Blocks to Protect Security Write S t S a Acknowledges from Device t r o t R p 1 0 1 0 A A A 0 CA 1 X X B B B B X CA X X X X X X X X CA 1 0 X X N N N N CA 2 1 0 K 3 2 1 0 K K 3 2 1 0 K S/HE Starting Block Number of Number Blocks to Protect High Endurance Block Read No S ACK t S a Acknowledges from Device t r Data from Device o t R p 1 0 1 0 A A A 0 CA 1 X X X X X X X CA X X X X X X X X CA 0 1 X X X X X X CA 1 1 1 1 B B B B 2 1 0 K K K K 3 2 1 0 S/HE High Endurance Block Number High Endurance Block Write S t S a Acknowledges from Device t r o t R p 1 0 1 0 A A A 0 CA 1 X X B B B B X CA X X X X X X X X CA 0 0 X X 0 0 0 0 CA 2 1 0 K 3 2 1 0 K K K S/HE High Endurance Block Number DS21073J-page 12  2003 Microchip Technology Inc.

24AA65/24LC65/24C65 FIGURE 8-2: CACHE WRITE TO THE ARRAY STARTING AT A PAGE BOUNDARY 1 Write command initiated at byte 0 of page 3 in the array; First data byte is loaded into the cache byte 0. 2 64 bytes of data are loaded into cache. cache page 0 cache cache cache cache page 1 cache page 2 cache page 7 (cid:127) (cid:127) (cid:127) (cid:127) (cid:127) (cid:127) byte 0 byte 1 byte 7 bytes 8-15 bytes 16-23 bytes 56-63 3 Write from cache into array initiated by STOP bit. Page 0 of cache written to page 3 of array. 4 Remaining pages in cache are written Write cycle is executed after every page is written. to sequential pages in array. page 0 page 1 page 2 byte 0 byte 1 (cid:127) (cid:127) (cid:127) byte 7 page 4 (cid:127) (cid:127) (cid:127) page 7 array row n page 0 page 1 page 2 page 3 page 4 (cid:127) (cid:127) (cid:127) page 7 array row n + 1 5 Last page in cache written to page 2 in next row. FIGURE 8-3: CACHE WRITE TO THE ARRAY STARTING AT A NON-PAGE BOUNDARY 1 Write command initiated; 64 bytes of data 2 Last 2 bytes loaded 'roll over' loaded into cache starting at byte 2 of page 0. to beginning. Last 2 bytes 3 loaded into page 0 of cache. cache cache cache cache cache page 1 cache page 2 cache page 7 (cid:127) (cid:127) (cid:127) (cid:127) (cid:127) (cid:127) byte 0 byte 1 byte 2 byte 7 bytes 8-15 bytes 16-23 bytes 56-63 4 Write from cache into array initiated by STOP bit. Page 0 of cache written to page 3 of array. 5 Remaining bytes in cache are Write cycle is executed after every page is written. written sequentially to array. array page 0 page 1 page 2 byte 0 byte 1 byte 2 byte 3 byte 4 (cid:127) (cid:127) (cid:127) byte 7 page 4 (cid:127) (cid:127) (cid:127) page 7 row n page 0 page 1 page 2 page 3 page 4 (cid:127) (cid:127) (cid:127) page 7 array row n + 1 6 Last 3 pages in cache written to next row in array.  2003 Microchip Technology Inc. DS21073J-page 13

24AA65/24LC65/24C65 9.0 PACKAGING INFORMATION 9.1 Package Marking Information 8-Lead PDIP (300 mil) Example: XXXXXXXX 24LC65 T/XXXNNN I/P017 YYWW 0310 8-Lead SOIC (208 mil) Example: XXXXXXXX 24LC65 T/XXXXXX I/SM YYWWNNN 0110017 Legend: XX...X Customer specific information* Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code T Temperature grade (Blank = Commercial, I = Industrial, E = Automotive) Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. * Standard PICmicro device marking consists of Microchip part number, year code, week code, and traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. DS21073J-page 14  2003 Microchip Technology Inc.

24AA65/24LC65/24C65 8-Lead Plastic Dual In-line (P) – 300 mil (PDIP) E1 D 2 n 1 α E A A2 L c A1 β B1 p eB B Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 8 8 Pitch p .100 2.54 Top to Seating Plane A .140 .155 .170 3.56 3.94 4.32 Molded Package Thickness A2 .115 .130 .145 2.92 3.30 3.68 Base to Seating Plane A1 .015 0.38 Shoulder to Shoulder Width E .300 .313 .325 7.62 7.94 8.26 Molded Package Width E1 .240 .250 .260 6.10 6.35 6.60 Overall Length D .360 .373 .385 9.14 9.46 9.78 Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43 Lead Thickness c .008 .012 .015 0.20 0.29 0.38 Upper Lead Width B1 .045 .058 .070 1.14 1.46 1.78 Lower Lead Width B .014 .018 .022 0.36 0.46 0.56 Overall Row Spacing § eB .310 .370 .430 7.87 9.40 10.92 Mold Draft Angle Top α 5 10 15 5 10 15 Mold Draft Angle Bottom β 5 10 15 5 10 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-018  2003 Microchip Technology Inc. DS21073J-page 15

24AA65/24LC65/24C65 8-Lead Plastic Small Outline (SM) – Medium, 208 mil (SOIC) E E1 p D 2 n 1 B α c A A2 φ A1 β L Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 8 8 Pitch p .050 1.27 Overall Height A .070 .075 .080 1.78 1.97 2.03 Molded Package Thickness A2 .069 .074 .078 1.75 1.88 1.98 Standoff § A1 .002 .005 .010 0.05 0.13 0.25 Overall Width E .300 .313 .325 7.62 7.95 8.26 Molded Package Width E1 .201 .208 .212 5.11 5.28 5.38 Overall Length D .202 .205 .210 5.13 5.21 5.33 Foot Length L .020 .025 .030 0.51 0.64 0.76 Foot Angle φ 0 4 8 0 4 8 Lead Thickness c .008 .009 .010 0.20 0.23 0.25 Lead Width B .014 .017 .020 0.36 0.43 0.51 Mold Draft Angle Top α 0 12 15 0 12 15 Mold Draft Angle Bottom β 0 12 15 0 12 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. Drawing No. C04-056 DS21073J-page 16  2003 Microchip Technology Inc.

24AA65/24LC65/24C65 APPENDIX A: REVISION HISTORY Revision J Corrections to Section 1.0, Electrical Characteristics.  2003 Microchip Technology Inc. DS21073J-page 17

24AA65/24LC65/24C65 NOTES: DS21073J-page 18  2003 Microchip Technology Inc.

24AA65/24LC65/24C65 ON-LINE SUPPORT SYSTEMS INFORMATION AND UPGRADE HOT LINE Microchip provides on-line support on the Microchip World Wide Web site. The Systems Information and Upgrade Line provides The web site is used by Microchip as a means to make system users a listing of the latest versions of all of files and information easily available to customers. To Microchip's development systems software products. view the site, the user must have access to the Internet Plus, this line provides information on how customers and a web browser, such as Netscape® or Microsoft® can receive the most current upgrade kits. The Hot Line Internet Explorer. Files are also available for FTP Numbers are: download from our FTP site. 1-800-755-2345 for U.S. and most of Canada, and 1-480-792-7302 for the rest of the world. Connecting to the Microchip Internet Web Site 042003 The Microchip web site is available at the following URL: www.microchip.com The file transfer site is available by using an FTP service to connect to: ftp://ftp.microchip.com The web site and file transfer site provide a variety of services. Users may download files for the latest Development Tools, Data Sheets, Application Notes, User's Guides, Articles and Sample Programs. A vari- ety of Microchip specific business information is also available, including listings of Microchip sales offices, distributors and factory representatives. Other data available for consideration is: (cid:127) Latest Microchip Press Releases (cid:127) Technical Support Section with Frequently Asked Questions (cid:127) Design Tips (cid:127) Device Errata (cid:127) Job Postings (cid:127) Microchip Consultant Program Member Listing (cid:127) Links to other useful web sites related to Microchip Products (cid:127) Conferences for products, Development Systems, technical information and more (cid:127) Listing of seminars and events  2003 Microchip Technology Inc. DS21073J-page 19

24AA65/24LC65/24C65 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod- uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: Technical Publications Manager Total Pages Sent ________ RE: Reader Response From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y N Device: 24AA65/24LC65/24C65 Literature Number: DS21073J Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS21073J-page 20  2003 Microchip Technology Inc.

24AA65/24LC65/24C65 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX XXX Examples: Device Temperature Package Pattern a) 24LC65T-I/SM: 64 Kbit Smart Serial, Range Tape and Reel, 207 mil SOIC package, Industrial temperature, 2.5V b) 24LC65-I/P: 64 Kbit Smart Serial, Device 24AA65 - 64K I2C 1.8V Serial EEPROM (100 kHz) Industrial temperature, PDIP package, 24AA65T - 64K I2C 1.8V Serial EEPROM (100 kHz) 24LC65 - 64K I2C Serial EEPROM (100 kHz/400 kHz) 2.5V 24LC65T - 64K I2C Serial EEPROM (Tape and Reel) c) 24AA65T-/SM: 64 Kbit Smart Serial, 24C65 - 64K I2C 4.5V Serial EEPROM (400 kHz) Tape and Reel, 207 mil SOIC package, 24C65T - 64K I2C 4.5V Serial EEPROM (Tape and Reel) Commercial temperature, 1.8V d) 24C65-E/P: 64 Kbit Smart Serial, Temperature Range Blank = 0°C to +70°C Automotive temperature, PDIP, 5V I = -40°C to +85°C E = -40°C to +125°C Package P = Plastic DIP (300 mil Body) SM = Plastic SOIC (207 mil Body, EIAJ standard) Sales and Support Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. Your local Microchip sales office 2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277 3. The Microchip Worldwide Site (www.microchip.com) Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products.  2003 Microchip Technology Inc. DS21073J-page 21

24AA65/24LC65/24C65 NOTES: DS21073J-page 22  2003 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices: (cid:127) Microchip products meet the specification contained in their particular Microchip Data Sheet. (cid:127) Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. (cid:127) There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. (cid:127) Microchip is willing to work with the customer who is concerned about the integrity of their code. (cid:127) Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is intended through suggestion only The Microchip name and logo, the Microchip logo, Accuron, and may be superseded by updates. It is your responsibility to dsPIC, KEELOQ, MPLAB, PIC, PICmicro, PICSTART, ensure that your application meets with your specifications. PRO MATE and PowerSmart are registered trademarks of No representation or warranty is given and no liability is Microchip Technology Incorporated in the U.S.A. and other assumed by Microchip Technology Incorporated with respect countries. to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such AmpLab, FilterLab, microID, MXDEV, MXLAB, PICMASTER, use or otherwise. Use of Microchip’s products as critical com- SEEVAL and The Embedded Control Solutions Company are ponents in life support systems is not authorized except with registered trademarks of Microchip Technology Incorporated express written approval by Microchip. No licenses are con- in the U.S.A. veyed, implicitly or otherwise, under any intellectual property Application Maestro, dsPICDEM, dsPICDEM.net, ECAN, rights. ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, microPort, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPIC, Select Mode, SmartSensor, SmartShunt, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. Serialized Quick Turn Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2003, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999 and Mountain View, California in March 2002. The Company’s quality system processes and procedures are QS-9000 compliant for its PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, non-volatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001 certified.  2003 Microchip Technology Inc. DS21073J-page 23

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Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: M icrochip: 24LC65/SM 24C65/SMG 24AA65/P 24LC65-I/SM 24LC65-I/SMG 24C65/P 24C65-I/P 24LC65T/SM 24AA65T/SM 24LC65/SMG 24AA65/SMG 24LC65T-I/SM 24C65T/SMG 24LC65T/SMG 24C65/SM 24LC65/P 24C65T/SM 24AA65/SM 24LC65T-I/SMG 24AA65T/SMG 24C65T-I/SMG 24LC65-I/P 24C65-I/SMG 24C65-I/SM 24C65T-I/SM