24AA64/24LC64/24FC64 2 64K I C™ Serial EEPROM Device Selection Table • Pb-Free and RoHS Compliant • Temperature Ranges: Part VCC Max. Clock Temp. Number Range Frequency Ranges - Industrial (I): -40°C to +85°C - Automotive (E): -40°C to +125°C 24AA64 1.7-5.5 400kHz(1) I, E Description: 24LC64 2.5-5.5 400kHz I, E 24FC64 1.7-5.5 1 MHz(2) I The Microchip Technology Inc. 24AA64/24LC64/ 24FC64 (24XX64*) is a 64 Kbit Electrically Erasable Note 1: 100 kHz for VCC <2.5V. PROM. The device is organized as a single block of 2: 400 kHz for VCC <2.5V. 8K x 8-bit memory with a 2-wire serial interface. Low- voltage design permits operation down to 1.7V, with Features: standby and active currents of only 1A and 3mA, respectively. It has been developed for advanced, low- • Single-Supply with Operation down to 1.7V for power applications such as personal communications 24AA64/24FC64 Devices, 2.5V for 24LC64 or data acquisition. The 24XX64 also has a page write Devices capability for up to 32 bytes of data. Functional • Low-Power CMOS Technology: address lines allow up to eight devices on the same - Active current 3mA, max. bus, for up to 512Kbits address space. The 24XX64 is - Standby current 1A, max. available in the standard 8-pin PDIP, surface mount • 2-Wire Serial Interface, I2C™ Compatible SOIC, SOIJ, TSSOP, DFN, TDFN and MSOP packages. The 24XX64 is also available in the 5-lead • Packages with 3 Address Pins are Cascadable up SOT-23, and Chip Scale packages. to 8 Devices • Schmitt Trigger Inputs for Noise Suppression Block Diagram • Output Slope Control to Eliminate Ground Bounce HV • 100kHz and 400kHz Clock Compatibility A0A1A2WP Generator • 1 MHz Clock for FC versions • Page Write Time 5 ms, max. • Self-timed Erase/Write Cycle I/O Memory EEPROM Control Control XDEC Array • 32-Byte Page Write Buffer Logic Logic Page • Hardware Write-Protect Latches • ESD Protection > 4,000V I/O • More than 1 Million Erase/Write Cycles SCL YDEC • Data Retention > 200 Years SDA • Factory Programming Available • Packages include 8-lead PDIP, SOIC, SOIJ, VCC TSSOP, X-Rotated TSSOP, MSOP, DFN, TDFN, VSS Sense Amp. 5-lead SOT-23 or Chip Scale R/W Control Package Types PDIP/MSOP/SOIC/SOIJ/TSSOP SOT-23 DFN/TDFN CS (Chip Scale)(1) X-Rotated TSSOP A0 1 8 VCC (X/ST) SCL 1 5 WP A0 1 8 VCC VCC 1 2 VSS A1 2 7 WP AA12 23 76 WSCPL VWCPC 12 87 SSCDLA VSS 2 A2 3 6 SCL SWCPL 4 3 5 SDA A0 3 6 VSS SDA 3 4 VCC VSS 4 5 SDA VSS 4 5 SDA A1 4 5 A2 (Top Down View, Note 1: Available in I-temp, “AA” only. Balls Not Visible) * 24XX64 is used in this document as a generic part number for the 24AA64/24LC64/24FC64 devices.  1997-2012 Microchip Technology Inc. DS21189T-page 1

24AA64/24LC64/24FC64 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings (†) VCC.............................................................................................................................................................................6.5V All inputs and outputs w.r.t. VSS.........................................................................................................-0.3V to VCC +1.0V Storage temperature...............................................................................................................................-65°C to +150°C Ambient temperature with power applied................................................................................................-40°C to +125°C ESD protection on all pins 4kV † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. TABLE 1-1: DC CHARACTERISTICS Industrial (I): TA = -40°C to +85°C, VCC = +1.7V to +5.5V DC CHARACTERISTICS Automotive (E): TA = -40°C to +125°C, VCC = +1.7V to +5.5V Param. Sym. Characteristic Min. Typ. Max. Units Conditions No. — A0, A1, A2, WP, SCL — — — — — and SDA pins D1 VIH High-level input voltage 0.7 VCC — — V — D2 VIL Low-level input voltage — — 0.3 VCC V VCC  2.5V 0.2 VCC V VCC  2.5V D3 VHYS Hysteresis of Schmitt 0.05 VCC — — V VCC  2.5V (Note 1) Trigger inputs (SDA, SCL pins) D4 VOL Low-level output voltage — — 0.40 V IOL = 3.0mA @ VCC = 4.5V IOL = 2.1mA @ VCC = 2.5V D5 ILI Input leakage current — — ±1 A VIN = VSS or VCC, WP = VSS VIN = VSS or VCC, WP = VCC D6 ILO Output leakage current — — ±1 A VOUT = VSS or VCC D7 CIN, Pin capacitance — — 10 pF VCC = 5.0V (Note 1) COUT (all inputs/outputs) TA = 25°C, FCLK = 1MHz D8 ICC write Operating current — 0.1 3 mA VCC = 5.5V, SCL = 400kHz D9 ICC read — 0.05 400 A D10 ICCS Standby current — 0.01 1 A Industrial — — 5 A Automotive SDA = SCL = VCC A0, A1, A2, WP = VSS Note 1: This parameter is periodically sampled and not 100% tested. 2: Typical measurements taken at room temperature. DS21189T-page 2  1997-2012 Microchip Technology Inc.

24AA64/24LC64/24FC64 TABLE 1-2: AC CHARACTERISTICS Electrical Characteristics: AC CHARACTERISTICS Industrial (I): VCC = +1.7V to 5.5V TA = -40°C to +85°C Automotive (E): VCC = +1.7V to 5.5V TA = -40°C to 125°C Param. Sym. Characteristic Min. Max. Units Conditions No. 1 FCLK Clock frequency — 100 kHz 1.7V  VCC  2.5V — 400 2.5V  VCC  5.5V — 400 1.7V  VCC  2.5V 24FC64 — 1000 2.5V  VCC  5.5V 24FC64 2 THIGH Clock high time 4000 — ns 1.7V  VCC  2.5V 600 — 2.5V  VCC  5.5V 600 — 1.7V  VCC  2.5V 24FC64 500 — 2.5V  VCC  5.5V 24FC64 3 TLOW Clock low time 4700 — ns 1.7V  VCC  2.5V 1300 — 2.5V  VCC  5.5V 1300 — 1.7V  VCC  2.5V 24FC64 500 — 2.5V  VCC  5.5V 24FC64 4 TR SDA and SCL rise time — 1000 ns 1.7V  VCC  2.5V (Note1) — 300 2.5V  VCC  5.5V — 300 1.7V  VCC  5.5V 24FC64 5 TF SDA and SCL fall time — 300 ns All except, 24FC64 (Note1) — 100 1.7V  VCC  5.5V 24FC64 6 THD:STA Start condition hold time 4000 — ns 1.7V  VCC  2.5V 600 — 2.5V  VCC  5.5V 600 — 1.7V  VCC  2.5V 24FC64 250 — 2.5V  VCC  5.5V 24FC64 7 TSU:STA Start condition setup time 4700 — ns 1.7V  VCC  2.5V 600 — 2.5V  VCC  5.5V 600 — 1.7V  VCC  2.5V 24FC64 250 — 2.5V  VCC  5.5V 24FC64 8 THD:DAT Data input hold time 0 — ns (Note2) 9 TSU:DAT Data input setup time 250 — ns 1.7V  VCC  2.5V 100 — 2.5V  VCC  5.5V 100 — 1.7V  VCC  5.5V 24FC64 10 TSU:STO Stop condition setup time 4000 — ns 1.7V  VCC  2.5V 600 — 2.5V  VCC  5.5V 600 — 1.7V  VCC  2.5V 24FC64 250 — 2.5V  VCC  5.5V 24FC64 11 TSU:WP WP setup time 4000 — ns 1.7V  VCC  2.5V 600 — 2.5V  VCC  5.5V 600 — 1.7V  VCC  5.5V 24FC64 12 THD:WP WP hold time 4700 — ns 1.7V  VCC  2.5V 1300 — 2.5V  VCC  5.5V 1300 — 1.7V  VCC  5.5V 24FC64 Note 1: Not 100% tested. CB = total capacitance of one bus line in pF. 2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. 3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs, which provide improved noise spike suppression. This eliminates the need for a TI specification for standard operation. 4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total Endurance™ Model, which can be obtained from Microchip’s web site at www.microchip.com.  1997-2012 Microchip Technology Inc. DS21189T-page 3

24AA64/24LC64/24FC64 Electrical Characteristics: AC CHARACTERISTICS Industrial (I): VCC = +1.7V to 5.5V TA = -40°C to +85°C Automotive (E): VCC = +1.7V to 5.5V TA = -40°C to 125°C Param. Sym. Characteristic Min. Max. Units Conditions No. 13 TAA Output valid from clock — 3500 ns 1.7V  VCC  2.5V (Note2) — 900 2.5V  VCC  5.5V — 900 1.7V  VCC  2.5V 24FC64 — 400 2.5V  VCC  5.5V 24FC64 14 TBUF Bus free time: Time the bus 4700 — ns 1.7V  VCC  2.5V must be free before a new 1300 — 2.5V  VCC  5.5V transmission can start 1300 — 1.7V  VCC  2.5V 24FC64 500 — 2.5V  VCC  5.5V 24FC64 15 TOF Output fall time from VIH 10 + 0.1CB 250 ns All except, 24FC64 (Note1) minimum to VIL maximum 250 24FC64 (Note1) CB  100pF 16 TSP Input filter spike suppression — 50 ns All except, 24FC64 (Notes1 (SDA and SCL pins) and3) 17 TWC Write cycle time (byte or — 5 ms — page) 18 — Endurance 1,000,000 — cycles Page Mode 25°C, 5.5V (Note4) Note 1: Not 100% tested. CB = total capacitance of one bus line in pF. 2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. 3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs, which provide improved noise spike suppression. This eliminates the need for a TI specification for standard operation. 4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total Endurance™ Model, which can be obtained from Microchip’s web site at www.microchip.com. FIGURE 1-1: BUS TIMING DATA 5 4 2 D3 SCL 7 3 8 9 10 SDA 6 IN 16 13 14 SDA OUT (protected) WP 11 12 (unprotected) DS21189T-page 4  1997-2012 Microchip Technology Inc.

24AA64/24LC64/24FC64 2.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table2-1. TABLE 2-1: PIN FUNCTION TABLE Rotated Name PDIP SOIC TSSOP DFN(1) TDFN(1) MSOP SOT-23 CS Description TSSOP A0 1 1 1 3 1 1 1 — — Chip Address Input A1 2 2 2 4 2 2 2 — — Chip Address Input A2 3 3 3 5 3 3 3 — — Chip Address Input VSS 4 4 4 6 4 4 4 2 2 Ground SDA 5 5 5 7 5 5 5 3 5 Serial Address/Data I/O SCL 6 6 6 8 6 6 6 1 4 Serial Clock WP 7 7 7 1 7 7 7 5 3 Write-Protect Input VCC 8 8 8 2 8 8 8 4 1 +1.7V to 5.5V Power Supply Note1: The exposed pad on the DFN/TDFN packages can be connected to VSS or left floating. 2.1 A0, A1, A2 Chip Address Inputs 2.3 Serial Clock (SCL) The A0, A1 and A2 inputs are used by the 24XX64 for The SCL input is used to synchronize the data transfer multiple device operation. The levels on these inputs from and to the device. are compared with the corresponding bits in the slave address. The chip is selected if the compare is true. 2.4 Write-Protect (WP) Up to eight devices may be connected to the same bus This pin must be connected to either VSS or VCC. If tied by using different Chip Select bit combinations. These to VSS, write operations are enabled. If tied to VCC, inputs must be connected to either VCC or VSS. write operations are inhibited but read operations are In most applications, the chip address inputs A0, A1 not affected. and A2 are hard-wired to logic ‘0’ or logic ‘1’. For applications in which these pins are controlled by a 3.0 FUNCTIONAL DESCRIPTION microcontroller or other programmable device, the chip address pins must be driven to logic ‘0’ or logic ‘1’ The 24XX64 supports a bidirectional, 2-wire bus and before normal device operation can proceed. Address data transmission protocol. A device that sends data pins are not available in the SOT-23 or Chip Scale onto the bus is defined as transmitter, while a device packages. receiving data is defined as a receiver. The bus has to be controlled by a master device which generates the 2.2 Serial Data (SDA) Serial Clock (SCL), controls the bus access and generates the Start and Stop conditions, while the SDA is a bidirectional pin used to transfer addresses 24XX64 works as slave. Both master and slave can and data into and out of the device. Since it is an open- operate as transmitter or receiver, but the master drain terminal, the SDA bus requires a pull-up resistor device determines which mode is activated. to VCC (typical 10k for 100kHz, 2kfor 400kHz). For normal data transfer, SDA is allowed to change only during SCL low. Changes during SCL high are reserved for indicating the Start and Stop conditions.  1997-2012 Microchip Technology Inc. DS21189T-page 5

24AA64/24LC64/24FC64 4.0 BUS CHARACTERISTICS The data on the line must be changed during the low period of the clock signal. There is one clock pulse per The following bus protocol has been defined: bit of data. • Data transfer may be initiated only when the bus Each data transfer is initiated with a Start condition and is not busy terminated with a Stop condition. The number of data • During data transfer, the data line must remain bytes transferred between Start and Stop conditions is stable whenever the clock line is high. Changes in determined by the master device and is, theoretically, the data line while the clock line is high will be unlimited (although only the last thirty two will be stored interpreted as a Start or Stop condition when doing a write operation). When an overwrite does occur, it will replace data in a first-in first-out (FIFO) Accordingly, the following bus conditions have been fashion. defined (Figure4-1). 4.5 Acknowledge 4.1 Bus Not Busy (A) Each receiving device, when addressed, is obliged to Both data and clock lines remain high. generate an acknowledge after the reception of each byte. The master device must generate an extra clock 4.2 Start Data Transfer (B) pulse which is associated with this Acknowledge bit. A high-to-low transition of the SDA line while the clock Note: The 24XX64 does not generate any (SCL) is high determines a Start condition. All Acknowledge bits if an internal commands must be preceded by a Start condition. programming cycle is in progress. 4.3 Stop Data Transfer (C) The device that acknowledges has to pull down the SDA line during the Acknowledge clock pulse in such a A low-to-high transition of the SDA line while the clock way that the SDA line is stable low during the high (SCL) is high determines a Stop condition. All period of the acknowledge related clock pulse. Of operations must be ended with a Stop condition. course, setup and hold times must be taken into account. During reads, a master must signal an end of 4.4 Data Valid (D) data to the slave by not generating an Acknowledge bit on the last byte that has been clocked out of the slave. The state of the data line represents valid data when, In this case, the slave (24XX64) will leave the data line after a Start condition, the data line is stable for the high to enable the master to generate the Stop duration of the high period of the clock signal. condition. FIGURE 4-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS (A) (B) (D) (D) (C) (A) SCL SDA Start Address or Data Stop Condition Acknowledge Allowed Condition Valid to Change DS21189T-page 6  1997-2012 Microchip Technology Inc.

24AA64/24LC64/24FC64 5.0 DEVICE ADDRESSING Acknowledge signal on the SDA line. Depending on the state of the R/W bit, the 24XX64 will select a read or A control byte is the first byte received following the write operation. Start condition from the master device (Figure5-1). The control byte consists of a four-bit control code. For FIGURE 5-1: CONTROL BYTE FORMAT the 24XX64, this is set as ‘1010’ binary for read and write operations. The next three bits of the control byte Read/Write Bit are the Chip Select bits (A2, A1, A0). The Chip Select bits allow the use of up to eight 24XX64 devices on the Chip Select same bus and are used to select which device is Control Code Bits accessed. The Chip Select bits in the control byte must correspond to the logic levels on the corresponding A2, S 1 0 1 0 A2 A1 A0 R/W ACK A1 and A0 pins for the device to respond. These bits are, in effect, the three Most Significant bits of the word Slave Address address. For the SOT-23 and Chip Scale packages, the address Start Bit Acknowledge Bit pins are not available. During device addressing, the A2, A1 and A0 Chip Select bits (Figure5-2) should be set to ‘0’. 5.1 Contiguous Addressing Across The last bit of the control byte defines the operation to Multiple Devices be performed. When set to a ‘1’, a read operation is The Chip Select bits A2, A1 and A0 can be used to selected. When set to a ‘0’, a write operation is expand the contiguous address space for up to 512K selected. The next two bytes received define the bits by adding up to eight 24XX64 devices on the same address of the first data byte (Figure5-2). Because bus. In this case, software can use A0 of the control only A12...A0 are used, the upper-three address bits byte as address bit A13; A1 as address bit A14; and A2 are “don’t care” bits. The upper-address bits are as address bit A15. It is not possible to sequentially transferred first, followed by the Less Significant bits. read across device boundaries. Following the Start condition, the 24XX64 monitors the The SOT-23 and Chip Scale packages do not support SDA bus, checking the device-type identifier being multiple device addressing on the same bus. transmitted. Upon receiving a ‘1010’ code and appro- priate device-select bits, the slave device outputs an FIGURE 5-2: ADDRESS SEQUENCE BIT ASSIGNMENTS Control Byte Address High Byte Address Low Byte A A A A A A A A A A 1 0 1 0 2 1 0 R/W x x x 12 11 10 9 8 7 • • • • • • 0 Control Chip Code Select x = “don’t care” bit bits  1997-2012 Microchip Technology Inc. DS21189T-page 7

24AA64/24LC64/24FC64 6.0 WRITE OPERATIONS 6.2 Page Write The write control byte, word address and the first data 6.1 Byte Write byte are transmitted to the 24XX64 in the same way as in a byte write. However, instead of generating a Stop Following the Start condition from the master, the condition, the master transmits up to 31 additional control code (four bits), the Chip Select (three bits) and bytes which are temporarily stored in the on-chip page the R/W bit (which is a logic low) are clocked onto the buffer and will be written into memory once the master bus by the master transmitter. This indicates to the has transmitted a Stop condition. Upon receipt of each addressed slave receiver that the address high byte will word, the five lower Address Pointer bits are internally follow once it has generated an Acknowledge bit during incremented by one. If the master should transmit more the ninth clock cycle. Therefore, the next byte transmit- than 32 bytes prior to generating the Stop condition, the ted by the master is the high-order byte of the word address counter will roll over and the previously address and will be written into the Address Pointer of received data will be overwritten. As with the byte write the 24XX64. The next byte is the Least Significant operation, once the Stop condition is received, an inter- Address Byte. After receiving another Acknowledge nal write cycle will begin (Figure6-2). If an attempt is signal from the 24XX64, the master device will transmit made to write to the array with the WP pin held high, the the data word to be written into the addressed memory device will acknowledge the command, but no write location. The 24XX64 acknowledges again and the cycle will occur, no data will be written, and the device master generates a Stop condition. This initiates the will immediately accept a new command. internal write cycle and, during this time, the 24XX64 will not generate Acknowledge signals (Figure6-1). If Note: Page write operations are limited to writ- an attempt is made to write to the array with the WP pin ing bytes within a single physical page, held high, the device will acknowledge the command, regardless of the number of bytes but no write cycle will occur, no data will be written and actually being written. Physical page the device will immediately accept a new command. boundaries start at addresses that are After a byte Write command, the internal address coun- integer multiples of the page buffer size ter will point to the address location following the one (or ‘page size’) and end at addresses that that was just written. are integer multiples of [page size – 1]. If a Page Write command attempts to write across a physical page boundary, the Note: When doing a write of less than 32 bytes result is that the data wraps around to the the data in the rest of the page is beginning of the current page (overwriting refreshed along with the data bytes being data previously stored there), instead of written. This will force the entire page to being written to the next page, as might be endure a write cycle, for this reason expected. It is therefore necessary for the endurance is specified per page. application software to prevent page write operations that would attempt to cross a page boundary. 6.3 Write Protection The WP pin allows the user to write-protect the entire array (0000-1FFF) when the pin is tied to VCC. If tied to VSS the write protection is disabled. The WP pin is sampled at the Stop bit for every Write command (Figure4-1). Toggling the WP pin after the Stop bit will have no effect on the execution of the write cycle. DS21189T-page 8  1997-2012 Microchip Technology Inc.

24AA64/24LC64/24FC64 FIGURE 6-1: BYTE WRITE S Bus Activity T S Master A Control Address Address T R Byte High Byte Low Byte Data O T P SDA Line S1 0 1 0A2 A1A0 0 x x x P A A A A Bus Activity C C C C K K K K x = “don’t care” bit FIGURE 6-2: PAGE WRITE S T S Bus Activity A Control Address Address T Master R Byte High Byte Low Byte Data Byte 0 Data Byte 31 O T P SDA Line S 10 1 0A2 A1 A0 0 x x x P A A A A A Bus Activity C C C C C K K K K K x = “don’t care” bit  1997-2012 Microchip Technology Inc. DS21189T-page 9

24AA64/24LC64/24FC64 7.0 ACKNOWLEDGE POLLING FIGURE 7-1: ACKNOWLEDGE POLLING FLOW Since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). Once the Stop condition for a Write command has been issued from the master, the device Send initiates the internally-timed write cycle and ACK polling Write Command can then be initiated immediately. This involves the master sending a Start condition followed by the control byte for a Write command (R/W = 0). If the device is still Send Stop Condition to busy with the write cycle, then no ACK will be returned. Initiate Write Cycle If no ACK is returned, the Start bit and control byte must be re-sent. If the cycle is complete, the device will return the ACK and the master can then proceed with the next Read or Write command. See Figure7-1 for a Send Start flow diagram of this operation. Send Control Byte with R/W = 0 Did Device No Acknowledge (ACK = 0)? Yes Next Operation DS21189T-page 10  1997-2012 Microchip Technology Inc.

24AA64/24LC64/24FC64 8.0 READ OPERATION This terminates the write operation, but not before the internal Address Pointer is set. The master then Read operations are initiated in the same way as write issues the control byte again, but with the R/W bit set operations, with the exception that the R/W bit of the to a one. The 24XX64 will then issue an acknowl- control byte is set to one. There are three basic types edge and transmit the 8-bit data word. The master of read operations: current address read, random read will not acknowledge the transfer, but does generate and sequential read. a Stop condition, which causes the 24XX64 to discontinue transmission (Figure8-2). After a 8.1 Current Address Read random Read command, the internal address coun- ter will point to the address location following the one The 24XX64 contains an address counter that main- that was just read. tains the address of the last word accessed, internally incremented by one. Therefore, if the previous read 8.3 Sequential Read access was to address ‘n’ (n is any legal address), the next current address read operation would access data Sequential reads are initiated in the same way as from address n + 1. random reads, except that once the 24XX64 transmits Upon receipt of the control byte with R/W bit set to one, the first data byte, the master issues an acknowledge as the 24XX64 issues an acknowledge and transmits the opposed to the Stop condition used in a random read. eight-bit data word. The master will not acknowledge This acknowledge directs the 24XX64 to transmit the the transfer, but does generate a Stop condition and the next sequentially-addressed 8-bit word (Figure8-3). 24XX64 discontinues transmission (Figure8-1). Following the final byte being transmitted to the master, the master will NOT generate an acknowledge, but will 8.2 Random Read generate a Stop condition. To provide sequential reads, the 24XX64 contains an internal Address Pointer which Random read operations allow the master to access is incremented by one at the completion of each any memory location in a random manner. To operation. This Address Pointer allows the entire perform this type of read operation, the word address memory contents to be serially read during one opera- must first be set. This is accomplished by sending tion. The internal Address Pointer will automatically roll the word address to the 24XX64 as part of a write over from address 1FFF to address 0000 if the master operation (R/W bit set to ‘0’). Once the word address acknowledges the byte received from the array address is sent, the master generates a Start condition 1FFF. following the acknowledge. FIGURE 8-1: CURRENT ADDRESS READ S Bus Activity T Control S Master A Byte Data (n) T R O T P SDA Line S P A N Bus Activity C O K A C K  1997-2012 Microchip Technology Inc. DS21189T-page 11

24AA64/24LC64/24FC64 FIGURE 8-2: RANDOM READ S S Bus Activity T T S Master A Control Address Address A Control Data T R Byte High Byte Low Byte R Byte Byte O T T P SDA Line S1 0 1 0AAA0 x x x S 1 01 0 AAA1 P 2 1 0 2 1 0 A A A A N Bus Activity C C C C O K K K K A x = “don’t care” bit C K FIGURE 8-3: SEQUENTIAL READ S Bus Activity Control T Master Byte Data n Data n + 1 Data n + 2 Data n + x O P SDA Line P A A A A N C C C C O Bus Activity K K K K A C K DS21189T-page 12  1997-2012 Microchip Technology Inc.

24AA64/24LC64/24FC64 9.0 PACKAGING INFORMATION 9.1 Package Marking Information 8-Lead PDIP (300 mil) Example: XXXXXXXX 24LC64 T/XXXNNN I/P e 3 13F YYWW 0527 8-Lead SOIC (3.90 mm) Example: XXXXXXXT 24LC64I XXXXYYWW SN e 3 0527 NNN 13F 8-Lead SOIC (5.28 mm) Example: XXXXXXXX 24LC64 T/XXXXXX I/SM e3 YYWWNNN 052713F 8-Lead TSSOP Example: XXXX 4LB TYWW I527 NNN 13F 8-Lead MSOP Example: XXXXXT 4L64I YWWNNN 52713F 8-Lead 2x3 DFN Example: XXX 274 YWW 527 NN I3  1997-2012 Microchip Technology Inc. DS21189T-page 13

24AA64/24LC64/24FC64 8-Lead 2x3 TDFN Example: XXX A74 YWW 527 NN I3 5-Lead SOT-23 Example: XXNN 7GNN 5-Lead Chip Scale Example: XW 75 NN 13 1st Line Marking Codes Part Number TSSOP TSSOP MSOP DFN TDFN SOT-23 X-Rotated I Temp. E Temp. I Temp. E Temp. I Temp. E Temp. 24AA64 4AB 4ABX 4A64T 271 — A71 E10 7HNN 7WNN 24LC64 4LB 4LBX 4L64T 274 275 A74 A75 7GNN 7JNN 24FC64 4FB — 4F64T 27A — A7A — — — Note: T = Temperature grade (I, E) Legend: XX...X Part number or part number code T Temperature (I, E) Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code (2 characters for small packages) e3 Pb-free JEDEC designator for Matte Tin (Sn) Note: For very small packages with no room for the Pb-free JEDEC designator e3 , the marking will only appear on the outer carton or reel label. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. DS21189T-page 14  1997-2012 Microchip Technology Inc.

24AA64/24LC64/24FC64 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)(cid:15)(cid:16)(cid:6)(cid:10)(cid:8)(cid:17)(cid:18)(cid:3)(cid:4)(cid:13)(cid:18)(cid:5)(cid:8)(cid:19)(cid:9)(cid:20)(cid:8)(cid:21)(cid:8)(cid:22)(cid:23)(cid:23)(cid:8)(cid:24)(cid:13)(cid:10)(cid:8)(cid:25)(cid:26)(cid:7)(cid:27)(cid:8)(cid:28)(cid:9)(cid:15)(cid:17)(cid:9)(cid:29) (cid:30)(cid:26)(cid:12)(cid:5)(cid:31) 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) N NOTE1 E1 1 2 3 D E A A2 L A1 c e eB b1 b 6(cid:15)(cid:7)&! (cid:19)7,8.(cid:22) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:2)9(cid:7)’(cid:7)&! (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7"’)(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)(cid:31)(cid:7)(cid:15)! 7 < (cid:31)(cid:7)&(cid:8)(cid:11) (cid:14) (cid:20)(cid:30)(cid:4)(cid:4)(cid:2)1(cid:22), (cid:13)(cid:10)(cid:12)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)&(cid:7)(cid:15)(cid:17)(cid:2)(cid:31)(cid:16)(cid:28)(cid:15)(cid:14) (cid:25) = = (cid:20)(cid:3)(cid:30)(cid:4) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:25)(cid:3) (cid:20)(cid:30)(cid:30)(cid:29) (cid:20)(cid:30)-(cid:4) (cid:20)(cid:30)(cid:24)(cid:29) 1(cid:28)!(cid:14)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)&(cid:7)(cid:15)(cid:17)(cid:2)(cid:31)(cid:16)(cid:28)(cid:15)(cid:14) (cid:25)(cid:30) (cid:20)(cid:4)(cid:30)(cid:29) = = (cid:22)(cid:11)(cid:10)"(cid:16)#(cid:14)(cid:9)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:11)(cid:10)"(cid:16)#(cid:14)(cid:9)(cid:2)>(cid:7)#&(cid:11) . (cid:20)(cid:3)(cid:24)(cid:4) (cid:20)-(cid:30)(cid:4) (cid:20)-(cid:3)(cid:29) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)>(cid:7)#&(cid:11) .(cid:30) (cid:20)(cid:3)(cid:23)(cid:4) (cid:20)(cid:3)(cid:29)(cid:4) (cid:20)(cid:3)<(cid:4) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21) (cid:20)-(cid:23)< (cid:20)-?(cid:29) (cid:20)(cid:23)(cid:4)(cid:4) (cid:13)(cid:7)(cid:12)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)&(cid:7)(cid:15)(cid:17)(cid:2)(cid:31)(cid:16)(cid:28)(cid:15)(cid:14) 9 (cid:20)(cid:30)(cid:30)(cid:29) (cid:20)(cid:30)-(cid:4) (cid:20)(cid:30)(cid:29)(cid:4) 9(cid:14)(cid:28)#(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:8) (cid:20)(cid:4)(cid:4)< (cid:20)(cid:4)(cid:30)(cid:4) (cid:20)(cid:4)(cid:30)(cid:29) 6(cid:12)(cid:12)(cid:14)(cid:9)(cid:2)9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) )(cid:30) (cid:20)(cid:4)(cid:23)(cid:4) (cid:20)(cid:4)?(cid:4) (cid:20)(cid:4)(cid:5)(cid:4) 9(cid:10)*(cid:14)(cid:9)(cid:2)9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) ) (cid:20)(cid:4)(cid:30)(cid:23) (cid:20)(cid:4)(cid:30)< (cid:20)(cid:4)(cid:3)(cid:3) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)(cid:26)(cid:10)*(cid:2)(cid:22)(cid:12)(cid:28)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:2)+ (cid:14)1 = = (cid:20)(cid:23)-(cid:4) (cid:30)(cid:26)(cid:12)(cid:5)(cid:11)(cid:31) (cid:30)(cid:20) (cid:31)(cid:7)(cid:15)(cid:2)(cid:30)(cid:2) (cid:7)!"(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)#(cid:14)$(cid:2)%(cid:14)(cid:28)&"(cid:9)(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)((cid:2))"&(cid:2)’"!&(cid:2))(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)*(cid:7)&(cid:11)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)&(cid:8)(cid:11)(cid:14)#(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) +(cid:2)(cid:22)(cid:7)(cid:17)(cid:15)(cid:7)%(cid:7)(cid:8)(cid:28)(cid:15)&(cid:2),(cid:11)(cid:28)(cid:9)(cid:28)(cid:8)&(cid:14)(cid:9)(cid:7)!&(cid:7)(cid:8)(cid:20) -(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)!(cid:2)(cid:21)(cid:2)(cid:28)(cid:15)#(cid:2).(cid:30)(cid:2)#(cid:10)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)"#(cid:14)(cid:2)’(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:20)(cid:2)(cid:6)(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:2)!(cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:14)$(cid:8)(cid:14)(cid:14)#(cid:2)(cid:20)(cid:4)(cid:30)(cid:4)/(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)!(cid:7)#(cid:14)(cid:20) (cid:23)(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)#(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6).(cid:2)0(cid:30)(cid:23)(cid:20)(cid:29)(cid:6)(cid:20) 1(cid:22),2(cid:2)1(cid:28)!(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)&(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)$(cid:28)(cid:8)&(cid:2) (cid:28)(cid:16)"(cid:14)(cid:2)!(cid:11)(cid:10)*(cid:15)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)!(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17),(cid:4)(cid:23)(cid:27)(cid:4)(cid:30)<1  1997-2012 Microchip Technology Inc. DS21189T-page 15

24AA64/24LC64/24FC64 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS21189T-page 16  1997-2012 Microchip Technology Inc.

24AA64/24LC64/24FC64 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  1997-2012 Microchip Technology Inc. DS21189T-page 17

24AA64/24LC64/24FC64 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8) (cid:24)(cid:6)(cid:10)(cid:10)(cid:8)!(cid:16)(cid:12)(cid:10)(cid:13)(cid:18)(cid:5)(cid:8)(cid:19) (cid:30)(cid:20)(cid:8)(cid:21)(cid:8)(cid:30)(cid:6)""(cid:26)#$(cid:8)(cid:22)%&(cid:23)(cid:8)(cid:24)(cid:24)(cid:8)(cid:25)(cid:26)(cid:7)(cid:27)(cid:8)(cid:28) !(cid:17)’(cid:29) (cid:30)(cid:26)(cid:12)(cid:5)(cid:31) 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) DS21189T-page 18  1997-2012 Microchip Technology Inc.

24AA64/24LC64/24FC64 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  1997-2012 Microchip Technology Inc. DS21189T-page 19

24AA64/24LC64/24FC64 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS21189T-page 20  1997-2012 Microchip Technology Inc.

24AA64/24LC64/24FC64 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  1997-2012 Microchip Technology Inc. DS21189T-page 21

24AA64/24LC64/24FC64 ((cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8) (cid:24)(cid:6)(cid:10)(cid:10)(cid:8)!(cid:16)(cid:12)(cid:10)(cid:13)(cid:18)(cid:5)(cid:8))"(cid:6)(cid:18)(cid:11)(cid:13)(cid:11)(cid:12)(cid:26)"(cid:8)(cid:19)!)(cid:20)(cid:8)(cid:28) !)(cid:3)*(cid:22)(cid:29) (cid:30)(cid:26)(cid:12)(cid:5)(cid:31) 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) b N E E1 1 2 3 e e1 D A A2 c φ A1 L L1 6(cid:15)(cid:7)&! (cid:6)(cid:19)99(cid:19)(cid:6).(cid:13).(cid:26)(cid:22) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:2)9(cid:7)’(cid:7)&! (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7"’)(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)(cid:31)(cid:7)(cid:15)! 7 (cid:29) 9(cid:14)(cid:28)#(cid:2)(cid:31)(cid:7)&(cid:8)(cid:11) (cid:14) (cid:4)(cid:20)(cid:24)(cid:29)(cid:2)1(cid:22), :"&!(cid:7)#(cid:14)(cid:2)9(cid:14)(cid:28)#(cid:2)(cid:31)(cid:7)&(cid:8)(cid:11) (cid:14)(cid:30) (cid:30)(cid:20)(cid:24)(cid:4)(cid:2)1(cid:22), : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)8(cid:14)(cid:7)(cid:17)(cid:11)& (cid:25) (cid:4)(cid:20)(cid:24)(cid:4) = (cid:30)(cid:20)(cid:23)(cid:29) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:25)(cid:3) (cid:4)(cid:20)<(cid:24) = (cid:30)(cid:20)-(cid:4) (cid:22)&(cid:28)(cid:15)#(cid:10)%% (cid:25)(cid:30) (cid:4)(cid:20)(cid:4)(cid:4) = (cid:4)(cid:20)(cid:30)(cid:29) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)>(cid:7)#&(cid:11) . (cid:3)(cid:20)(cid:3)(cid:4) = -(cid:20)(cid:3)(cid:4) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)>(cid:7)#&(cid:11) .(cid:30) (cid:30)(cid:20)-(cid:4) = (cid:30)(cid:20)<(cid:4) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21) (cid:3)(cid:20)(cid:5)(cid:4) = -(cid:20)(cid:30)(cid:4) 3(cid:10)(cid:10)&(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) 9 (cid:4)(cid:20)(cid:30)(cid:4) = (cid:4)(cid:20)?(cid:4) 3(cid:10)(cid:10)&(cid:12)(cid:9)(cid:7)(cid:15)& 9(cid:30) (cid:4)(cid:20)-(cid:29) = (cid:4)(cid:20)<(cid:4) 3(cid:10)(cid:10)&(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14) (cid:3) (cid:4)R = -(cid:4)R 9(cid:14)(cid:28)#(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:8) (cid:4)(cid:20)(cid:4)< = (cid:4)(cid:20)(cid:3)? 9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) ) (cid:4)(cid:20)(cid:3)(cid:4) = (cid:4)(cid:20)(cid:29)(cid:30) (cid:30)(cid:26)(cid:12)(cid:5)(cid:11)(cid:31) (cid:30)(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)!(cid:2)(cid:21)(cid:2)(cid:28)(cid:15)#(cid:2).(cid:30)(cid:2)#(cid:10)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)"#(cid:14)(cid:2)’(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:20)(cid:2)(cid:6)(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:2)!(cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:14)$(cid:8)(cid:14)(cid:14)#(cid:2)(cid:4)(cid:20)(cid:30)(cid:3)(cid:5)(cid:2)’’(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)!(cid:7)#(cid:14)(cid:20) (cid:3)(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)#(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6).(cid:2)0(cid:30)(cid:23)(cid:20)(cid:29)(cid:6)(cid:20) 1(cid:22),2 1(cid:28)!(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)&(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)$(cid:28)(cid:8)&(cid:2) (cid:28)(cid:16)"(cid:14)(cid:2)!(cid:11)(cid:10)*(cid:15)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)!(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17),(cid:4)(cid:23)(cid:27)(cid:4)(cid:24)(cid:30)1 DS21189T-page 22  1997-2012 Microchip Technology Inc.

24AA64/24LC64/24FC64 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  1997-2012 Microchip Technology Inc. DS21189T-page 23

24AA64/24LC64/24FC64 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8))+(cid:13)(cid:18)(cid:8) +"(cid:13)(cid:18),(cid:8) (cid:24)(cid:6)(cid:10)(cid:10)(cid:8)!(cid:16)(cid:12)(cid:10)(cid:13)(cid:18)(cid:5)(cid:8)(cid:19) )(cid:20)(cid:8)(cid:21)(cid:8)-%-(cid:8)(cid:24)(cid:24)(cid:8)(cid:25)(cid:26)(cid:7)(cid:27)(cid:8)(cid:28)) !(cid:9)(cid:29) (cid:30)(cid:26)(cid:12)(cid:5)(cid:31) 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) D N E E1 NOTE1 1 2 b e c φ A A2 A1 L1 L 6(cid:15)(cid:7)&! (cid:6)(cid:19)99(cid:19)(cid:6).(cid:13).(cid:26)(cid:22) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:2)9(cid:7)’(cid:7)&! (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7"’)(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)(cid:31)(cid:7)(cid:15)! 7 < (cid:31)(cid:7)&(cid:8)(cid:11) (cid:14) (cid:4)(cid:20)?(cid:29)(cid:2)1(cid:22), : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)8(cid:14)(cid:7)(cid:17)(cid:11)& (cid:25) = = (cid:30)(cid:20)(cid:3)(cid:4) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:25)(cid:3) (cid:4)(cid:20)<(cid:4) (cid:30)(cid:20)(cid:4)(cid:4) (cid:30)(cid:20)(cid:4)(cid:29) (cid:22)&(cid:28)(cid:15)#(cid:10)%%(cid:2) (cid:25)(cid:30) (cid:4)(cid:20)(cid:4)(cid:29) = (cid:4)(cid:20)(cid:30)(cid:29) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)>(cid:7)#&(cid:11) . ?(cid:20)(cid:23)(cid:4)(cid:2)1(cid:22), (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)>(cid:7)#&(cid:11) .(cid:30) (cid:23)(cid:20)-(cid:4) (cid:23)(cid:20)(cid:23)(cid:4) (cid:23)(cid:20)(cid:29)(cid:4) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21) (cid:3)(cid:20)(cid:24)(cid:4) -(cid:20)(cid:4)(cid:4) -(cid:20)(cid:30)(cid:4) 3(cid:10)(cid:10)&(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) 9 (cid:4)(cid:20)(cid:23)(cid:29) (cid:4)(cid:20)?(cid:4) (cid:4)(cid:20)(cid:5)(cid:29) 3(cid:10)(cid:10)&(cid:12)(cid:9)(cid:7)(cid:15)& 9(cid:30) (cid:30)(cid:20)(cid:4)(cid:4)(cid:2)(cid:26).3 3(cid:10)(cid:10)&(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14) (cid:3) (cid:4)R = <R 9(cid:14)(cid:28)#(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:8) (cid:4)(cid:20)(cid:4)(cid:24) = (cid:4)(cid:20)(cid:3)(cid:4) 9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) ) (cid:4)(cid:20)(cid:30)(cid:24) = (cid:4)(cid:20)-(cid:4) (cid:30)(cid:26)(cid:12)(cid:5)(cid:11)(cid:31) (cid:30)(cid:20) (cid:31)(cid:7)(cid:15)(cid:2)(cid:30)(cid:2) (cid:7)!"(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)#(cid:14)$(cid:2)%(cid:14)(cid:28)&"(cid:9)(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)((cid:2))"&(cid:2)’"!&(cid:2))(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)*(cid:7)&(cid:11)(cid:7)(cid:15)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)&(cid:8)(cid:11)(cid:14)#(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)!(cid:2)(cid:21)(cid:2)(cid:28)(cid:15)#(cid:2).(cid:30)(cid:2)#(cid:10)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)"#(cid:14)(cid:2)’(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:20)(cid:2)(cid:6)(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:2)!(cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:14)$(cid:8)(cid:14)(cid:14)#(cid:2)(cid:4)(cid:20)(cid:30)(cid:29)(cid:2)’’(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)!(cid:7)#(cid:14)(cid:20) -(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)#(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6).(cid:2)0(cid:30)(cid:23)(cid:20)(cid:29)(cid:6)(cid:20) 1(cid:22),2 1(cid:28)!(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)&(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)$(cid:28)(cid:8)&(cid:2) (cid:28)(cid:16)"(cid:14)(cid:2)!(cid:11)(cid:10)*(cid:15)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)!(cid:20) (cid:26).32 (cid:26)(cid:14)%(cid:14)(cid:9)(cid:14)(cid:15)(cid:8)(cid:14)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)((cid:2)"!"(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)((cid:2)%(cid:10)(cid:9)(cid:2)(cid:7)(cid:15)%(cid:10)(cid:9)’(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:12)"(cid:9)(cid:12)(cid:10)!(cid:14)!(cid:2)(cid:10)(cid:15)(cid:16)(cid:18)(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17),(cid:4)(cid:23)(cid:27)(cid:4)<?1 DS21189T-page 24  1997-2012 Microchip Technology Inc.

24AA64/24LC64/24FC64 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  1997-2012 Microchip Technology Inc. DS21189T-page 25

24AA64/24LC64/24FC64 Note: For the mostcurrent package drawings,please seetheMicrochip Packaging Specification located at http://www.microchip.com/packaging DS21189T-page 26  1997-2012 Microchip Technology Inc.

24AA64/24LC64/24FC64 Note: For the mostcurrent package drawings,please seetheMicrochip Packaging Specification located at http://www.microchip.com/packaging  1997-2012 Microchip Technology Inc. DS21189T-page 27

24AA64/24LC64/24FC64 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS21189T-page 28  1997-2012 Microchip Technology Inc.

24AA64/24LC64/24FC64 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)(cid:15)(cid:16)(cid:6)(cid:10)(cid:8).(cid:10)(cid:6)(cid:12)$(cid:8)(cid:30)(cid:26)(cid:8)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:6)(cid:14),(cid:6)/(cid:5)(cid:8)(cid:19)0’(cid:20)(cid:8)(cid:21)(cid:8)*1(cid:22)1(cid:23)%&(cid:8)(cid:24)(cid:24)(cid:8)(cid:25)(cid:26)(cid:7)(cid:27)(cid:8)(cid:28)(cid:15).(cid:30)(cid:29) (cid:30)(cid:26)(cid:12)(cid:5)(cid:31) 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) D e b N N L K E E2 EXPOSEDPAD NOTE1 NOTE1 1 2 2 1 D2 TOPVIEW BOTTOMVIEW A NOTE2 A3 A1 6(cid:15)(cid:7)&! (cid:6)(cid:19)99(cid:19)(cid:6).(cid:13).(cid:26)(cid:22) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:2)9(cid:7)’(cid:7)&! (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7"’)(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)(cid:31)(cid:7)(cid:15)! 7 < (cid:31)(cid:7)&(cid:8)(cid:11) (cid:14) (cid:4)(cid:20)(cid:29)(cid:4)(cid:2)1(cid:22), : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)8(cid:14)(cid:7)(cid:17)(cid:11)& (cid:25) (cid:4)(cid:20)<(cid:4) (cid:4)(cid:20)(cid:24)(cid:4) (cid:30)(cid:20)(cid:4)(cid:4) (cid:22)&(cid:28)(cid:15)#(cid:10)%%(cid:2) (cid:25)(cid:30) (cid:4)(cid:20)(cid:4)(cid:4) (cid:4)(cid:20)(cid:4)(cid:3) (cid:4)(cid:20)(cid:4)(cid:29) ,(cid:10)(cid:15)&(cid:28)(cid:8)&(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:25)- (cid:4)(cid:20)(cid:3)(cid:4)(cid:2)(cid:26).3 : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21) (cid:3)(cid:20)(cid:4)(cid:4)(cid:2)1(cid:22), : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)>(cid:7)#&(cid:11) . -(cid:20)(cid:4)(cid:4)(cid:2)1(cid:22), .$(cid:12)(cid:10)!(cid:14)#(cid:2)(cid:31)(cid:28)#(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21)(cid:3) (cid:30)(cid:20)-(cid:4) = (cid:30)(cid:20)(cid:29)(cid:29) .$(cid:12)(cid:10)!(cid:14)#(cid:2)(cid:31)(cid:28)#(cid:2)>(cid:7)#&(cid:11) .(cid:3) (cid:30)(cid:20)(cid:29)(cid:4) = (cid:30)(cid:20)(cid:5)(cid:29) ,(cid:10)(cid:15)&(cid:28)(cid:8)&(cid:2)>(cid:7)#&(cid:11) ) (cid:4)(cid:20)(cid:3)(cid:4) (cid:4)(cid:20)(cid:3)(cid:29) (cid:4)(cid:20)-(cid:4) ,(cid:10)(cid:15)&(cid:28)(cid:8)&(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) 9 (cid:4)(cid:20)-(cid:4) (cid:4)(cid:20)(cid:23)(cid:4) (cid:4)(cid:20)(cid:29)(cid:4) ,(cid:10)(cid:15)&(cid:28)(cid:8)&(cid:27)&(cid:10)(cid:27).$(cid:12)(cid:10)!(cid:14)#(cid:2)(cid:31)(cid:28)# U (cid:4)(cid:20)(cid:3)(cid:4) = = (cid:30)(cid:26)(cid:12)(cid:5)(cid:11)(cid:31) (cid:30)(cid:20) (cid:31)(cid:7)(cid:15)(cid:2)(cid:30)(cid:2) (cid:7)!"(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)#(cid:14)$(cid:2)%(cid:14)(cid:28)&"(cid:9)(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)((cid:2))"&(cid:2)’"!&(cid:2))(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)*(cid:7)&(cid:11)(cid:7)(cid:15)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)&(cid:8)(cid:11)(cid:14)#(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) (cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2)(cid:11)(cid:28) (cid:14)(cid:2)(cid:10)(cid:15)(cid:14)(cid:2)(cid:10)(cid:9)(cid:2)’(cid:10)(cid:9)(cid:14)(cid:2)(cid:14)$(cid:12)(cid:10)!(cid:14)#(cid:2)&(cid:7)(cid:14)(cid:2))(cid:28)(cid:9)!(cid:2)(cid:28)&(cid:2)(cid:14)(cid:15)#!(cid:20) -(cid:20) (cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)(cid:7)!(cid:2)!(cid:28)*(cid:2)!(cid:7)(cid:15)(cid:17)"(cid:16)(cid:28)&(cid:14)#(cid:20) (cid:23)(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)#(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6).(cid:2)0(cid:30)(cid:23)(cid:20)(cid:29)(cid:6)(cid:20) 1(cid:22),2 1(cid:28)!(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)&(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)$(cid:28)(cid:8)&(cid:2) (cid:28)(cid:16)"(cid:14)(cid:2)!(cid:11)(cid:10)*(cid:15)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)!(cid:20) (cid:26).32 (cid:26)(cid:14)%(cid:14)(cid:9)(cid:14)(cid:15)(cid:8)(cid:14)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)((cid:2)"!"(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)((cid:2)%(cid:10)(cid:9)(cid:2)(cid:7)(cid:15)%(cid:10)(cid:9)’(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:12)"(cid:9)(cid:12)(cid:10)!(cid:14)!(cid:2)(cid:10)(cid:15)(cid:16)(cid:18)(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17),(cid:4)(cid:23)(cid:27)(cid:30)(cid:3)-,  1997-2012 Microchip Technology Inc. DS21189T-page 29

24AA64/24LC64/24FC64 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS21189T-page 30  1997-2012 Microchip Technology Inc.

24AA64/24LC64/24FC64 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  1997-2012 Microchip Technology Inc. DS21189T-page 31

24AA64/24LC64/24FC64 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS21189T-page 32  1997-2012 Microchip Technology Inc.

24AA64/24LC64/24FC64 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)(cid:15)(cid:16)(cid:6)(cid:10)(cid:8).(cid:10)(cid:6)(cid:12)$(cid:8)(cid:30)(cid:26)(cid:8)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:6)(cid:14),(cid:6)/(cid:5)(cid:8)(cid:19)0(cid:30)(cid:20)(cid:8)(cid:21)(cid:8)*1(cid:22)1(cid:23)%2((cid:8)(cid:24)(cid:24)(cid:8)(cid:25)(cid:26)(cid:7)(cid:27)(cid:8)(cid:28))(cid:15).(cid:30)(cid:29) (cid:30)(cid:26)(cid:12)(cid:5)(cid:31) 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)  1997-2012 Microchip Technology Inc. DS21189T-page 33

24AA64/24LC64/24FC64 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS21189T-page 34  1997-2012 Microchip Technology Inc.

24AA64/24LC64/24FC64 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Please contact your local Microchip representative for specific details.  1997-2012 Microchip Technology Inc. DS21189T-page 35

24AA64/24LC64/24FC64 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS21189T-page 36  1997-2012 Microchip Technology Inc.

24AA64/24LC64/24FC64 APPENDIX A: REVISION HISTORY Revision H (12/2003) Corrections to Section 1.0, Electrical Characteristics. Revision J (04/2005) Added DFN package. Revision K (08/2005) Revised Sections 7.1 and 7.4. Revision L (03/2007) Added 24FC64 Part; Revised Device Selection Table; Revised Features Section; Deleted Rotated TSSOP Package; Revised Table 1-2; Revised Table 7-1; Revised Package Information; Replaced Package Drawings; Revised Product ID Section. Revision M (01/2009) Updated package drawings. Added 8-lead TDFN and 5-lead SOT-23 packages. Revision N (03/2009) Added 5-lead Chip Scale package. Revision P (03/2009) Added 5-lead Chip Scale Package Diagram and Land Pattern. Revised Block Diagram. Revision Q (06/09) Revised Features section; Revised Table 1-2, Para. 18; Added note to Table 2-1; Revised SOT-23 package example. Revision R (03/2010) Added TSSOP X-Rotated package; Updated Package Drawings; Updated Product ID. Revision S (01/2012) Updated Package Drawings: Updated Product ID. Revision T (12/2012) Revised Automotive E-temp; Product ID System.  1997-2012 Microchip Technology Inc. DS21189T-page 37

24AA64/24LC64/24FC64 NOTES: DS21189T-page 38  1997-2012 Microchip Technology Inc.

24AA64/24LC64/24FC64 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at Users of Microchip products can receive assistance www.microchip.com. This web site is used as a means through several channels: to make files and information easily available to • Distributor or Representative customers. Accessible by using your favorite Internet • Local Sales Office browser, the web site contains the following • Field Application Engineer (FAE) information: • Technical Support • Product Support – Data sheets and errata, • Development Systems Information Line application notes and sample programs, design resources, user’s guides and hardware support Customers should contact their distributor, documents, latest software releases and archived representative or field application engineer (FAE) for software support. Local sales offices are also available to help • General Technical Support – Frequently Asked customers. A listing of sales offices and locations is Questions (FAQ), technical support requests, included in the back of this document. online discussion groups, Microchip consultant Technical support is available through the web site program member listing at: http://microchip.com/support • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions.  1997-2012 Microchip Technology Inc. DS21189T-page 39

24AA64/24LC64/24FC64 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480)792-4150. Please list the following information, and use this outline to provide us with your comments about this document. TO: Technical Publications Manager Total Pages Sent ________ RE: Reader Response From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y N Device: 24AA64/24LC64/24FC64 Literature Number: DS21189T Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS21189T-page 40  1997-2012 Microchip Technology Inc.

24AA64/24LC64/24FC64 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. XX /XX Examples: Device Temperature Package a) 24AA64-I/P: Industrial Temperature, Range 1.7V, PDIP package b) 24AA64-I/SN: Industrial Temperature, Device: 24AA64: 1.7V, 64 Kbit I2C™ Serial EEPROM 1.7V, SOIC package 24AA64T: 1.7V, 64 Kbit I2C Serial EEPROM c) 24AA64-I/SM: Industrial Temperature, (Tape and Reel) 1.7V, SOIC (5.28 mm) package 24AA64X: 1.7V, 64 Kbit I2C Serial EEPROM in d) 24AA64T-I/ST: Industrial Temperature, alternate pinout (ST only) 1.7V, TSSOP package, tape and reel 24AA64XT: 1.7V, 64 KbitI2C Serial EEPROM in e) 24LC64-I/P: Industrial Temperature, alternate pinout (ST only) 2.5V, PDIP package 24LC64: 2.5V, 64 Kbit I2C Serial EEPROM 24LC64T: 2.5V, 64 Kbit I2C Serial EEPROM f) 24LC64-E/SN: Extended Temperature, 2.5V, SOIC package (Tape and Reel) 24LC64X: 2.5V, 64 Kbit I2C Serial EEPROM in g) 24LC64-E/SM: Extended Temperature, alternate pinout (ST only) 2.5V, SOIC (5.28 mm) package 24LC64XT: 2.5V, 64 Kbit I2C Serial EEPROM in h) 24LC64-I/ST: Industrial Temperature, alternate pinout (ST only) 2.5V, TSSOP package 24FC64: 2.5V, 64 Kbit I2C Serial EEPROM i) 24AA64T-I/CS16K: Industrial Tempera- 24FC64T: 2.5V, 64 Kbit I2C Serial EEPROM (Tape ture, 1.7V, CS package, tape and reel and Reel) j) 24AA64T-E/SN: Extended Temperature, 1.7V, SOIC package, tape and reel Temperature I = -40°C to +85°C Range: E = -40°C to +125°C Package: P = Plastic DIP (300 mil body), 8-lead SN = Plastic SOIC (3.90 mm body), 8-lead SM = Plastic SOIC (5.28 mm body), 8-lead ST = Plastic TSSOP (4.4 mm), 8-lead MS = Plastic MSOP (Micro Small Outline), 8-lead MC = Plastic DFN (2x3x0.9 mm body), 8-lead MNY(1)= Plastic TDFN (2x3x0.75 mm body), 8-lead OT = Plastic SOT-23, 5-lead (Tape and Reel only) CS16K(2)=Chip Scale (CS), 5-lead (I-temp, "AA", Tape and Reel only) Note 1: "Y" indicates a Nickel Palladium Gold (NiPdAu) finish. 2: "16K" indicates 160K technology.  1997-2012 Microchip Technology Inc. DS21189T-page41

24AA64/24LC64/24FC64 NOTES: DS21189T-page 42  1997-2012 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC, and may be superseded by updates. It is your responsibility to FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, ensure that your application meets with your specifications. PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash MICROCHIP MAKES NO REPRESENTATIONS OR and UNI/O are registered trademarks of Microchip Technology WARRANTIES OF ANY KIND WHETHER EXPRESS OR Incorporated in the U.S.A. and other countries. IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, INCLUDING BUT NOT LIMITED TO ITS CONDITION, MTP, SEEVAL and The Embedded Control Solutions QUALITY, PERFORMANCE, MERCHANTABILITY OR Company are registered trademarks of Microchip Technology FITNESS FOR PURPOSE. Microchip disclaims all liability Incorporated in the U.S.A. arising from this information and its use. Use of Microchip Silicon Storage Technology is a registered trademark of devices in life support and/or safety applications is entirely at Microchip Technology Inc. in other countries. the buyer’s risk, and the buyer agrees to defend, indemnify and Analog-for-the-Digital Age, Application Maestro, BodyCom, hold harmless Microchip from any and all damages, claims, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, suits, or expenses resulting from such use. No licenses are dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, conveyed, implicitly or otherwise, under any Microchip ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial intellectual property rights. Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O, Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA and Z-Scale are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. GestIC and ULPP are registered trademarks of Microchip Technology Germany II GmbH & Co. & KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 1997-2012, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 9781620767641 QUALITY MANAGEMENT SYSTEM Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and CERTIFIED BY DNV Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures == ISO/TS 16949 == are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.  1997-2012 Microchip Technology Inc. DS21189T-page 43

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Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: M icrochip: 24LC64-I/ST 24LC64-I/PG 24LC64-I/SN 24LC64-I/SM 24LC64-I/MS 24LC64-E/SNG 24LC64-I/SMG 24LC64- I/SNG 24LC64-I/STG 24AA64T-I/SN 24AA64T-I/SM 24AA64T-I/ST 24AA64-I/MSG 24AA64T-I/MSG 24AA64T- I/STG 24AA64T-I/SNG 24LC64-I/MSG 24LC64T-I/SNG 24LC64T-I/STG 24AA64T-I/SMG 24LC64T-E/ST 24LC64T- E/SN 24LC64T-E/MS 24LC64T-E/SM 24AA64-I/P 24LC64-I/P 24LC64T-I/MS 24LC64T-I/ST 24LC64T-I/SN 24LC64-E/ST 24LC64-E/SM 24LC64-E/SN 24AA64/SN 24AA64/SM 24LC64-E/MS 24AA64/P 24AA64-I/SMG 24AA64-I/STG 24AA64-I/SNG 24LC64T-I/MSG 24AA64T-I/MS 24LC64T-I/SMG 24AA64T/SM 24AA64T/SN 24AA64-I/PG 24AA64-I/SN 24AA64-I/SM 24AA64-I/MS 24AA64-I/ST 24LC64T-E/SNG 24LC64-E/P 24AA64T- I/CS16K 24AA64T-I/MC 24LC64T-I/MC 24LC64T-I/SM 24FC64-I/MC 24FC64-I/MF 24FC64-I/MS 24FC64-I/P 24FC64-I/SM 24FC64-I/SN 24FC64-I/ST 24FC64T-I/MC 24FC64T-I/MF 24FC64T-I/MS 24FC64T-I/SM 24FC64T- I/SN 24FC64T-I/ST 24AA64T-I/MNY 24LC64-E/MNY 24LC64T-I/OT 24LC64T-I/MNY 24FC64T-I/OT 24FC64-I/MNY 24AA64-I/MNY 24FC64T-I/MNY 24AA64T-I/OT 24LC64T-E/MNY 24LC64-I/MNY 24LC64T-E/OT 24AA64-E/P 24AA64T-E/ST 24AA64-E/SN 24AA64-E/MS 24AA64-E/ST 24AA64T-E/SM 24AA64T-E/MS 24AA64T-E/SN 24AA64-E/SM 24AA64T-E/OT 24AA64T-E/MNY