24AA515/24LC515/24FC515 2 512K I C™ CMOS Serial EEPROM Device Selection Table Package Type PDIP Part VCC Max Clock Temp Number Range Frequency Ranges A0 1 8 VCC 2 24AA515 1.8-5.5V 400kHz† I A1 2 4 7 WP A A 24LC515 2.5-5.5V 400kHz I A2 3 5 6 SCL 1 24FC515 2.5-5.5V 1MHz I 5 / VSS 4 5 SDA †100kHz for VCC < 2.5V. Features SOIC • Low-power CMOS technology A0 1 8 VCC - Maximum write current 3mA at 5.5V 2 - Maximum read current 400µA at 5.5V A1 2 4A 7 WP A - Standby current 100nA typical at 5.5V A2 3 51 6 SCL (cid:127) 2-wire serial interface bus, I 2C™ compatible VSS 4 5/ 5 SDA (cid:127) Cascadable for up to four devices (cid:127) Self-timed ERASE/WRITE cycle (cid:127) 64-byte Page Write mode available (cid:127) 5ms max write cycle time Block Diagram (cid:127) Hardware write-protect for entire array (cid:127) Output slope control to eliminate ground bounce A0A1 WP HVGenerator (cid:127) Schmitt Trigger inputs for noise suppression (cid:127) 100,000 erase/write cycles (cid:127) Electrostatic discharge protection > 4000V I/O Memory EEPROM Control Control XDEC Array (cid:127) Data retention > 200 years Logic Logic (cid:127) 8-pin PDIP, SOIC packages Page Latches (cid:127) Temperature ranges: I/O - Industrial (I): -40°C to +85°C SCL YDEC Description SDA The Microchip Technology Inc. 24AA515/24LC515/ VCC 24FC515 (24XX515*) is a 64K x 8 (512K bit) Serial VSS Sense AMP Electrically Erasable PROM, capable of operation R/W Control across a broad voltage range (1.8V to 5.5V). It has been developed for advanced, low power applications such as personal communications or data acquisition. This device has both byte write and page write capabil- ity of up to 64 bytes of data. This device is capable of both random and sequential reads. Reads may be sequential within address boundaries 0000h to 7FFFh & 8000h to FFFFh. Functional address lines allow up to four devices on the same data bus. This allows for up to 2Mbits total system EEPROM memory. This device is available in the standard 8-pin plastic DIP and SOIC packages. 24XX515 is used in this document as a generic part number for the 24AA515/24LC515/24FC515 devices. Preliminary  2003 Microchip Technology Inc. DS21673C-page 1

24AA515/24LC515/24FC515 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings(†) VCC.............................................................................................................................................................................6.5V All inputs and outputs w.r.t. VSS.........................................................................................................-0.6V to VCC +1.0V Storage temperature...............................................................................................................................-65°C to +150°C Ambient temperature with power applied................................................................................................-65°C to +125°C ESD protection on all pins......................................................................................................................................................≥ 4kV † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. TABLE 1-1: DC CHARACTERISTICS DC CHARACTERISTICS Industrial (I): VCC = +1.8V to 5.5V TA = -40°C to +85°C Param. Sym Characteristic Min Max Units Conditions No. D1 A0, A1, SCL, SDA, and WP pins: D2 VIH High-level input voltage 0.7 VCC — V VCC ≥ 2.5V D3 VIL Low-level input voltage — 0.3 VCC V VCC ≥ 2.5V 0.2 VCC V VCC < 2.5V D4 VHYS Hysteresis of Schmitt 0.05 VCC — V VCC ≥ 2.5V (Note) Trigger inputs (SDA, SCL pins) D5 VOL Low-level output voltage — 0.40 V IOL = 3.0mA @ VCC = 4.5V IOL = 2.1mA @ VCC = 2.5V D6 ILI Input leakage current — ±1 µA VIN = VSS or VCC, WP = VSS VIN = VSS or VCC, WP = VCC D7 ILO Output leakage current — ±1 µA VOUT = VSS or VCC D8 CIN, Pin capacitance — 10 pF VCC = 5.0V (Note) COUT (all inputs/outputs) TA = 25°C, fC= 1MHz D9 ICC Read Operating current — 400 µA VCC = 5.5V, SCL = 400kHz ICC Write — 3 mA VCC = 5.5V D10 Iccs Standby current — 5 µA SCL = SDA = VCC = 5.5V A0, A1, WP = VSS, A2 = VCC Note: This parameter is periodically sampled and not 100% tested. Preliminary DS21673C-page 2  2003 Microchip Technology Inc.

24AA515/24LC515/24FC515 TABLE 1-2: AC CHARACTERISTICS AC CHARACTERISTICS Industrial (I): VCC = +1.8V to 5.5V TA = -40°C to +85°C Param. Sym Characteristic Min. Max. Units Conditions No. 1 FCLK Clock frequency — 100 kHz 1.8V ≤ VCC ≤ 2.5V — 400 2.5V ≤ VCC ≤ 5.5V — 1000 2.5V ≤ VCC ≤ 5.5V (24FC515 only) 2 THIGH Clock high time 4000 — ns 1.8V ≤ VCC ≤ 2.5V 600 — 2.5V ≤ VCC ≤ 5.5V 500 — 2.5V ≤ VCC ≤ 5.5V (24FC515 only) 3 TLOW Clock low time 4700 — ns 1.8V ≤ VCC ≤ 2.5V 1300 — 2.5V ≤ VCC ≤ 5.5V 500 — 2.5V ≤ VCC ≤ 5.5V (24FC515 only) 4 TR SDA and SCL rise time — 1000 ns 1.8V ≤ VCC ≤ 2.5V (Note1) — 300 2.5V ≤ VCC ≤ 5.5V — 300 2.5V ≤ VCC ≤ 5.5V (24FC515 only) 5 TF SDA and SCL fall time — 300 ns All except, 24FC515 (Note1) — 100 2.5V ≤ VCC ≤ 5.5V (24FC515 only) 6 THD:STA Start condition hold time 4000 — ns 1.8V ≤ VCC ≤ 2.5V 600 — 2.5V ≤ VCC ≤ 5.5V 250 — 2.5V ≤ VCC ≤ 5.5V (24FC515 only) 7 TSU:STA Start condition setup time 4700 — ns 1.8V ≤ VCC ≤ 2.5V 600 — 2.5V ≤ VCC ≤ 5.5V 250 — 2.5V ≤ VCC ≤ 5.5V (24FC515 only) 8 THD:DAT Data input hold time 0 — ns (Note2) 9 TSU:DAT Data input setup time 250 — ns 1.8V ≤ VCC ≤ 2.5V 100 — 2.5V ≤ VCC ≤ 5.5V 100 — 2.5V ≤ VCC ≤ 5.5V (24FC515 only) 10 TSU:STO Stop condition setup time 4000 — ns 1.8V ≤ VCC ≤ 2.5V 600 — 2.5V ≤ VCC ≤ 5.5V 250 — 2.5V ≤ VCC ≤ 5.5V (24FC515 only) 11 TSU:WP WP setup time 4000 — ns 1.8V ≤ VCC ≤ 2.5V 600 — 2.5V ≤ VCC ≤ 5.5V 600 — 2.5V ≤ VCC ≤ 5.5V (24FC515 only) 12 THD:WP WP hold time 4700 — ns 1.8V ≤ VCC ≤ 2.5V 1300 — 2.5V ≤ VCC ≤ 5.5V 1300 — 2.5V ≤ VCC ≤ 5.5V (24FC515 only) 13 TAA Output valid from clock — 3500 ns 1.8V ≤ VCC ≤ 2.5V (Note2) — 900 2.5V ≤ VCC ≤ 5.5V — 400 2.5V ≤ VCC ≤ 5.5V (24FC515 only) 14 TBUF Bus free time: Time the bus 4700 — ns 1.8V ≤ VCC ≤ 2.5V must be free before a new 1300 — 2.5V ≤ VCC ≤ 5.5V transmission can start 500 — 2.5V ≤ VCC ≤ 5.5V (24FC515 only) 15 TOF Output fall time from VIH 10 + 0.1CB 250 ns All except, 24FC515 (Note1) minimum to VIL maximum 250 24FC515 (Note1) CB ≤ 100pF 16 TSP Input filter spike suppression — 50 ns All except, 24FC515 (Notes1 and3) (SDA and SCL pins) 17 TWC Write cycle time (byte or page) — 5 ms 18 Endurance 1 M — cycles 25°C, VCC = 5.0V, Block mode (Note4) Note 1: Not 100% tested. CB = total capacitance of one bus line in pF. 2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. 3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs which provide improved noise spike suppression. This eliminates the need for a TI specification for standard operation. 4: This parameter is not tested but established by characterization. For endurance estimates in a specific application, please consult the Total Endurance™ Model which can be obtained from Microchip’s web site @www.microchip.com. Preliminary  2003 Microchip Technology Inc. DS21673C-page 3

24AA515/24LC515/24FC515 FIGURE 1-1: BUS TIMING DATA 5 4 2 D4 SCL 7 3 8 9 10 SDA 6 IN 16 13 14 SDA OUT (protected) WP 11 12 (unprotected) Preliminary DS21673C-page 4  2003 Microchip Technology Inc.

24AA515/24LC515/24FC515 2.0 PIN DESCRIPTIONS 2.4 Serial Clock (SCL) The descriptions of the pins are listed in Table2-1. This input is used to synchronize the data transfer from and to the device. TABLE 2-1: PIN FUNCTION TABLE 2.5 Write-Protect (WP) Name PDIP SOIC Function A0 1 1 User Configurable Chip Select This pin can be connected to either VSS, VCC or left floating. An internal pull-down resistor on this pin will A1 2 2 User Configurable Chip Select keep this device in the unprotected state if left floating. A2 3 3 Non-Configurable Chip Select. If tied to VSS or left floating, normal memory operation This pin must be hard wired to is enabled (read/write the entire memory 0000h- logical 1 state (VCC). Device FFFFh). will not operate with this pin If tied to VCC, write operations are inhibited. Read left floating or held to logical 0 operations are not affected. (VSS). VSS 4 4 Ground 3.0 FUNCTIONAL DESCRIPTION SDA 5 5 Serial Data SCL 6 6 Serial Clock The 24XX515 supports a bidirectional 2-wire bus and data transmission protocol. A device that sends data WP 7 7 Write-Protect Input onto the bus is defined as a transmitter, and a device VCC 8 8 +1.8 to 5.5V (24AA515) receiving data as a receiver. The bus must be +2.5 to 5.5V (24LC515) controlled by a master device which generates the +4.5 to 5.5V (24FC515) serial clock (SCL), controls the bus access, and generates the Start and Stop conditions while the 2.1 A0, A1 Chip Address Inputs 24XX515 works as a slave. Both master and slave can operate as a transmitter or receiver, but the master The A0, A1 inputs are used by the 24XX515 for multiple device determines which mode is activated. device operations. The levels on these inputs are compared with the corresponding bits in the slave address. The chip is selected if the compare is true. Up to four devices may be connected to the same bus by using different Chip Select bit combinations. If left unconnected, these inputs will be pulled down internally to VSS. 2.2 A2 Chip Address Input The A2 input is non-configurable Chip Select. This pin must be tied to VCC in order for this device to operate. 2.3 Serial Data (SDA) This is a bidirectional pin used to transfer addresses and data into and data out of the device. It is an open- drain terminal, therefore, the SDA bus requires a pull- up resistor to VCC (typical 10kΩ for 100kHz, 2kΩ for 400kHz and 1MHz). For normal data transfer SDA is allowed to change only during SCL low. Changes during SCL high are reserved for indicating the Start and Stop conditions. Preliminary  2003 Microchip Technology Inc. DS21673C-page 5

24AA515/24LC515/24FC515 4.0 BUS CHARACTERISTICS The data on the line must be changed during the low period of the clock signal. There is one bit of data per The following bus protocol has been defined: clock pulse. (cid:127) Data transfer may be initiated only when the bus Each data transfer is initiated with a Start condition and is not busy. terminated with a Stop condition. The number of the (cid:127) During data transfer, the data line must remain data bytes transferred between the Start and Stop stable whenever the clock line is high. Changes in conditions is determined by the master device. the data line while the clock line is high will be interpreted as a Start or Stop condition. 4.5 Acknowledge Accordingly, the following bus conditions have been Each receiving device, when addressed, is obliged to defined (Figure4-1). generate an Acknowledge signal after the reception of each byte. The master device must generate an extra 4.1 Bus not Busy (A) clock pulse which is associated with this Acknowledge bit. Both data and clock lines remain high. Note: The 24XX515 does not generate any 4.2 Start Data Transfer (B) Acknowledge bits if an internal program- ming cycle is in progress. A high-to-low transition of the SDA line while the clock A device that acknowledges must pull-down the SDA (SCL) is high determines a Start condition. All line during the Acknowledge clock pulse in such a way commands must be preceded by a Start condition. that the SDA line is stable low during the high period of the acknowledge related clock pulse. Of course, setup 4.3 Stop Data Transfer (C) and hold times must be taken into account. During A low-to-high transition of the SDA line while the clock reads, a master must signal an end of data to the slave (SCL) is high determines a Stop condition. All by NOT generating an Acknowledge bit on the last byte operations must end with a Stop condition. that has been clocked out of the slave. In this case, the slave (24XX515) will leave the data line high to enable 4.4 Data Valid (D) the master to generate the Stop condition. The state of the data line represents valid data when, after a Start condition, the data line is stable for the duration of the high period of the clock signal. FIGURE 4-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS (A) (B) (D) (D) (C) (A) SCL SDA Start Address or Data Stop Condition Acknowledge Allowed Condition Valid To Change FIGURE 4-2: ACKNOWLEDGE TIMING Acknowledge Bit SCL 1 2 3 4 5 6 7 8 9 1 2 3 SDA Data from transmitter Data from transmitter Transmitter must release the SDA line at this point Receiver must release the SDA line at this point allowing the Receiver to pull the SDA line low to so the Transmitter can continue sending data. acknowledge the previous eight bits of data. Preliminary DS21673C-page 6  2003 Microchip Technology Inc.

24AA515/24LC515/24FC515 5.0 DEVICE ADDRESSING FIGURE 5-1: CONTROL BYTE FORMAT A control byte is the first byte received following the Start condition from the master device (Figure5-1). Read/Write Bit The control byte consists of a 4-bit control code; for the 24XX515, this is set as ‘1010’ binary for read and write Chip Select operations. The next bit of the control byte is the block Control Code Bits select bit (B0). This bit acts as the A15 address bit for accessing the entire array. The next two bits of the S 1 0 1 0 B0 A1 A0 R/W ACK control byte are the Chip Select bits (A1, A0). The Chip Select bits allow the use of up to four 24XX515 devices Slave Address on the same bus and are used to select which device is accessed. The Chip Select bits in the control byte must Start Bit Acknowledge Bit correspond to the logic levels on the corresponding A1 and A0 pins for the device to respond. These bits are in effect the two Most Significant bits of the word address. 5.1 Contiguous Addressing Across The last bit of the control byte defines the operation to Multiple Devices be performed. When set to a one, a read operation is selected, and when set to a zero, a write operation is The Chip Select bits A1, A0 can be used to expand the selected. The next two bytes received define the contiguous address space for up to 2Mbit by adding up address of the first data byte (Figure5-2). Because to four 24XX515's on the same bus. In this case, only A14…A0 are used, the upper address bit is a don’t software can use A0 of the control byte as address bit care. The upper address bits are transferred first, A16 and A1 as address bit A17. It is not possible to followed by the less significant bits. sequentially read across device boundaries. Following the Start condition, the 24XX515 monitors Each device has internal addressing boundary the SDA bus checking the device type identifier being limitations. This divides each part into two segments of transmitted. Upon receiving a ‘1010’ code and appro- 256K bits. The block select bit ‘B0’ controls access to priate device select bits, the slave device outputs an each “half” rather than address bit location A15. Acknowledge signal on the SDA line. Depending on the Sequential read operations are limited to 256K blocks. state of the R/W bit, the 24XX515 will select a read or To read through four devices on the same bus, eight write operation. random Read commands must be given. This device has an internal addressing boundary limitation that is divided into two segments of 256K bits. Block select bit ‘B0’ is used in place of address bit location ‘A15’ to control access to each segment. FIGURE 5-2: ADDRESS SEQUENCE BIT ASSIGNMENTS CONTROL BYTE ADDRESS HIGH BYTE ADDRESS LOW BYTE B A A A A A A A A A A A 1 0 1 0 0 1 0 R/W X 14 13 12 11 10 9 8 7 (cid:127) (cid:127) (cid:127) (cid:127) (cid:127) (cid:127) 0 CONTROL BLOCK CHIP CODE SELECTSELECT X = Don’t Care Bit BIT BITS Preliminary  2003 Microchip Technology Inc. DS21673C-page 7

24AA515/24LC515/24FC515 6.0 WRITE OPERATIONS 6.3 Write Protection The WP pin allows the user to write-protect the entire 6.1 Byte Write array (0000-FFFF) when the pin is tied to VCC. If tied to Following the Start condition from the master, the VSS or left floating, the write protection is disabled. The WP pin is sampled at the Stop bit for every Write control code (four bits), the block select (one bit) the command (Figure1-1) Toggling the WP pin after the Chip Select (two bits), and the R/W bit (which is a logic Stop bit will have no effect on the execution of the write low) are clocked onto the bus by the master transmitter. cycle. This indicates to the addressed slave receiver that the address high byte will follow after it has generated an Note: Page write operations are limited to writing Acknowledge bit during the ninth clock cycle. There- bytes within a single physical page, fore, the next byte transmitted by the master is the regardless of the number of bytes actually high-order byte of the word address and will be written being written. Physical page boundaries into the address pointer of the 24XX515. The next byte start at addresses that are integer is the Least Significant Address Byte. After receiving multiples of the page buffer size (or ‘page another Acknowledge signal from the 24XX515, the size’) and end at addresses that are master device will transmit the data word to be written integer multiples of [page size - 1]. If a into the addressed memory location. The 24XX515 Page Write command attempts to write acknowledges again and the master generates a Stop across a physical page boundary, the condition. This initiates the internal write cycle and dur- result is that the data wraps around to the ing this time, the 24XX515 will not generate Acknowl- beginning of the current page (overwriting edge signals (Figure6-1). If an attempt is made to write data previously stored there), instead of to the array with the WP pin held high, the device will being written to the next page as might be acknowledge the command but no write cycle will expected. It is therefore necessary for the occur, no data will be written, and the device will application software to prevent page write immediately accept a new command. After a byte Write operations that would attempt to cross a command, the internal address counter will point to the page boundary. address location following the one that was just written. 6.2 Page Write The write control byte, word address, and the first data byte are transmitted to the 24XX515 in the same way as in a byte write. But instead of generating a Stop condition, the master transmits up to 63 additional bytes, which are temporarily stored in the on-chip page buffer and will be written into memory after the master has transmitted a Stop condition. After receipt of each word, the six lower address pointer bits are internally incremented by one. If the master should transmit more than 64 bytes prior to generating the Stop condition, the address counter will roll over and the previously received data will be overwritten. As with the byte write operation, once the Stop condition is received, an internal write cycle will begin (Figure6-2). If an attempt is made to write to the array with the WP pin held high, the device will acknowledge the command but no write cycle will occur, no data will be written, and the device will immediately accept a new command. Preliminary DS21673C-page 8  2003 Microchip Technology Inc.

24AA515/24LC515/24FC515 FIGURE 6-1: BYTE WRITE S BUS ACTIVITY T S CONTROL ADDRESS ADDRESS MASTER A T R BYTE HIGH BYTE LOW BYTE DATA O T P SDA LINE S1 0 1 0 B0A1A0 0 X P A A A A BUS ACTIVITY C C C C K K K K X = don’t care bit FIGURE 6-2: PAGE WRITE S T S BUS ACTIVITY A CONTROL ADDRESS ADDRESS T MASTER R BYTE HIGH BYTE LOW BYTE DATA BYTE 0 DATA BYTE 63 O T P SDA LINE S1 0 1 0B0A1A0 0 X P A A A A A BUS ACTIVITY C C C C C K K K K K X = don’t care bit Preliminary  2003 Microchip Technology Inc. DS21673C-page 9

24AA515/24LC515/24FC515 7.0 ACKNOWLEDGE POLLING FIGURE 7-1: ACKNOWLEDGE POLLING FLOW Since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (This feature can be used to maximize bus throughput.) Once the Stop condition for a Write Send command has been issued from the master, the device Write Command initiates the internally timed write cycle. ACK polling can be initiated immediately. This involves the master sending a Start condition, followed by the control byte Send Stop for a Write command (R/W = 0). If the device is still Condition to busy with the write cycle, then no ACK will be returned. Initiate Write Cycle If no ACK is returned, then the Start bit and control byte must be resent. If the cycle is complete, then the device will return the ACK, and the master can then proceed with the next Read or Write command. See Figure7-1 Send Start for flow diagram. Send Control Byte with R/W = 0 Did Device NO Acknowledge (ACK = 0)? YES Next Operation Preliminary DS21673C-page 10  2003 Microchip Technology Inc.

24AA515/24LC515/24FC515 8.0 READ OPERATION 8.2 Random Read Read operations are initiated in the same way as write Random read operations allow the master to access operations with the exception that the R/W bit of the any memory location in a random manner. To perform control byte is set to one. There are three basic types this type of read operation, first the word address must of read operations: current address read, random read, be set. This is done by sending the word address to the and sequential read. 24XX515 as part of a write operation (R/W bit set to 0). After the word address is sent, the master generates a 8.1 Current Address Read Start condition following the acknowledge. This termi- nates the write operation, but not before the internal The 24XX515 contains an address counter that main- address pointer is set. Then, the master issues the tains the address of the last word accessed, internally control byte again but with the R/W bit set to a one. The incremented by one. Therefore, if the previous read 24XX515 will then issue an acknowledge and transmit access was to address n (n is any legal address), the the 8-bit data word. The master will not acknowledge next current address read operation would access data the transfer but does generate a Stop condition which from address n + 1. causes the 24XX515 to discontinue transmission Upon receipt of the control byte with R/W bit set to one, (Figure8-2). After a random Read command, the inter- the 24XX515 issues an acknowledge and transmits the nal address counter will point to the address location 8-bit data word. The master will not acknowledge the following the one that was just read. transfer but does generate a Stop condition and the 24XX515 discontinues transmission (Figure8-1). 8.3 Sequential Read Sequential reads are initiated in the same way as a FIGURE 8-1: CURRENT ADDRESS random read except that after the 24XX515 transmits READ the first data byte, the master issues an acknowledge S as opposed to the Stop condition used in a random T S BUS ACTIVITY A CONTROL DATA T read. This acknowledge directs the 24XX515 to trans- MASTER R BYTE BYTE O mit the next sequentially addressed 8-bit word T P (Figure8-3). Following the final byte transmitted to the SDA LINE S 1 0 1 0 B AA 1 P master, the master will NOT generate an acknowledge 0 1 0 A N but will generate a Stop condition. To provide sequen- BUS ACTIVITY C O tial reads, the 24XX515 contains an internal address K A pointer which is incremented by one at the completion C K of each operation. This address pointer allows half the memory contents to be serially read during one opera- tion. Sequential read address boundaries are 0000h to 7FFFh and 8000h to FFFFh. The internal address pointer will automatically roll over from address 7FFF to address 0000 if the master acknowledges the byte received from the array address 7FFF. The internal address counter will automatically roll over from address FFFFh to address 8000h if the master acknowledges the byte received from the array address FFFFh. Preliminary  2003 Microchip Technology Inc. DS21673C-page 11

24AA515/24LC515/24FC515 FIGURE 8-2: RANDOM READ S S BUS ACTIVITY T T S CONTROL ADDRESS ADDRESS CONTROL DATA MASTER A A T R BYTE HIGH BYTE LOW BYTE R BYTE BYTE O T T P SDA LINE S 1 0 1 0 B A A 0 X S 1 0 1 0 B A A1 P 0 1 0 0 1 0 A A A A N BUS ACTIVITY C C C C O K K K K A C X = Don’t Care Bit K FIGURE 8-3: SEQUENTIAL READ CONTROL S BUS ACTIVITY T MASTER BYTE DATA n DATA n + 1 DATA n + 2 DATA n + X O P SDA LINE P A A A A N C C C C O BUS ACTIVITY K K K K A C K Preliminary DS21673C-page 12  2003 Microchip Technology Inc.

24AA515/24LC515/24FC515 9.0 PACKAGING INFORMATION 9.1 Package Marking Information 8-Lead PDIP (300 mil) Example: XXXXXXXX 24LC515 XXXXXNNN I/PNNN YYWW YYWW 8-Lead SOIC (208 mil) Example: XXXXXXXX 24LC515 XXXXXXXX I/SM YYWWNNN YYWWNNN Legend: XX...X Customer specific information* YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. * Standard marking consists of Microchip part number, year code, week code, traceability code (facility code, mask rev#, and assembly code). For marking beyond this, certain price adders apply. Please Preliminary  2003 Microchip Technology Inc. DS21673C-page 13

24AA515/24LC515/24FC515 8-Lead Plastic Dual In-line (P) – 300 mil (PDIP) E1 D 2 n 1 α E A A2 L c A1 β B1 p eB B Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 8 8 Pitch p .100 2.54 Top to Seating Plane A .140 .155 .170 3.56 3.94 4.32 Molded Package Thickness A2 .115 .130 .145 2.92 3.30 3.68 Base to Seating Plane A1 .015 0.38 Shoulder to Shoulder Width E .300 .313 .325 7.62 7.94 8.26 Molded Package Width E1 .240 .250 .260 6.10 6.35 6.60 Overall Length D .360 .373 .385 9.14 9.46 9.78 Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43 Lead Thickness c .008 .012 .015 0.20 0.29 0.38 Upper Lead Width B1 .045 .058 .070 1.14 1.46 1.78 Lower Lead Width B .014 .018 .022 0.36 0.46 0.56 Overall Row Spacing § eB .310 .370 .430 7.87 9.40 10.92 Mold Draft Angle Top α 5 10 15 5 10 15 Mold Draft Angle Bottom β 5 10 15 5 10 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-018 Preliminary DS21673C-page 14  2003 Microchip Technology Inc.

24AA515/24LC515/24FC515 8-Lead Plastic Small Outline (SM) – Medium, 208 mil (SOIC) E E1 p D 2 n 1 B α c A A2 φ A1 β L Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 8 8 Pitch p .050 1.27 Overall Height A .070 .075 .080 1.78 1.97 2.03 Molded Package Thickness A2 .069 .074 .078 1.75 1.88 1.98 Standoff § A1 .002 .005 .010 0.05 0.13 0.25 Overall Width E .300 .313 .325 7.62 7.95 8.26 Molded Package Width E1 .201 .208 .212 5.11 5.28 5.38 Overall Length D .202 .205 .210 5.13 5.21 5.33 Foot Length L .020 .025 .030 0.51 0.64 0.76 Foot Angle φ 0 4 8 0 4 8 Lead Thickness c .008 .009 .010 0.20 0.23 0.25 Lead Width B .014 .017 .020 0.36 0.43 0.51 Mold Draft Angle Top α 0 12 15 0 12 15 Mold Draft Angle Bottom β 0 12 15 0 12 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. Drawing No. C04-056 Preliminary  2003 Microchip Technology Inc. DS21673C-page 15

24AA515/24LC515/24FC515 APPENDIX A: REVISION HISTORY Revision C Corrections to Section 1.0, Electrical Characteristics. Preliminary DS21673C-page 16  2003 Microchip Technology Inc.

24AA515/24LC515/24FC515 ON-LINE SUPPORT SYSTEMS INFORMATION AND UPGRADE HOT LINE Microchip provides on-line support on the Microchip World Wide Web site. The Systems Information and Upgrade Line provides The web site is used by Microchip as a means to make system users a listing of the latest versions of all of files and information easily available to customers. To Microchip's development systems software products. view the site, the user must have access to the Internet Plus, this line provides information on how customers and a web browser, such as Netscape® or Microsoft® can receive the most current upgrade kits. The Hot Line Internet Explorer. Files are also available for FTP Numbers are: download from our FTP site. 1-800-755-2345 for U.S. and most of Canada, and 1-480-792-7302 for the rest of the world. Connecting to the Microchip Internet Web Site 042003 The Microchip web site is available at the following URL: www.microchip.com The file transfer site is available by using an FTP service to connect to: ftp://ftp.microchip.com The web site and file transfer site provide a variety of services. Users may download files for the latest Development Tools, Data Sheets, Application Notes, User's Guides, Articles and Sample Programs. A vari- ety of Microchip specific business information is also available, including listings of Microchip sales offices, distributors and factory representatives. Other data available for consideration is: (cid:127) Latest Microchip Press Releases (cid:127) Technical Support Section with Frequently Asked Questions (cid:127) Design Tips (cid:127) Device Errata (cid:127) Job Postings (cid:127) Microchip Consultant Program Member Listing (cid:127) Links to other useful web sites related to Microchip Products (cid:127) Conferences for products, Development Systems, technical information and more (cid:127) Listing of seminars and events Preliminary  2003 Microchip Technology Inc. DS21673C-page 17

24AA515/24LC515/24FC515 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod- uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: Technical Publications Manager Total Pages Sent ________ RE: Reader Response From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y N Device: 24AA515/24LC515/24FC515 Literature Number: DS21673C Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? Preliminary DS21673C-page 18  2003 Microchip Technology Inc.

24AA515/24LC515/24FC515 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX Examples: Device Temperature Package a) 24AA515T-I/SM: Tape and Reel, Industrial Range Temperature, SOIC package. b) 24LC515-I/P: Industrial Temperature, PDIP package. Device 24AA515: = 512K Bit 1.8V I2C CMOS Serial EEPROM c) 24LC515-I/SM: Industrial Temperature, 24AA515T: = 512K Bit 1.8V I2C CMOS Serial EEPROM SOIC package. (Tape and Reel) 24LC515: = 512K Bit 2.5V I2C CMOS Serial EEPROM d) 24LC515T-I/SM: Tape and Reel, Industrial 24LC515T: = 512K Bit 2.5V I2C CMOS Serial EEPROM Temperature, SOIC package. (Tape and Reel) 24FC515: = 512K Bit 2.5V I2C CMOS Serial EEPROM 24FC515T: = 512K Bit 2.5V I2C CMOS Serial EEPROM (Tape and Reel) Temperature Range I = -40°C to +85°C Package P = Plastic DIP (300 mil Body), 8-lead SM = Plastic SOIC (208 mil Body), 8-lead SALES AND SUPPORT Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom- mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. Your local Microchip sales office 2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277 3. The Microchip Worldwide Site (www.microchip.com) Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products. Preliminary  2003 Microchip Technology Inc. DS21673C-page 19

24AA515/24LC515/24FC515 NOTES: Preliminary DS21673C-page 20  2003 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices: (cid:127) Microchip products meet the specification contained in their particular Microchip Data Sheet. (cid:127) Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. (cid:127) There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. (cid:127) Microchip is willing to work with the customer who is concerned about the integrity of their code. (cid:127) Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is intended through suggestion only The Microchip name and logo, the Microchip logo, Accuron, and may be superseded by updates. It is your responsibility to dsPIC, KEELOQ, MPLAB, PIC, PICmicro, PICSTART, ensure that your application meets with your specifications. PRO MATE and PowerSmart are registered trademarks of No representation or warranty is given and no liability is Microchip Technology Incorporated in the U.S.A. and other assumed by Microchip Technology Incorporated with respect countries. to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such AmpLab, FilterLab, microID, MXDEV, MXLAB, PICMASTER, use or otherwise. Use of Microchip’s products as critical com- SEEVAL and The Embedded Control Solutions Company are ponents in life support systems is not authorized except with registered trademarks of Microchip Technology Incorporated express written approval by Microchip. No licenses are con- in the U.S.A. veyed, implicitly or otherwise, under any intellectual property Application Maestro, dsPICDEM, dsPICDEM.net, ECAN, rights. ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, microPort, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPIC, Select Mode, SmartSensor, SmartShunt, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. Serialized Quick Turn Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2003, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999 and Mountain View, California in March 2002. The Company’s quality system processes and procedures are QS-9000 compliant for its PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, non-volatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001 certified. Preliminary  2003 Microchip Technology Inc. DS21673C-page 21

WORLDWIDE SALES AND SERVICE AMERICAS ASIA/PACIFIC Korea Corporate Office Australia 168-1, Youngbo Bldg. 3 Floor Samsung-Dong, Kangnam-Ku 2355 West Chandler Blvd. Suite 22, 41 Rawson Street Seoul, Korea 135-882 Chandler, AZ 85224-6199 Epping 2121, NSW Tel: 82-2-554-7200 Fax: 82-2-558-5932 or Tel: 480-792-7200 Australia 82-2-558-5934 Fax: 480-792-7277 Tel: 61-2-9868-6733 Singapore Technical Support: 480-792-7627 Fax: 61-2-9868-6755 Web Address: http://www.microchip.com China - Beijing 200 Middle Road #07-02 Prime Centre Atlanta Unit 915 Singapore, 188980 3780 Mansell Road, Suite 130 Bei Hai Wan Tai Bldg. Tel: 65-6334-8870 Fax: 65-6334-8850 Alpharetta, GA 30022 No. 6 Chaoyangmen Beidajie Taiwan Tel: 770-640-0034 Beijing, 100027, No. China Fax: 770-640-0307 Tel: 86-10-85282100 Kaohsiung Branch Fax: 86-10-85282104 30F - 1 No. 8 Boston China - Chengdu Min Chuan 2nd Road 2 Lan Drive, Suite 120 Kaohsiung 806, Taiwan Rm. 2401-2402, 24th Floor, Westford, MA 01886 Tel: 886-7-536-4818 Tel: 978-692-3848 Ming Xing Financial Tower Fax: 886-7-536-4803 No. 88 TIDU Street Fax: 978-692-3821 Taiwan Chengdu 610016, China Chicago Tel: 86-28-86766200 Taiwan Branch 333 Pierce Road, Suite 180 Fax: 86-28-86766599 11F-3, No. 207 Itasca, IL 60143 China - Fuzhou Tung Hua North Road Tel: 630-285-0071 Taipei, 105, Taiwan Fax: 630-285-0075 Unit 28F, World Trade Plaza Tel: 886-2-2717-7175 Fax: 886-2-2545-0139 No. 71 Wusi Road Dallas Fuzhou 350001, China EUROPE 4570 Westgrove Drive, Suite 160 Tel: 86-591-7503506 Austria Addison, TX 75001 Fax: 86-591-7503521 Tel: 972-818-7423 China - Hong Kong SAR Durisolstrasse 2 Fax: 972-818-2924 Unit 901-6, Tower 2, Metroplaza AA-u4s6tr0ia0 Wels Detroit 223 Hing Fong Road Tel: 43-7242-2244-399 Tri-Atria Office Building Kwai Fong, N.T., Hong Kong Fax: 43-7242-2244-393 32255 Northwestern Highway, Suite 190 Tel: 852-2401-1200 Denmark Farmington Hills, MI 48334 Fax: 852-2401-3431 Regus Business Centre Tel: 248-538-2250 China - Shanghai Lautrup hoj 1-3 Fax: 248-538-2260 Room 701, Bldg. B Ballerup DK-2750 Denmark Kokomo Far East International Plaza Tel: 45-4420-9895 Fax: 45-4420-9910 2767 S. Albright Road No. 317 Xian Xia Road France Kokomo, IN 46902 Shanghai, 200051 Parc d’Activite du Moulin de Massy Tel: 765-864-8360 Tel: 86-21-6275-5700 43 Rue du Saule Trapu Fax: 765-864-8387 Fax: 86-21-6275-5060 Batiment A - ler Etage Los Angeles China - Shenzhen 91300 Massy, France Rm. 1812, 18/F, Building A, United Plaza Tel: 33-1-69-53-63-20 18201 Von Karman, Suite 1090 No. 5022 Binhe Road, Futian District Fax: 33-1-69-30-90-79 Irvine, CA 92612 Shenzhen 518033, China Germany Tel: 949-263-1888 Tel: 86-755-82901380 Steinheilstrasse 10 Fax: 949-263-1338 Fax: 86-755-8295-1393 D-85737 Ismaning, Germany Phoenix China - Shunde Tel: 49-89-627-144-0 2355 West Chandler Blvd. Room 401, Hongjian Building Fax: 49-89-627-144-44 Chandler, AZ 85224-6199 No. 2 Fengxiangnan Road, Ronggui Town Italy Tel: 480-792-7966 Shunde City, Guangdong 528303, China Via Quasimodo, 12 Fax: 480-792-4338 Tel: 86-765-8395507 Fax: 86-765-8395571 20025 Legnano (MI) San Jose China - Qingdao Milan, Italy 2107 North First Street, Suite 590 Rm. B505A, Fullhope Plaza, Tel: 39-0331-742611 San Jose, CA 95131 No. 12 Hong Kong Central Rd. Fax: 39-0331-466781 Tel: 408-436-7950 Qingdao 266071, China Netherlands Fax: 408-436-7955 Tel: 86-532-5027355 Fax: 86-532-5027205 P. A. De Biesbosch 14 Toronto India NL-5152 SC Drunen, Netherlands 6285 Northam Drive, Suite 108 Divyasree Chambers Tel: 31-416-690399 Mississauga, Ontario L4V 1X5, Canada 1 Floor, Wing A (A3/A4) Fax: 31-416-690340 Tel: 905-673-0699 No. 11, O’Shaugnessey Road United Kingdom Fax: 905-673-6509 Bangalore, 560 025, India 505 Eskdale Road Tel: 91-80-2290061 Fax: 91-80-2290062 Winnersh Triangle Japan Wokingham Benex S-1 6F Berkshire, England RG41 5TU 3-18-20, Shinyokohama Tel: 44-118-921-5869 Kohoku-Ku, Yokohama-shi Fax: 44-118-921-5820 Kanagawa, 222-0033, Japan Tel: 81-45-471- 6166 Fax: 81-45-471-6122 07/28/03 Preliminary DS21673C-page 22  2003 Microchip Technology Inc.

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: M icrochip: 24AA515T-I/SM 24FC515-I/P 24LC515-I/P 24FC515-I/SM 24AA515-I/SM 24LC515-I/SM 24FC515T-I/SM 24LC515T-I/SM 24AA515-I/P