24AA32A/24LC32A 2 32K I C™ Serial EEPROM Device Selection Table Description The Microchip Technology Inc. 24AA32A/24LC32A Part VCC Max Clock Temp (24XX32A*) is a 32 Kbit Electrically Erasable PROM. Number Range Frequency Ranges The device is organized as four blocks of 8K x 8-bit 24AA32A 1.8-5.5 400kHz(1) I memory with a 2-wire serial interface. Low-voltage 24LC32A 2.5-5.5 400kHz I, E design permits operation down to 1.8V, with standby and active currents of only 1µA and 1mA, Note 1: 100kHz for VCC <2.5V respectively. It has been developed for advanced, low- power applications such as personal communications Features or data acquisition. The 24XX32A also has a page write capability for up to 32 bytes of data. Functional address • Single supply with operation down to 1.8V lines allow up to eight devices on the same bus, for up (cid:127) Low-power CMOS technology to 256Kbits address space. The 24XX32A is available - 1mA active current typical in the standard 8-pin PDIP, surface mount SOIC, - 1µA standby current (max.) (I-temp) TSSOP and MSOP packages. (cid:127) Organized as 4 blocks of 8K bits (32K bit) (cid:127) 2-wire serial interface bus, I 2C™ compatible Package Types (cid:127) Cascadable for up to eight devices PDIP/SOIC/TSSOP/MSOP ROTATED TSSOP (cid:127) Schmitt Trigger inputs for noise suppression (24AA32AX/24LC32AX) (cid:127) Output slope control to eliminate ground bounce A0 1 8 Vcc 2 WP 1 2 8 SCL (cid:127) 100kHz (<2.5V) and 400kHz ( ≥2.5V) A1 2 4X 7 WP Vcc 2 4X 7 SDA compatibility A2 3 X 6 SCL A0 3 X3 6 Vss (cid:127) Self-timed write cycle (including auto-erase) Vss 4 32 5 SDA A1 4 2X 5 A2 (cid:127) Page write buffer for up to 32 bytes (cid:127) 2ms typical write cycle time for page write (cid:127) Hardware write-protect for entire memory Block Diagram (cid:127) Can be operated as a serial ROM (cid:127) Factory programming (QTP) available A0A1A2WP HV Generator (cid:127) ESD protection > 4,000V (cid:127) 1,000,000 erase/write cycles (cid:127) Data retention > 200 years I/O Memory EEPROM Control Control XDEC (cid:127) 8-lead PDIP, SOIC, TSSOP and MSOP packages Logic Logic Array (cid:127) Standard and Pb-free finishes available Page Latches (cid:127) Available temperature ranges: I/O - Industrial (I): -40°C to +85°C SCL YDEC - Automotive (E): -40°C to +125°C SDA Vcc VSS Sense Amp. R/W Control *24XX32A is used in this document as a generic part number for the 24AA32A/24LC32A devices.  2003 Microchip Technology Inc. DS21713D-page 1

24AA32A/24LC32A 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings (†) VCC.............................................................................................................................................................................6.5V All inputs and outputs w.r.t. VSS.........................................................................................................-0.3V to VCC +1.0V Storage temperature...............................................................................................................................-65°C to +150°C Ambient temperature with power applied................................................................................................-65°C to +125°C ESD protection on all pins......................................................................................................................................................≥ 4kV † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. TABLE 1-1: DC CHARACTERISTICS VCC = +1.8V to +5.5V DC CHARACTERISTICS Industrial (I): TA = -40°C to +85°C Automotive (E): TA = -40°C to +125°C Param. Symbol Characteristic Min Typ Max Units Conditions No. D1 VIH WP, SCL and SDA pins — — — — — D2 — High-level input voltage 0.7 VCC — — V — D3 VIL Low-level input voltage — — 0.3 VCC V — D4 VHYS Hysteresis of Schmitt 0.05 VCC — — V (Note 1) Trigger inputs D5 VOL Low-level output voltage — — 0.40 V IOL = 3.0mA, VCC = 2.5V D6 ILI Input leakage current — — ±1 µA VIN =.1V to VCC D7 ILO Output leakage current — — ±1 µA VOUT =.1V to VCC D8 CIN, Pin capacitance — — 10 pF VCC = 5.0V (Note 1) COUT (all inputs/outputs) TA = 25°C, FCLK = 1MHz D9 ICC write Operating current — 0.1 3 mA VCC = 5.5V, SCL = 400kHz D10 ICC read — 0.05 1 mA — D11 ICCS Standby current — 0.01 1 µA Industrial — — 5 µA Automotive SDA = SCL = VCC WP = VSS Note 1: This parameter is periodically sampled and not 100% tested. 2: Typical measurements taken at room temperature. DS21713D-page 2  2003 Microchip Technology Inc.

24AA32A/24LC32A TABLE 1-2: AC CHARACTERISTICS VCC = +1.8V to +5.5V AC CHARACTERISTICS Industrial (I): TA = -40°C to +85°C Automotive (E): TA = -40°C to +125°C Param. Symbol Characteristic Min Max Units Conditions No. 1 FCLK Clock frequency — 400 kHz 2.5V ≤ VCC ≤ 5.5V — 100 1.8V ≤ VCC < 2.5V (24AA32A) 2 THIGH Clock high time 600 — ns 2.5V ≤ VCC ≤ 5.5V 4000 — 1.8V ≤ VCC < 2.5V (24AA32A) 3 TLOW Clock low time 1300 — ns 2.5V ≤ VCC ≤ 5.5V 4700 — 1.8V ≤ VCC < 2.5V (24AA32A) 4 TR SDA and SCL rise time — 300 ns 2.5V ≤ VCC ≤ 5.5V (Note1) — 1000 1.8V ≤ VCC < 2.5V (24AA32A) 5 TF SDA and SCL fall time — 300 ns (Note1) 6 THD:STA Start condition hold time 600 — ns 2.5V ≤ VCC ≤ 5.5V 4000 — 1.8V ≤ VCC < 2.5V (24AA32A) 7 TSU:STA Start condition setup time 600 — ns 2.5V ≤ VCC ≤ 5.5V 4700 — 1.8V ≤ VCC < 2.5V (24AA32A) 8 THD:DAT Data input hold time 0 — ns (Note2) 9 TSU:DAT Data input setup time 100 — ns 2.5V ≤ VCC ≤ 5.5V 250 — 1.8V ≤ VCC < 2.5V (24AA32A) 10 TSU:STO Stop condition setup time 600 — ns 2.5V ≤ VCC ≤ 5.5V 4000 — 1.8V ≤ VCC < 2.5V (24AA32A) 11 TAA Output valid from clock — 900 ns 2.5V ≤ VCC ≤ 5.5V (Note2) — 3500 1.8V ≤ VCC < 2.5V (24AA32A) 12 TBUF Bus free time: Time the bus 1300 — ns 2.5V ≤ VCC ≤ 5.5V must be free before a new 4700 — 1.8V ≤ VCC < 2.5V (24AA32A) transmission can start 13 TOF Output fall time from VIH 20+0.1CB 250 ns 2.5V ≤ VCC ≤ 5.5V minimum to VIL maximum — 250 1.8V ≤ VCC < 2.5V (24AA32A) 14 TSP Input filter spike suppression — 50 ns (Notes1 and3) (SDA and SCL pins) 15 TWC Write cycle time (byte or — 5 ms — page) 16 — Endurance 1M — cycles 25°C, (Note4) Note 1: Not 100% tested. CB = total capacitance of one bus line in pF. 2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. 3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs which provide improved noise spike suppression. This eliminates the need for a TI specification for standard operation. 4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total Endurance™ Model which can be obtained on Microchip’s web site: www.microchip.com.  2003 Microchip Technology Inc. DS21713D-page 3

24AA32A/24LC32A FIGURE 1-1: BUS TIMING DATA 5 4 2 3 SCL 7 8 9 10 6 SDA IN 14 11 12 SDA OUT FIGURE 1-2: BUS TIMING START/STOP D4 SCL 6 7 10 SDA Start Stop DS21713D-page 4  2003 Microchip Technology Inc.

24AA32A/24LC32A 2.0 FUNCTIONAL DESCRIPTION 3.4 Data Valid (D) The 24XX32A supports a bidirectional, 2-wire bus and The state of the data line represents valid data when, data transmission protocol. A device that sends data after a Start condition, the data line is stable for the onto the bus is defined as transmitter, while a device duration of the high period of the clock signal. receiving data is defined as a receiver. The bus has to The data on the line must be changed during the low be controlled by a master device which generates the period of the clock signal. There is one clock pulse per serial clock (SCL), controls the bus access and gener- bit of data. ates the Start and Stop conditions, while the 24XX32A Each data transfer is initiated with a Start condition and works as slave. Both master and slave can operate as terminated with a Stop condition. The number of data transmitter or receiver, but the master device deter- bytes transferred between Start and Stop conditions is mines which mode is activated. determined by the master device and is, theoretically unlimited, (although only the last thirty two bytes will be 3.0 BUS CHARACTERISTICS stored when doing a write operation). When an over- write does occur it will replace data in a first-in first-out The following bus protocol has been defined: (FIFO) fashion. (cid:127) Data transfer may be initiated only when the bus is not busy. 3.5 Acknowledge (cid:127) During data transfer, the data line must remain stable whenever the clock line is high. Changes in Each receiving device, when addressed, is obliged to the data line while the clock line is high will be generate an acknowledge after the reception of each interpreted as a Start or Stop condition. byte. The master device must generate an extra clock pulse which is associated with this Acknowledge bit. Accordingly, the following bus conditions have been defined (Figure3-1). Note: The 24XX32A does not generate any Acknowledge bits if an internal 3.1 Bus not Busy (A) programming cycle is in progress. The device that acknowledges, has to pull down the Both data and clock lines remain high. SDA line during the Acknowledge clock pulse in such a way that the SDA line is stable low during the high 3.2 Start Data Transfer (B) period of the acknowledge related clock pulse. Of A high-to-low transition of the SDA line while the clock course, setup and hold times must be taken into (SCL) is high determines a Start condition. All com- account. During reads, a master must signal an end of mands must be preceded by a Start condition. data to the slave by not generating an Acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave (24XX32A) will leave the data 3.3 Stop Data Transfer (C) line high to enable the master to generate the Stop A low-to-high transition of the SDA line while the clock condition. (SCL) is high determines a Stop condition. All opera- tions must be ended with a Stop condition. FIGURE 3-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS (A) (B) (D) (D) (C) (A) SCL SDA START ADDRESS OR DATA STOP CONDITION ACKNOWLEDGE ALLOWED CONDITION VALID TO CHANGE  2003 Microchip Technology Inc. DS21713D-page 5

24AA32A/24LC32A 3.6 Device Addressing FIGURE 3-2: CONTROL BYTE FORMAT A control byte is the first byte received following the Read/Write Bit Start condition from the master device (Figure3-2). The control byte consists of a four-bit control code. For Chip Select the 24XX32A, this is set as ‘1010’ binary for read and Control Code Bits write operations. The next three bits of the control byte are the Chip Select bits (A2, A1, A0). The Chip Select S 1 0 1 0 A2 A1 A0 R/W ACK bits allow the use of up to eight 24XX32A devices on the same bus and are used to select which device is Slave Address accessed. The Chip Select bits in the control byte must correspond to the logic levels on the corresponding A2, Start Bit Acknowledge Bit A1, and A0 pins for the device to respond. These bits are in effect the three Most Significant bits of the word address. 3.7 Contiguous Addressing Across The last bit of the control byte defines the operation to Multiple Devices be performed. When set to a ‘1’, a read operation is selected. When set to a zero, a write operation is The Chip Select bits A2, A1, A0 can be used to expand selected. The next two bytes received define the the contiguous address space for up to 256K bits by address of the first data byte (Figure3-3). Because adding up to eight 24XX32A's on the same bus. In this only A11 to A0 are used, the upper four address bits are case, software can use A0 of the control byte as don’t care bits. The upper address bits are transferred address bit A12, A1 as address bit A13, and A2 as first, followed by the less significant bits. address bit A14. It is not possible to sequentially read across device boundaries. Following the Start condition, the 24XX32A monitors the SDA bus checking the device type identifier being transmitted and, upon receiving a ‘1010’ code and appropriate device select bits, the slave device outputs an Acknowledge signal on the SDA line. Depending on the state of the R/W bit, the 24XX32A will select a read or write operation. FIGURE 3-3: ADDRESS SEQUENCE BIT ASSIGNMENTS CONTROL BYTE ADDRESS HIGH BYTE ADDRESS LOW BYTE A A A A A A A A A 1 0 1 0 2 1 0 R/W X X X X 11 10 9 8 7 (cid:127) (cid:127) (cid:127) (cid:127) (cid:127) (cid:127) 0 CONTROL CHIP X = Don’t Care Bit CODE SELECT BITS DS21713D-page 6  2003 Microchip Technology Inc.

24AA32A/24LC32A 4.0 WRITE OPERATIONS 4.2 Page Write The write control byte, word address and the first data 4.1 Byte Write byte are transmitted to the 24XX32A in the same way as in a byte write. However, instead of generating a Following the Start condition from the master, the Stop condition, the master transmits up to 31 additional control code (4 bits), the Chip Select (3 bits), and the bytes which are temporarily stored in the on-chip page R/W bit (which is a logic low) are clocked onto the bus buffer and will be written into memory once the master by the master transmitter. This indicates to the has transmitted a Stop condition. Upon receipt of each addressed slave receiver that the address high byte word, the five lower-address pointer bits are internally will follow once it has generated an Acknowledge bit incremented by ‘1’. If the master should transmit more during the ninth clock cycle. Therefore, the next byte than 32 bytes prior to generating the Stop condition, the transmitted by the master is the high-order byte of the address counter will roll over and the previously word address and will be written into the address received data will be overwritten. As with the byte write pointer of the 24XX32A. The next byte is the Least operation, once the Stop condition is received, an Significant Address Byte. After receiving another internal write cycle will begin (Figure4-2). If an attempt Acknowledge signal from the 24XX32A, the master is made to write to the array with the WP pin held high, device will transmit the data word to be written into the the device will acknowledge the command but no write addressed memory location. The 24XX32A acknowl- cycle will occur, no data will be written and the device edges again and the master generates a Stop will immediately accept a new command. condition. This initiates the internal write cycle and, during this time, the 24XX32A will not generate Note: Page write operations are limited to writing Acknowledge signals (Figure4-1). If an attempt is bytes within a single physical page, made to write to the array with the WP pin held high, regardless of the number of bytes the device will acknowledge the command but no actually being written. Physical page write cycle will occur. No data will be written and the boundaries start at addresses that are device will immediately accept a new command. After integer multiples of the page buffer size (or a byte Write command, the internal address counter ‘page size’) and, end at addresses that are will point to the address location following the one that integer multiples of [page size - 1]. If a was just written. Page Write command attempts to write across a physical page boundary, the result is that the data wraps around to the beginning of the current page (overwriting data previously stored there), instead of being written to the next page as might be expected. It is therefore necessary for the application software to prevent page write operations that would attempt to cross a page boundary. 4.3 Write-Protection The WP pin allows the user to write-protect the entire array (0000-0FFFF) when the pin is tied to VCC. If tied to VSS or left floating, the write protection is disabled. The WP pin is sampled at the Stop bit for every write command (Figure3-1) Toggling the WP pin after the Stop bit will have no effect on the execution of the write cycle.  2003 Microchip Technology Inc. DS21713D-page 7

24AA32A/24LC32A FIGURE 4-1: BYTE WRITE S BUS ACTIVITY T S MASTER A CONTROL ADDRESS ADDRESS T R BYTE HIGH BYTE LOW BYTE DATA O T P SDA LINE S10 1 0A2A1A0 0 XXXX P A A A A BUS ACTIVITY C C C C K K K K X = don’t care bit FIGURE 4-2: PAGE WRITE S T S BUS ACTIVITY A CONTROL ADDRESS ADDRESS T MASTER R BYTE HIGH BYTE LOW BYTE DATA BYTE 0 DATA BYTE 31 O T P SDA LINE S10 10A2A1A00 XXXX P A A A A A BUS ACTIVITY C C C C C K K K K K X = don’t care bit DS21713D-page 8  2003 Microchip Technology Inc.

24AA32A/24LC32A 5.0 ACKNOWLEDGE POLLING FIGURE 5-1: ACKNOWLEDGE POLLING FLOW Since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). Once the Stop condition for a write command has been issued from the master, the device Send initiates the internally-timed write cycle. ACK polling Write Command can then be initiated immediately. This involves the master sending a Start condition followed by the control byte for a Write command (R/W = 0). If the device is still Send Stop Condition to busy with the write cycle, then no ACK will be returned. Initiate Write Cycle If no ACK is returned, the Start bit and control byte must be re-sent. If the cycle is complete, the device will return the ACK and the master can then proceed with the next Read or Write command. See Figure5-1 for Send Start flow diagram of this operation. Send Control Byte with R/W = 0 Did Device NO Acknowledge (ACK = 0)? YES Next Operation  2003 Microchip Technology Inc. DS21713D-page 9

24AA32A/24LC32A 6.0 READ OPERATION 6.3 Sequential Read Read operations are initiated in the same way as write Sequential reads are initiated in the same way as a operations, with the exception that the R/W bit of the random read, except that once the 24XX32A transmits control byte is set to ‘1’. There are three basic types of the first data byte, the master issues an acknowledge read operations: current address read, random read, as opposed to the Stop condition used in a random and sequential read. read. This acknowledge directs the 24XX32A to transmit the next sequentially addressed 8-bit word 6.1 Current Address Read (Figure6-3). Following the final byte transmitted to the master, the master will NOT generate an acknowledge The 24XX32A contains an address counter that main- but will generate a Stop condition. To provide sequen- tains the address of the last word accessed, internally tial reads, the 24XX32A contains an internal address incremented by ‘1’. Therefore, if the previous read pointer which is incremented by ‘1’ upon completion of access was to address n (n is any legal address), the each operation. This address pointer allows the entire next current address read operation would access data memory contents to be serially read during one from address n + 1. operation. The internal address pointer will automati- Upon receipt of the control byte with R/W bit set to ‘1’, cally roll over from address FFF to address 0000 if the the 24XX32A issues an acknowledge and transmits the master acknowledges the byte received from the array 8- bit data word. The master will not acknowledge the address 0FFF. transfer but does generate a Stop condition and the 24XX32A discontinues transmission (Figure6-1). 6.2 Random Read Random read operations allow the master to access any memory location in a random manner. To perform this type of read operation, the word address must first be first. This is accomplished by sending the word address to the 24XX32A as part of a write operation (R/W bit set to ‘0’). Once the word address is sent, the master generates a Start condition following the acknowledge. This terminates the write operation, but not before the internal address pointer is set. The master issues the control byte again, but with the R/W bit set to a ‘1’. The 24XX32A will then issue an acknowledge and transmit the 8-bit data word. The master will not acknowledge the transfer but does generate a Stop condition which causes the 24XX32A to discontinue transmission (Figure6-2). After a ran- dom Read command, the internal address counter will point to the address location following the one that was just read. FIGURE 6-1: CURRENT ADDRESS READ S BUS ACTIVITY T CONTROL S MASTER A BYTE DATA (n) T R O T P SDA LINE S P A N BUS ACTIVITY C O K A C K DS21713D-page 10  2003 Microchip Technology Inc.

24AA32A/24LC32A FIGURE 6-2: RANDOM READ S S BUS ACTIVITY T T S MASTER A CONTROL ADDRESS ADDRESS A CONTROL DATA T R BYTE HIGH BYTE LOW BYTE R BYTE BYTE O T T P SDA LINE S10 1 0AAA0 XXXX S1 01 0 AAA1 P 2 1 0 21 0 A A A A N BUS ACTIVITY C C C C O K K K K A X = Don’t Care Bit C K FIGURE 6-3: SEQUENTIAL READ S BUS ACTIVITY CONTROL T MASTER BYTE DATA n DATA n + 1 DATA n + 2 DATA n + X O P SDA LINE P A A A A N C C C C O BUS ACTIVITY K K K K A C K  2003 Microchip Technology Inc. DS21713D-page 11

24AA32A/24LC32A 7.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table7-1. TABLE 7-1: PIN FUNCTION TABLE ROTATED Name PDIP SOIC TSSOP MSOP Description TSSOP A0 1 1 1 1 3 Chip Address Input A1 2 2 2 2 4 Chip Address Input A2 3 3 3 3 5 Chip Address Input VSS 4 4 4 4 6 Ground SDA 5 5 5 5 7 Serial Address/Data I/O SCL 6 6 6 6 8 Serial Clock WP 7 7 7 7 1 Write-Protect Input VCC 8 8 8 8 2 +1.8V to 5.5V Power Supply 7.1 A0, A1, A2 Chip Address Inputs 7.3 Serial Clock (SCL) The A0, A1, A2 inputs are used by the 24XX32A for The SCL input is used to synchronize the data transfer multiple device operation. The levels on these inputs to and from the device. are compared with the corresponding bits in the slave address. The chip is selected if the compare is true. 7.4 Write-Protect (WP) Up to eight devices may be connected to the same bus The WP pin can be connected to either VSS, VCC or left by using different Chip Select bit combinations. These floating. An internal pull-down resistor on this pin will inputs must be connected to either VCC or VSS. keep the device in the unprotected state if left floating. If tied to VSS, or left floating, normal memory operation 7.2 Serial Data (SDA) is enabled (read/write the entire memory 000-FFF). SDA is a bidirectional pin used to transfer addresses If tied to VCC, write operations are inhibited. Read and data into and out of the device. It is an open-drain operations are not affected. terminal, therefore, the SDA bus requires a pull-up resistor to VCC (typical 10kΩ for 100kHz, 2kΩ for 400kHz) For normal data transfer, SDA is allowed to change only during SCL low. Changes during SCL high are reserved for indicating Start and Stop conditions. DS21713D-page 12  2003 Microchip Technology Inc.

24AA32A/24LC32A 8.0 PACKAGING INFORMATION 8.1 Package Marking Information 8-Lead PDIP (300 mil) Example: XXXXXXXX 24LC32A T/XXXNNN I/P13F YYWW 0327 8-Lead SOIC (150 mil) Example: XXXXXXXX 24LC32A T/XXYYWW I/SN0327 NNN 13F 8-Lead SOIC (208 mil) Example: XXXXXXXX 24LC32A T/XXXXXX I/SM YYWWNNN 032713F 8-Lead TSSOP Example: TSSOP Marking Codes Device XXXX 4LA STD Rot Pb-free Rot TYWW I327 24AA32A 4AA 4AAX G4AA G4AAX NNN 13F 24LC32A 4LA 4LAX G4LA G4LAX 8-Lead MSOP Example: MSOP Marking Codes XXXXXT 4L32AI Device YWWNNN 32713F STD Pb-free 24AA32A 4A32 G4AA 24LC32A 4L32A G4LA Note: Pb-free part number using “G” suffix is marked on carton Legend: XX...X Customer specific information* T Temperature grade (I, E) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. *Standard QTP marking consists of Microchip part number, year code, week code, and traceability code.  2003 Microchip Technology Inc. DS21713D-page 13

24AA32A/24LC32A 8-Lead Plastic Dual In-line (P) – 300 mil (PDIP) E1 D 2 n 1 α E A A2 L c A1 β B1 p eB B Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 8 8 Pitch p .100 2.54 Top to Seating Plane A .140 .155 .170 3.56 3.94 4.32 Molded Package Thickness A2 .115 .130 .145 2.92 3.30 3.68 Base to Seating Plane A1 .015 0.38 Shoulder to Shoulder Width E .300 .313 .325 7.62 7.94 8.26 Molded Package Width E1 .240 .250 .260 6.10 6.35 6.60 Overall Length D .360 .373 .385 9.14 9.46 9.78 Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43 Lead Thickness c .008 .012 .015 0.20 0.29 0.38 Upper Lead Width B1 .045 .058 .070 1.14 1.46 1.78 Lower Lead Width B .014 .018 .022 0.36 0.46 0.56 Overall Row Spacing § eB .310 .370 .430 7.87 9.40 10.92 Mold Draft Angle Top α 5 10 15 5 10 15 Mold Draft Angle Bottom β 5 10 15 5 10 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-018 DS21713D-page 14  2003 Microchip Technology Inc.

24AA32A/24LC32A 8-Lead Plastic Small Outline (SN) –Narrow, 150 mil (SOIC) E E1 p D 2 B n 1 h α 45° c A A2 φ β L A1 Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 8 8 Pitch p .050 1.27 Overall Height A .053 .061 .069 1.35 1.55 1.75 Molded Package Thickness A2 .052 .056 .061 1.32 1.42 1.55 Standoff § A1 .004 .007 .010 0.10 0.18 0.25 Overall Width E .228 .237 .244 5.79 6.02 6.20 Molded Package Width E1 .146 .154 .157 3.71 3.91 3.99 Overall Length D .189 .193 .197 4.80 4.90 5.00 Chamfer Distance h .010 .015 .020 0.25 0.38 0.51 Foot Length L .019 .025 .030 0.48 0.62 0.76 Foot Angle φ 0 4 8 0 4 8 Lead Thickness c .008 .009 .010 0.20 0.23 0.25 Lead Width B .013 .017 .020 0.33 0.42 0.51 Mold Draft Angle Top α 0 12 15 0 12 15 Mold Draft Angle Bottom β 0 12 15 0 12 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-057  2003 Microchip Technology Inc. DS21713D-page 15

24AA32A/24LC32A 8-Lead Plastic Small Outline (SM) – Medium, 208 mil (SOIC) E E1 p D 2 n 1 B α c A A2 φ A1 β L Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 8 8 Pitch p .050 1.27 Overall Height A .070 .075 .080 1.78 1.97 2.03 Molded Package Thickness A2 .069 .074 .078 1.75 1.88 1.98 Standoff § A1 .002 .005 .010 0.05 0.13 0.25 Overall Width E .300 .313 .325 7.62 7.95 8.26 Molded Package Width E1 .201 .208 .212 5.11 5.28 5.38 Overall Length D .202 .205 .210 5.13 5.21 5.33 Foot Length L .020 .025 .030 0.51 0.64 0.76 Foot Angle φ 0 4 8 0 4 8 Lead Thickness c .008 .009 .010 0.20 0.23 0.25 Lead Width B .014 .017 .020 0.36 0.43 0.51 Mold Draft Angle Top α 0 12 15 0 12 15 Mold Draft Angle Bottom β 0 12 15 0 12 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. Drawing No. C04-056 DS21713D-page 16  2003 Microchip Technology Inc.

24AA32A/24LC32A 8-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP) E E1 p D 2 1 n B α A c φ A1 A2 β L Units INCHES MILLIMETERS* Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 8 8 Pitch p .026 0.65 Overall Height A .043 1.10 Molded Package Thickness A2 .033 .035 .037 0.85 0.90 0.95 Standoff § A1 .002 .004 .006 0.05 0.10 0.15 Overall Width E .246 .251 .256 6.25 6.38 6.50 Molded Package Width E1 .169 .173 .177 4.30 4.40 4.50 Molded Package Length D .114 .118 .122 2.90 3.00 3.10 Foot Length L .020 .024 .028 0.50 0.60 0.70 Foot Angle φ 0 4 8 0 4 8 Lead Thickness c .004 .006 .008 0.09 0.15 0.20 Lead Width B .007 .010 .012 0.19 0.25 0.30 Mold Draft Angle Top α 0 5 10 0 5 10 Mold Draft Angle Bottom β 0 5 10 0 5 10 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005” (0.127mm) per side. JEDEC Equivalent: MO-153 Drawing No. C04-086  2003 Microchip Technology Inc. DS21713D-page 17

24AA32A/24LC32A 8-Lead Plastic Micro Small Outline Package (MS) (MSOP) E E1 p D 2 B n 1 α A A2 c φ A1 (F) L β Units INCHES MILLIMETERS* Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 8 8 Pitch p .026 BSC 0.65 BSC Overall Height A - - .043 - - 1.10 Molded Package Thickness A2 .030 .033 .037 0.75 0.85 0.95 Standoff A1 .000 - .006 0.00 - 0.15 Overall Width E .193 TYP. 4.90 BSC Molded Package Width E1 .118 BSC 3.00 BSC Overall Length D .118 BSC 3.00 BSC Foot Length L .016 .024 .031 0.40 0.60 0.80 Footprint (Reference) F .037 REF 0.95 REF Foot Angle φ 0° - 8° 0° - 8° Lead Thickness c .003 .006 .009 0.08 - 0.23 Lead Width B .009 .012 .016 0.22 - 0.40 Mold Draft Angle Top α 5° - 15° 5° - 15° Mold Draft Angle Bottom β 5° - 15° 5° - 15° *Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MO-187 Drawing No. C04-111 DS21713D-page 18  2003 Microchip Technology Inc.

24AA32A/24LC32A APPENDIX A: REVISION HISTORY Revision D Corrections to Section 1.0, Electrical Characteristics.  2003 Microchip Technology Inc. DS21713D-page 19

24AA32A/24LC32A NOTES: DS21713D-page 20  2003 Microchip Technology Inc.

24AA32A/24LC32A ON-LINE SUPPORT SYSTEMS INFORMATION AND UPGRADE HOT LINE Microchip provides on-line support on the Microchip World Wide Web site. The Systems Information and Upgrade Line provides The web site is used by Microchip as a means to make system users a listing of the latest versions of all of files and information easily available to customers. To Microchip's development systems software products. view the site, the user must have access to the Internet Plus, this line provides information on how customers and a web browser, such as Netscape® or Microsoft® can receive the most current upgrade kits. The Hot Line Internet Explorer. Files are also available for FTP Numbers are: download from our FTP site. 1-800-755-2345 for U.S. and most of Canada, and 1-480-792-7302 for the rest of the world. Connecting to the Microchip Internet Web Site 042003 The Microchip web site is available at the following URL: www.microchip.com The file transfer site is available by using an FTP service to connect to: ftp://ftp.microchip.com The web site and file transfer site provide a variety of services. Users may download files for the latest Development Tools, Data Sheets, Application Notes, User's Guides, Articles and Sample Programs. A vari- ety of Microchip specific business information is also available, including listings of Microchip sales offices, distributors and factory representatives. Other data available for consideration is: (cid:127) Latest Microchip Press Releases (cid:127) Technical Support Section with Frequently Asked Questions (cid:127) Design Tips (cid:127) Device Errata (cid:127) Job Postings (cid:127) Microchip Consultant Program Member Listing (cid:127) Links to other useful web sites related to Microchip Products (cid:127) Conferences for products, Development Systems, technical information and more (cid:127) Listing of seminars and events  2003 Microchip Technology Inc. DS21713D-page 21

24AA32A/24LC32A READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod- uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: Technical Publications Manager Total Pages Sent ________ RE: Reader Response From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y N Device: 24AA32A/24LC32A Literature Number: DS21713D Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS21713D-page 22  2003 Microchip Technology Inc.

24AA32A/24LC32A PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX X Examples: a) 24AA32A-I/P: Industrial Temperature,1.8V, Device Temperature Package Lead Finish PDIP package Range b) 24AA32A-I/SN: Industrial Temperature,1.8V, SOIC package Device: 24AA32A: 1.8V, 32 Kbit I2C Serial EEPROM c) 24AA32A-I/SM: Industrial Temperature.,1.8V, 24AA32AT: 1.8V, 32 Kbit I2C Serial EEPROM SOIC (208 mil) package (Tape and Reel) 24AA32AX 1.8V, 32 Kbit I2C Serial EEPROM in d) 24AA32AX-I/ST: Industrial Temp.,1.8V, Rotated TSSOP package alternate pinout (ST only) 24AA32AXT1.8V, 32 Kbit I2C Serial EEPROM in e) 24AA32A-I/ST: Industrial Temperature.,1.8V, alternate pinout (ST only) TSSOP package 24LC32A: 2.5V, 32 Kbit I2C Serial EEPROM f) 24AA32A-I/PG: Industrial Temperature.,1.8V, 24LC32AT: 2.5V, 32 Kbit I2C Serial EEPROM PDIP package. Pb-free (Tape and Reel) 24LC32AX 2.5V, 32 Kbit I2C Serial EEPROM in alternate pinout (ST only) g) 24LC32A-I/P: Industrial Temperature, 2.5V, 24LC32AXT2.5V, 32 Kbit I2C Serial EEPROM in PDIP package alternate pinout (ST only) h) 24LC32A-E/SN: Automotive Temperature, 2.5V SOIC package Tempera- I = -40°C to +85°C i) 24LC32A-E/SM: Automotive Temperature, ture E = -40°C to +125°C 2.5V SOIC (208 mil) package Range: j) 24LC32AX-E/ST: Automotive Temperature, 2.5V, Rotated TSSOP package k) 24LC32AT-I/ST: Industrial Temperature, 2.5V, Package: P = Plastic DIP (300 mil body), 8-lead TSSOP package, Tape and Reel SN = Plastic SOIC (150 mil body), 8-lead SM = Plastic SOIC (208 mil body), 8-lead l) 24LC32AT-I/SNG: Industrial Temperature, ST = Plastic TSSOP (4.4 mm), 8-lead 2.5V, SOIC package, Tape and Reel, Pb-free MS = Plastic Micro Small Outline (MSOP), 8-lead Lead Finish Blank = Standard 63% / 37% SnPb G = Pb-free (Matte Tin - Pure Sn) Sales and Support Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. Your local Microchip sales office 2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277 3. The Microchip Worldwide Site (www.microchip.com) Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products.  2003 Microchip Technology Inc. DS21713D-page 23

24AA32A/24LC32A NOTES: DS21713D-page 24  2003 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices: (cid:127) Microchip products meet the specification contained in their particular Microchip Data Sheet. (cid:127) Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. (cid:127) There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. (cid:127) Microchip is willing to work with the customer who is concerned about the integrity of their code. (cid:127) Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is intended through suggestion only The Microchip name and logo, the Microchip logo, Accuron, and may be superseded by updates. It is your responsibility to dsPIC, KEELOQ, MPLAB, PIC, PICmicro, PICSTART, ensure that your application meets with your specifications. PRO MATE and PowerSmart are registered trademarks of No representation or warranty is given and no liability is Microchip Technology Incorporated in the U.S.A. and other assumed by Microchip Technology Incorporated with respect countries. to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such AmpLab, FilterLab, microID, MXDEV, MXLAB, PICMASTER, use or otherwise. Use of Microchip’s products as critical com- SEEVAL and The Embedded Control Solutions Company are ponents in life support systems is not authorized except with registered trademarks of Microchip Technology Incorporated express written approval by Microchip. No licenses are con- in the U.S.A. veyed, implicitly or otherwise, under any intellectual property Application Maestro, dsPICDEM, dsPICDEM.net, ECAN, rights. ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, microPort, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPIC, Select Mode, SmartSensor, SmartShunt, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. Serialized Quick Turn Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2003, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999 and Mountain View, California in March 2002. The Company’s quality system processes and procedures are QS-9000 compliant for its PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, non-volatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001 certified.  2003 Microchip Technology Inc. DS21713D-page 25

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Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: M icrochip: 24LC32AX-I/ST 24LC32A/SN 24AA32A-I/SM 24AA32A-I/MS 24AA32A-I/ST 24AA32A-I/SN 24LC32A-I/SMG 24LC32AXT/ST 24AA32AT-I/SMG 24LC32A-I/P 24LC32AT/SM 24LC32AT/SN 24LC32AX-E/ST 24AA32A-I/P 24LC32AT-I/SMG 24LC32AT-I/SNG 24LC32AT-E/MS 24LC32AT-E/SN 24LC32AT-E/ST 24LC32AT-E/SM 24LC32A/SM 24LC32AXT-E/ST 24AA32AT/SN 24AA32AT/SM 24LC32AX/ST 24LC32AT-I/SM 24LC32AT-I/ST 24LC32AT-I/SN 24AA32AT-I/MS 24AA32AT-I/ST 24AA32AT-I/SM 24AA32AT-I/SN 24AA32A-I/SMG 24LC32AXT- I/ST 24AA32A/SM 24LC32A-E/SM 24LC32A-E/MS 24LC32A-E/SN 24LC32A-E/ST 24LC32A/P 24LC32A-I/SN 24LC32A-I/MS 24LC32A-I/SM 24LC32A-I/ST 24LC32A-E/P