24AA08H/24LC08BH 2 8K I C™ Serial EEPROM with Half-Array Write-Protect Device Selection Table Description: Part VCC Max. Clock Temp. The Microchip Technology Inc. 24AA08H/24LC08BH Number Range Frequency Ranges (24XX08H*) is an 8 Kbit Electrically Erasable PROM. 24AA08H 1.7-5.5 400kHz(1) I The device is organized as four blocks of 256 x 8-bit memory with a 2-wire serial interface. Low-voltage 24LC08BH 2.5-5.5 400kHz I, E design permits operation down to 1.7V, with standby Note 1: 100kHz for VCC <2.5V and active currents of only 1A and 1mA, respectively. The 24XX08H also has a page write Features: capability for up to 16 bytes of data. The 24XX08H is available in the standard 8-pin PDIP, surface mount • Single Supply with Operation Down to 1.7V for SOIC, TSSOP, 2x3 TDFN and MSOP packages, and 24AA08H Devices, 2.5V for 24LC08BH Devices is also available in the 5-lead SOT-23 package. All • Low-Power CMOS Technology: packages are RoHS compliant. - Read current 1mA, max. Block Diagram - Standby current 1A, max. • 2-Wire Serial Interface, I2C™ Compatible HV WP Generator • Schmitt Trigger Inputs for Noise Suppression • Output Slope Control to eliminate Ground Bounce • 100kHz and 400kHz Clock Compatibility I/O Memory EEPROM • Page Write Time 3 ms, typical Control Control XDEC Array Logic Logic • Self-Timed Erase/Write Cycle Page • 16-Byte Page Write Buffer Latches • Hardware Write-Protect for Half-Array (200h-3FFh) I/O SCL • ESD Protection >4,000V YDEC • More than 1 Million Erase/Write Cycles SDA • Data Retention >200 years VCC Sense Amp. • Factory Programming available VSS R/W Control • Packages include 8-lead PDIP, SOIC, TSSOP, TDFN, MSOP and 5-lead SOT-23 Package Types • RoHS Compliant PDIP, MSOP SOIC, TSSOP • Temperature Ranges: - Industrial (I): -40°C to +85°C A0 1 8 VCC A0 1 8 VCC - Automotive (E): -40°C to +125°C A1 2 7 WP A1 2 7 WP A2 3 6 SCL A2 3 6 SCL VSS 4 5 SDA VSS 4 5 SDA SOT-23-5 TDFN SCL 1 5 WP A0 1 8 VCC A1 2 7 WP Vss 2 A2 3 6 SCL VSS 4 5 SDA SDA 3 4 Vcc Note: Pins A0, A1 and A2 are not used by the 24XX08. (No *24XX08H is used in this document as a generic part internal connections). number for the 24AA08H/24LC08BH devices.  2008-2013 Microchip Technology Inc. DS20002084B-page 1

24AA08H/24LC08BH 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings (†) VCC.............................................................................................................................................................................6.5V All inputs and outputs w.r.t. VSS.........................................................................................................-0.3V to VCC +1.0V Storage temperature...............................................................................................................................-65°C to +150°C Ambient temperature with power applied................................................................................................-40°C to +125°C ESD protection on all pins 4kV † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. TABLE 1-1: DC CHARACTERISTICS VCC = +1.7V to +5.5V DC CHARACTERISTICS Industrial (I): TA = -40°C to +85°C Automotive (E): TA = -40°C to +125°C Param. Symbol Characteristic Min. Typ. Max. Units Conditions No. — — WP, SCL and SDA pins — — — — — D1 VIH High-level input voltage 0.7 VCC — — V — D2 VIL Low-level input voltage — — 0.3 VCC V — D3 VHYS Hysteresis of Schmitt 0.05 VCC — — V (Note) Trigger inputs D4 VOL Low-level output voltage — — 0.40 V IOL = 3.0mA, VCC = 2.5V D5 ILI Input leakage current — — ±1 A VIN = VSS or VCC D6 ILO Output leakage current — — ±1 A VOUT = VSS or VCC D7 CIN, Pin capacitance — — 10 pF VCC = 5.0V (Note) COUT (all inputs/outputs) TA = 25°C, FCLK = 1MHz D8 ICC write Operating current — 0.1 3 mA VCC = 5.5V, SCL = 400kHz D9 ICC read — 0.05 1 mA — D10 ICCS Standby current — 0.01 1 A Industrial — — 5 A Automotive SDA = SCL = VCC WP = VSS Note: This parameter is periodically sampled and not 100% tested. DS20002084B-page 2  2008-2013 Microchip Technology Inc.

24AA08H/24LC08BH TABLE 1-2: AC CHARACTERISTICS Industrial (I): TA = -40°C to +85°C, VCC = +1.7V to +5.5V AC CHARACTERISTICS Automotive (E): TA = -40°C to +125°C, VCC = +2.5V to +5.5V Param. Symbol Characteristic Min. Max. Units Conditions No. 1 FCLK Clock Frequency — 400 kHz 2.5V  VCC  5.5V — 100 1.7V  VCC  2.5V (24AA08H) 2 THIGH Clock High Time 600 — ns 2.5V  VCC  5.5V 4000 — 1.7V  VCC  2.5V (24AA08H) 3 TLOW Clock Low Time 1300 — ns 2.5V  VCC  5.5V 4700 — 1.7V  VCC  2.5V (24AA08H) 4 TR SDA and SCL Rise Time — 300 ns 2.5V  VCC  5.5V (Note1) — 1000 1.7V  VCC  2.5V (24AA08H) 5 TF SDA and SCL Fall Time — 300 ns (Note1) 6 THD:STA Start Condition Hold Time 600 — ns 2.5V  VCC  5.5V 4000 — 1.7V  VCC  2.5V (24AA08H) 7 TSU:STA Start Condition Setup Time 600 — ns 2.5V  VCC  5.5V 4700 — 1.7V  VCC  2.5V (24AA08H) 8 THD:DAT Data Input Hold Time 0 — ns (Note2) 9 TSU:DAT Data Input Setup Time 100 — ns 2.5V  VCC  5.5V 250 — 1.7V  VCC  2.5V (24AA08H) 10 TSU:STO Stop Condition Setup Time 600 — ns 2.5V  VCC  5.5V 4000 — 1.7V  VCC  2.5V (24AA08H) 11 TSU:WP WP Setup Time 600 — ns 2.5V VCC  5.5V 4000 — 1.7V VCC < 2.5V (24AA08H) 12 THD:WP WP Hold Time 1300 — ns 2.5V VCC  5.5V 4700 — 1.7V VCC < 2.5V (24AA08H) 13 TAA Output Valid from Clock — 900 ns 2.5V  VCC  5.5V (Note2) — 3500 1.7V  VCC  2.5V (24AA08H) 14 TBUF Bus free time: Time the bus 1300 — ns 2.5V  VCC  5.5V must be free before a new 4700 — 1.7V  VCC  2.5V (24AA08H) transmission can start 15 TOF Output Fall Time from VIH — 250 ns 2.5V  VCC  5.5V Minimum to VIL Maximum — 250 1.7V  VCC  2.5V (24AA08H) 16 TSP Input Filter Spike Suppression — 50 ns (Notes1 and3) (SDA and SCL pins) 17 TWC Write Cycle Time (byte or — 5 ms — page) 18 — Endurance 1M — cycles 25°C, (Note4) Note 1: Not 100% tested. CB = total capacitance of one bus line in pF. 2: As a transmitter the device must provide an internal minimum delay time to bridge the undefined region (minimum 300ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. 3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs which provide improved noise spike suppression. This eliminates the need for a TI specification for standard operation. 4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total Endurance™ Model which can be obtained on Microchip’s web site at www.microchip.com.  2008-2013 Microchip Technology Inc. DS20002084B-page 3

24AA08H/24LC08BH FIGURE 1-1: BUS TIMING DATA 5 4 2 D3 SCL 7 3 8 9 10 SDA 6 IN 16 13 14 SDA OUT (protected) WP 11 12 (unprotected) DS20002084B-page 4  2008-2013 Microchip Technology Inc.

24AA08H/24LC08BH 2.0 FUNCTIONAL DESCRIPTION 3.4 Data Valid (D) The 24XX08H supports a bidirectional, 2-wire bus and The state of the data line represents valid data when, data transmission protocol. A device that sends data after a Start condition, the data line is stable for the onto the bus is defined as a transmitter, while a device duration of the high period of the clock signal. receiving data is defined as a receiver. The bus has to The data on the line must be changed during the low be controlled by a master device which generates the period of the clock signal. There is one clock pulse per Serial Clock (SCL), controls the bus access and bit of data. generates the Start and Stop conditions, while the Each data transfer is initiated with a Start condition and 24XX08H works as slave. Both master and slave can terminated with a Stop condition. The number of the operate as transmitter or receiver, but the master data bytes transferred between the Start and Stop device determines which mode is activated. conditions is determined by the master device and is theoretically unlimited, although only the last sixteen 3.0 BUS CHARACTERISTICS will be stored when doing a write operation. When an overwrite does occur it will replace data in a first-in first- The following bus protocol has been defined: out (FIFO) fashion. • Data transfer may be initiated only when the bus is not busy. 3.5 Acknowledge • During data transfer, the data line must remain stable whenever the clock line is high. Changes in Each receiving device, when addressed, is obliged to the data line while the clock line is high will be generate an acknowledge after the reception of each interpreted as a Start or Stop condition. byte. The master device must generate an extra clock pulse which is associated with this Acknowledge bit. Accordingly, the following bus conditions have been defined (Figure3-1). Note: The 24XX08H does not generate any Acknowledge bits if an internal program- 3.1 Bus Not Busy (A) ming cycle is in progress. The device that acknowledges, has to pull down the Both data and clock lines remain high. SDA line during the acknowledge clock pulse in such a way that the SDA line is stable low during the high 3.2 Start Data Transfer (B) period of the acknowledge related clock pulse. Of A high-to-low transition of the SDA line while the clock course, setup and hold times must be taken into (SCL) is high determines a Start condition. All account. During reads, a master must signal an end of commands must be preceded by a Start condition. data to the slave by not generating an Acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave (24XX08H) will leave the data 3.3 Stop Data Transfer (C) line high to enable the master to generate the Stop A low-to-high transition of the SDA line while the clock condition. (SCL) is high determines a Stop condition. All operations must be ended with a Stop condition. FIGURE 3-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS (A) (B) (D) (D) (C) (A) SCL SDA Start Address or Data Stop Condition Acknowledge Allowed Condition Valid to Change  2008-2013 Microchip Technology Inc. DS20002084B-page 5

24AA08H/24LC08BH 3.6 Device Addressing FIGURE 3-2: CONTROL BYTE ALLOCATION A control byte is the first byte received following the Start condition from the master device (Figure3-2). Read/Write Bit The control byte consists of a four-bit control code. For the 24XX08H, this is set as ‘1010’ binary for read and Block write operations. The next three bits of the control byte Select Control Code Bits are the block-select bits (B2, B1, B0). B2 is a “don’t care” for the 24XX08H. They are used by the master device to select which of the four 256 word-blocks of S 1 0 1 0 x B1 B0 R/W ACK memory are to be accessed. These bits are in effect the three Most Significant bits of the word address. Slave Address The last bit of the control byte defines the operation to be performed. When set to ‘1’ a read operation is selected. When set to ‘0’ a write operation is selected. Start Bit Acknowledge Bit Following the Start condition, the 24XX08H monitors the SDA bus, checking the device type identifier being x = “don’t care” transmitted and, upon receiving a ‘1010’ code, the slave device outputs an Acknowledge signal on the SDA line. Depending on the state of the R/W bit, the 24XX08H will select a read or write operation. Control Operation Block Select R/W Code Read 1010 Block Address 1 Write 1010 Block Address 0 DS20002084B-page 6  2008-2013 Microchip Technology Inc.

24AA08H/24LC08BH 4.0 WRITE OPERATION 4.2 Page Write The write control byte, word address and the first data 4.1 Byte Write byte are transmitted to the 24XX08H in the same way as in a byte write. However, instead of generating a Following the Start condition from the master, the Stop condition, the master transmits up to 16 data bytes device code (4 bits), the block address (3 bits) and the to the 24XX08H, which are temporarily stored in the on- R/W bit, which is a logic-low, is placed onto the bus by chip page buffer and will be written into memory once the master transmitter. This indicates to the addressed the master has transmitted a Stop condition. Upon slave receiver that a byte with a word address will receipt of each word, the four lower-order Address follow once it has generated an Acknowledge bit during Pointer bits are internally incremented by ‘1’. The the ninth clock cycle. Therefore, the next byte transmit- higher-order 7 bits of the word address remain ted by the master is the word address and will be constant. If the master should transmit more than 16 written into the Address Pointer of the 24XX08H. After words prior to generating the Stop condition, the receiving another Acknowledge signal from the address counter will roll over and the previously 24XX08H, the master device will transmit the data word received data will be overwritten. As with the byte write to be written into the addressed memory location. The operation, once the Stop condition is received an 24XX08H acknowledges again and the master internal write cycle will begin (Figure4-2). generates a Stop condition. This initiates the internal write cycle and, during this time, the 24XX08H will not Note: Page write operations are limited to writ- generate Acknowledge signals (Figure4-1). ing bytes within a single physical page, regardless of the number of bytes actually being written. Physical page boundaries start at addresses that are integer multiples of the page buffer size (or ‘page-size’) and end at addresses that are integer multiples of [page size – 1]. If a Page Write command attempts to write across a physical page boundary, the result is that the data wraps around to the beginning of the current page (overwriting data previously stored there), instead of being written to the next page, as might be expected. It is therefore necessary for the application software to prevent page write operations that would attempt to cross a page boundary. FIGURE 4-1: BYTE WRITE S S Bus Activity T Control Word T Master A Byte Address Data O R P T SDA Line S 1 0 1 0 X B1B0 0 P A A A Bus Activity Block C C C K K K Select x = “don’t care” Bits FIGURE 4-2: PAGE WRITE S S Bus Activity T Control Word T Master AR Byte Address (n) Data (n) Data (n + 1) Data (n + 15) OP T SDA Line S1 0 10 XB1B00 P A A A A A Bus Activity Block C C C C C K K K K K Select x = “don’t care” Bits  2008-2013 Microchip Technology Inc. DS20002084B-page 7

24AA08H/24LC08BH 5.0 ACKNOWLEDGE POLLING 6.0 WRITE PROTECTION Since the device will not acknowledge during a write The WP pin allows the user to write-protect half of the cycle, this can be used to determine when the cycle is array (200h-3FFh) when the pin is tied to VCC. If the pin complete (this feature can be used to maximize bus is tied to VSS the write protection is disabled. throughput). Once the Stop condition for a Write command has been issued from the master, the device initiates the internally-timed write cycle and ACK polling can then be initiated immediately. This involves the master sending a Start condition followed by the control byte for a Write command (R/W = 0). If the device is still busy with the write cycle, no ACK will be returned. If the cycle is complete, the device will return the ACK and the master can then proceed with the next Read or Write command. See Figure5-1 for a flow diagram of this operation. FIGURE 5-1: ACKNOWLEDGE POLLING FLOW Send Write Command Send Stop Condition to Initiate Write Cycle Send Start Send Control Byte with R/W = 0 Did Device No Acknowledge (ACK = 0)? Yes Next Operation DS20002084B-page 8  2008-2013 Microchip Technology Inc.

24AA08H/24LC08BH 7.0 READ OPERATION 7.3 Sequential Read Read operations are initiated in the same way as write Sequential reads are initiated in the same way as a operations, with the exception that the R/W bit of the random read, except that once the 24XX08H transmits slave address is set to ‘1’. There are three basic types the first data byte, the master issues an acknowledge of read operations: current address read, random read as opposed to a Stop condition in a random read. This and sequential read. directs the 24XX08H to transmit the next sequentially- addressed 8-bit word (Figure7-3). 7.1 Current Address Read To provide sequential reads, the 24XX08H contains an internal Address Pointer that is incremented by one The 24XX08H contains an address counter that main- upon completion of each operation. This Address tains the address of the last word accessed, internally Pointer allows the entire memory contents to be serially incremented by ‘1’. Therefore, if the previous access read during one operation. (either a read or write operation) was to address n, the next current address read operation would access data 7.4 Noise Protection from address n + 1. Upon receipt of the slave address with R/W bit set to ‘1’, the 24XX08H issues an acknowl- The 24XX08H employs a VCC threshold detector circuit edge and transmits the 8-bit data word. The master will which disables the internal erase/write logic if the VCC not acknowledge the transfer, but does generate a Stop is below 1.5V at nominal conditions. condition and the 24XX08H discontinues transmission The SCL and SDA inputs have Schmitt Trigger and (Figure7-1). filter circuits which suppress noise spikes to assure proper device operation, even on a noisy bus. 7.2 Random Read Random read operations allow the master to access any memory location in a random manner. To perform this type of read operation, the word address must first be set. This is accomplished by sending the word address to the 24XX08H as part of a write operation. Once the word address is sent, the master generates a Start condition following the acknowledge. This terminates the write operation, but not before the internal Address Pointer is set. The master then issues the control byte again, but with the R/W bit set to a ‘1’. The 24XX08H will then issue an acknowledge and transmit the 8-bit data word. The master will not acknowledge the transfer, but does generate a Stop condition and the 24XX08H will discontinue transmis- sion (Figure7-2). FIGURE 7-1: CURRENT ADDRESS READ S Bus Activity T Control S Master A Byte Data (n) T R O T P SDA Line S 1 0 1 0 x B1B0 1 P A N Bus Activity C o Block K Select A Bits C x = “don’t care” K  2008-2013 Microchip Technology Inc. DS20002084B-page 9

24AA08H/24LC08BH FIGURE 7-2: RANDOM READ S S Bus Activity T Control Word T Control S A A T Master R Byte Address (n) R Byte Data (n) O T T P S1010XB1B00 S1010XB1B01 P SDA Line A A A N Block C C Block C o Select K K Select K Bus Activity A Bits Bits C x = “don’t care” K FIGURE 7-3: SEQUENTIAL READ S Control Bus Activity T Master Byte Data (n) Data (n + 1) Data (n + 2) Data (n + X) O P 1 P SDA Line A A A A N C C C C o Bus Activity K K K K A C K DS20002084B-page 10  2008-2013 Microchip Technology Inc.

24AA08H/24LC08BH 8.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table8-1. TABLE 8-1: PIN FUNCTION TABLE Name PDIP SOIC TSSOP TDFN MSOP SOT-23 Description A0 1 1 1 1 1 — Not Connected A1 2 2 2 2 2 — Not Connected A2 3 3 3 3 3 — Not Connected VSS 4 4 4 4 4 2 Ground SDA 5 5 5 5 5 3 Serial Address/Data I/O SCL 6 6 6 6 6 1 Serial Clock WP 7 7 7 7 7 5 Write-Protect Input VCC 8 8 8 8 8 4 +1.7V to 5.5V Power Supply 8.1 Serial Address/Data Input/Output 8.3 Write-Protect (WP) (SDA) The WP pin must be connected to either VSS or VCC. SDA is a bidirectional pin used to transfer addresses If tied to VSS, normal memory operation is enabled and data into and out of the device. Since it is an open- (read/write the entire memory 000-03FF). drain terminal, the SDA bus requires a pull-up resistor If tied to VCC, write operations are inhibited, half of the to VCC (typical 10k for 100kHz, 2k for 400kHz). memory will be write-protected (200h-3FFh). Read For normal data transfer, SDA is allowed to change operations are not affected. only during SCL low. Changes during SCL high are reserved for indicating Start and Stop conditions. 8.4 A0, A1, A2 8.2 Serial Clock (SCL) The A0, A1 and A2 pins are not used by the 24XX08H. They may be left floating or tied to either VSS or VCC. The SCL input is used to synchronize the data transfer to and from the device.  2008-2013 Microchip Technology Inc. DS20002084B-page 11

24AA08H/24LC08BH 9.0 PACKAGING INFORMATION 9.1 Package Marking Information 8-Lead PDIP (300 mil) Example: XXXXXXXX 24LC08BH T/XXXNNN I/P e 3 13F YYWW 1345 8-Lead SOIC (3.90 mm) Example: 24LC08BHI XXXXXXXT SN e 3 1345 XXXXYYWW NNN 13F 8-Lead TSSOP Example: XXXX 4L8H TYWW I345 NNN 13F 8-Lead MSOP Example: XXXXXT 4L8BHI YWWNNN 34513F 5-Lead SOT-23 Example: XXNN 4QNN 8-Lead 2x3 TDFN Example: XXX AS5 YWW 345 NN 13 DS20002084B-page 12  2008-2013 Microchip Technology Inc.

24AA08H/24LC08BH 1st Line Marking Part No. SOT-23 TDFN PDIP SOIC TSSOP MSOP I-Temp E-Temp I-Temp E-Temp 24AA08H 24AA08H 24AA08HT 4A8H 4A8HT 4MNN — AS1 — 24LC08BH 24LC08BH 24L08BHT 4L8H 4L8BHT 4QNN 4RNN AS4 AS5 Note: T = Temperature grade (I,E) NN = Alphanumeric traceability code Legend: XX...X Part number or part number code T Temperature (I, E) Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code (2 characters for small packages) e3 JEDEC® designator for Matte Tin (Sn) Note: For very small packages with no room for the JEDEC designator e 3 , the marking will only appear on the outer carton or reel label. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. *Standard OTP marking consists of Microchip part number, year code, week code, and traceability code.  2008-2013 Microchip Technology Inc. DS20002084B-page 13

24AA08H/24LC08BH (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)(cid:15)(cid:16)(cid:6)(cid:10)(cid:8)(cid:17)(cid:18)(cid:3)(cid:4)(cid:13)(cid:18)(cid:5)(cid:8)(cid:19)(cid:9)(cid:20)(cid:8)(cid:21)(cid:8)(cid:22)(cid:23)(cid:23)(cid:8)(cid:24)(cid:13)(cid:10)(cid:8)(cid:25)(cid:26)(cid:7)(cid:27)(cid:8)(cid:28)(cid:9)(cid:15)(cid:17)(cid:9)(cid:29) (cid:30)(cid:26)(cid:12)(cid:5)(cid:31) 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) N NOTE1 E1 1 2 3 D E A A2 L A1 c e eB b1 b 6(cid:15)(cid:7)&! (cid:19)7,8.(cid:22) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:2)9(cid:7)’(cid:7)&! (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7"’)(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)(cid:31)(cid:7)(cid:15)! 7 < (cid:31)(cid:7)&(cid:8)(cid:11) (cid:14) (cid:20)(cid:30)(cid:4)(cid:4)(cid:2)1(cid:22), (cid:13)(cid:10)(cid:12)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)&(cid:7)(cid:15)(cid:17)(cid:2)(cid:31)(cid:16)(cid:28)(cid:15)(cid:14) (cid:25) = = (cid:20)(cid:3)(cid:30)(cid:4) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:25)(cid:3) (cid:20)(cid:30)(cid:30)(cid:29) (cid:20)(cid:30)-(cid:4) (cid:20)(cid:30)(cid:24)(cid:29) 1(cid:28)!(cid:14)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)&(cid:7)(cid:15)(cid:17)(cid:2)(cid:31)(cid:16)(cid:28)(cid:15)(cid:14) (cid:25)(cid:30) (cid:20)(cid:4)(cid:30)(cid:29) = = (cid:22)(cid:11)(cid:10)"(cid:16)#(cid:14)(cid:9)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:11)(cid:10)"(cid:16)#(cid:14)(cid:9)(cid:2)>(cid:7)#&(cid:11) . (cid:20)(cid:3)(cid:24)(cid:4) (cid:20)-(cid:30)(cid:4) (cid:20)-(cid:3)(cid:29) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)>(cid:7)#&(cid:11) .(cid:30) (cid:20)(cid:3)(cid:23)(cid:4) (cid:20)(cid:3)(cid:29)(cid:4) (cid:20)(cid:3)<(cid:4) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21) (cid:20)-(cid:23)< (cid:20)-?(cid:29) (cid:20)(cid:23)(cid:4)(cid:4) (cid:13)(cid:7)(cid:12)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)&(cid:7)(cid:15)(cid:17)(cid:2)(cid:31)(cid:16)(cid:28)(cid:15)(cid:14) 9 (cid:20)(cid:30)(cid:30)(cid:29) (cid:20)(cid:30)-(cid:4) (cid:20)(cid:30)(cid:29)(cid:4) 9(cid:14)(cid:28)#(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:8) (cid:20)(cid:4)(cid:4)< (cid:20)(cid:4)(cid:30)(cid:4) (cid:20)(cid:4)(cid:30)(cid:29) 6(cid:12)(cid:12)(cid:14)(cid:9)(cid:2)9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) )(cid:30) (cid:20)(cid:4)(cid:23)(cid:4) (cid:20)(cid:4)?(cid:4) (cid:20)(cid:4)(cid:5)(cid:4) 9(cid:10)*(cid:14)(cid:9)(cid:2)9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) ) (cid:20)(cid:4)(cid:30)(cid:23) (cid:20)(cid:4)(cid:30)< (cid:20)(cid:4)(cid:3)(cid:3) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)(cid:26)(cid:10)*(cid:2)(cid:22)(cid:12)(cid:28)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:2)+ (cid:14)1 = = (cid:20)(cid:23)-(cid:4) (cid:30)(cid:26)(cid:12)(cid:5)(cid:11)(cid:31) (cid:30)(cid:20) (cid:31)(cid:7)(cid:15)(cid:2)(cid:30)(cid:2) (cid:7)!"(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)#(cid:14)$(cid:2)%(cid:14)(cid:28)&"(cid:9)(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)((cid:2))"&(cid:2)’"!&(cid:2))(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)*(cid:7)&(cid:11)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)&(cid:8)(cid:11)(cid:14)#(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) +(cid:2)(cid:22)(cid:7)(cid:17)(cid:15)(cid:7)%(cid:7)(cid:8)(cid:28)(cid:15)&(cid:2),(cid:11)(cid:28)(cid:9)(cid:28)(cid:8)&(cid:14)(cid:9)(cid:7)!&(cid:7)(cid:8)(cid:20) -(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)!(cid:2)(cid:21)(cid:2)(cid:28)(cid:15)#(cid:2).(cid:30)(cid:2)#(cid:10)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)"#(cid:14)(cid:2)’(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:20)(cid:2)(cid:6)(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:2)!(cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:14)$(cid:8)(cid:14)(cid:14)#(cid:2)(cid:20)(cid:4)(cid:30)(cid:4)/(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)!(cid:7)#(cid:14)(cid:20) (cid:23)(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)#(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6).(cid:2)0(cid:30)(cid:23)(cid:20)(cid:29)(cid:6)(cid:20) 1(cid:22),2(cid:2)1(cid:28)!(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)&(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)$(cid:28)(cid:8)&(cid:2) (cid:28)(cid:16)"(cid:14)(cid:2)!(cid:11)(cid:10)*(cid:15)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)!(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17),(cid:4)(cid:23)(cid:27)(cid:4)(cid:30)<1 DS20002084B-page 14  2008-2013 Microchip Technology Inc.

24AA08H/24LC08BH Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2008-2013 Microchip Technology Inc. DS20002084B-page 15

24AA08H/24LC08BH Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS20002084B-page 16  2008-2013 Microchip Technology Inc.

24AA08H/24LC08BH (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8) (cid:24)(cid:6)(cid:10)(cid:10)(cid:8)!(cid:16)(cid:12)(cid:10)(cid:13)(cid:18)(cid:5)(cid:8)(cid:19) (cid:30)(cid:20)(cid:8)(cid:21)(cid:8)(cid:30)(cid:6)""(cid:26)#$(cid:8)(cid:22)%&(cid:23)(cid:8)(cid:24)(cid:24)(cid:8)(cid:25)(cid:26)(cid:7)(cid:27)(cid:8)(cid:28) !(cid:17)’(cid:29) (cid:30)(cid:26)(cid:12)(cid:5)(cid:31) 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)  2008-2013 Microchip Technology Inc. DS20002084B-page 17

24AA08H/24LC08BH (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)()(cid:13)(cid:18)(cid:8) )"(cid:13)(cid:18)*(cid:8) (cid:24)(cid:6)(cid:10)(cid:10)(cid:8)!(cid:16)(cid:12)(cid:10)(cid:13)(cid:18)(cid:5)(cid:8)(cid:19) ((cid:20)(cid:8)(cid:21)(cid:8)+%+(cid:8)(cid:24)(cid:24)(cid:8)(cid:25)(cid:26)(cid:7)(cid:27)(cid:8)(cid:28)( !(cid:9)(cid:29) (cid:30)(cid:26)(cid:12)(cid:5)(cid:31) 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) D N E E1 NOTE1 1 2 b e c φ A A2 A1 L1 L 6(cid:15)(cid:7)&! (cid:6)(cid:19)99(cid:19)(cid:6).(cid:13).(cid:26)(cid:22) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:2)9(cid:7)’(cid:7)&! (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7"’)(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)(cid:31)(cid:7)(cid:15)! 7 < (cid:31)(cid:7)&(cid:8)(cid:11) (cid:14) (cid:4)(cid:20)?(cid:29)(cid:2)1(cid:22), : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)8(cid:14)(cid:7)(cid:17)(cid:11)& (cid:25) = = (cid:30)(cid:20)(cid:3)(cid:4) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:25)(cid:3) (cid:4)(cid:20)<(cid:4) (cid:30)(cid:20)(cid:4)(cid:4) (cid:30)(cid:20)(cid:4)(cid:29) (cid:22)&(cid:28)(cid:15)#(cid:10)%%(cid:2) (cid:25)(cid:30) (cid:4)(cid:20)(cid:4)(cid:29) = (cid:4)(cid:20)(cid:30)(cid:29) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)>(cid:7)#&(cid:11) . ?(cid:20)(cid:23)(cid:4)(cid:2)1(cid:22), (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)>(cid:7)#&(cid:11) .(cid:30) (cid:23)(cid:20)-(cid:4) (cid:23)(cid:20)(cid:23)(cid:4) (cid:23)(cid:20)(cid:29)(cid:4) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21) (cid:3)(cid:20)(cid:24)(cid:4) -(cid:20)(cid:4)(cid:4) -(cid:20)(cid:30)(cid:4) 3(cid:10)(cid:10)&(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) 9 (cid:4)(cid:20)(cid:23)(cid:29) (cid:4)(cid:20)?(cid:4) (cid:4)(cid:20)(cid:5)(cid:29) 3(cid:10)(cid:10)&(cid:12)(cid:9)(cid:7)(cid:15)& 9(cid:30) (cid:30)(cid:20)(cid:4)(cid:4)(cid:2)(cid:26).3 3(cid:10)(cid:10)&(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14) (cid:3) (cid:4)R = <R 9(cid:14)(cid:28)#(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:8) (cid:4)(cid:20)(cid:4)(cid:24) = (cid:4)(cid:20)(cid:3)(cid:4) 9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) ) (cid:4)(cid:20)(cid:30)(cid:24) = (cid:4)(cid:20)-(cid:4) (cid:30)(cid:26)(cid:12)(cid:5)(cid:11)(cid:31) (cid:30)(cid:20) (cid:31)(cid:7)(cid:15)(cid:2)(cid:30)(cid:2) (cid:7)!"(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)#(cid:14)$(cid:2)%(cid:14)(cid:28)&"(cid:9)(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)((cid:2))"&(cid:2)’"!&(cid:2))(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)*(cid:7)&(cid:11)(cid:7)(cid:15)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)&(cid:8)(cid:11)(cid:14)#(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)!(cid:2)(cid:21)(cid:2)(cid:28)(cid:15)#(cid:2).(cid:30)(cid:2)#(cid:10)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)"#(cid:14)(cid:2)’(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:20)(cid:2)(cid:6)(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:2)!(cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:14)$(cid:8)(cid:14)(cid:14)#(cid:2)(cid:4)(cid:20)(cid:30)(cid:29)(cid:2)’’(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)!(cid:7)#(cid:14)(cid:20) -(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)#(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6).(cid:2)0(cid:30)(cid:23)(cid:20)(cid:29)(cid:6)(cid:20) 1(cid:22),2 1(cid:28)!(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)&(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)$(cid:28)(cid:8)&(cid:2) (cid:28)(cid:16)"(cid:14)(cid:2)!(cid:11)(cid:10)*(cid:15)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)!(cid:20) (cid:26).32 (cid:26)(cid:14)%(cid:14)(cid:9)(cid:14)(cid:15)(cid:8)(cid:14)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)((cid:2)"!"(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)((cid:2)%(cid:10)(cid:9)(cid:2)(cid:7)(cid:15)%(cid:10)(cid:9)’(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:12)"(cid:9)(cid:12)(cid:10)!(cid:14)!(cid:2)(cid:10)(cid:15)(cid:16)(cid:18)(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17),(cid:4)(cid:23)(cid:27)(cid:4)<?1 DS20002084B-page 18  2008-2013 Microchip Technology Inc.

24AA08H/24LC08BH Note: For the mostcurrent package drawings,please seetheMicrochip Packaging Specification located at http://www.microchip.com/packaging  2008-2013 Microchip Technology Inc. DS20002084B-page 19

24AA08H/24LC08BH Note: For the mostcurrent package drawings,please seetheMicrochip Packaging Specification located at http://www.microchip.com/packaging DS20002084B-page 20  2008-2013 Microchip Technology Inc.

24AA08H/24LC08BH Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2008-2013 Microchip Technology Inc. DS20002084B-page 21

24AA08H/24LC08BH ,(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8) (cid:24)(cid:6)(cid:10)(cid:10)(cid:8)!(cid:16)(cid:12)(cid:10)(cid:13)(cid:18)(cid:5)(cid:8)("(cid:6)(cid:18)(cid:11)(cid:13)(cid:11)(cid:12)(cid:26)"(cid:8)(cid:19)!((cid:20)(cid:8)(cid:28) !((cid:3)-(cid:22)(cid:29) (cid:30)(cid:26)(cid:12)(cid:5)(cid:31) 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) b N E E1 1 2 3 e e1 D A A2 c φ A1 L L1 6(cid:15)(cid:7)&! (cid:6)(cid:19)99(cid:19)(cid:6).(cid:13).(cid:26)(cid:22) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:2)9(cid:7)’(cid:7)&! (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7"’)(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)(cid:31)(cid:7)(cid:15)! 7 (cid:29) 9(cid:14)(cid:28)#(cid:2)(cid:31)(cid:7)&(cid:8)(cid:11) (cid:14) (cid:4)(cid:20)(cid:24)(cid:29)(cid:2)1(cid:22), :"&!(cid:7)#(cid:14)(cid:2)9(cid:14)(cid:28)#(cid:2)(cid:31)(cid:7)&(cid:8)(cid:11) (cid:14)(cid:30) (cid:30)(cid:20)(cid:24)(cid:4)(cid:2)1(cid:22), : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)8(cid:14)(cid:7)(cid:17)(cid:11)& (cid:25) (cid:4)(cid:20)(cid:24)(cid:4) = (cid:30)(cid:20)(cid:23)(cid:29) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:25)(cid:3) (cid:4)(cid:20)<(cid:24) = (cid:30)(cid:20)-(cid:4) (cid:22)&(cid:28)(cid:15)#(cid:10)%% (cid:25)(cid:30) (cid:4)(cid:20)(cid:4)(cid:4) = (cid:4)(cid:20)(cid:30)(cid:29) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)>(cid:7)#&(cid:11) . (cid:3)(cid:20)(cid:3)(cid:4) = -(cid:20)(cid:3)(cid:4) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)>(cid:7)#&(cid:11) .(cid:30) (cid:30)(cid:20)-(cid:4) = (cid:30)(cid:20)<(cid:4) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21) (cid:3)(cid:20)(cid:5)(cid:4) = -(cid:20)(cid:30)(cid:4) 3(cid:10)(cid:10)&(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) 9 (cid:4)(cid:20)(cid:30)(cid:4) = (cid:4)(cid:20)?(cid:4) 3(cid:10)(cid:10)&(cid:12)(cid:9)(cid:7)(cid:15)& 9(cid:30) (cid:4)(cid:20)-(cid:29) = (cid:4)(cid:20)<(cid:4) 3(cid:10)(cid:10)&(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14) (cid:3) (cid:4)R = -(cid:4)R 9(cid:14)(cid:28)#(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:8) (cid:4)(cid:20)(cid:4)< = (cid:4)(cid:20)(cid:3)? 9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) ) (cid:4)(cid:20)(cid:3)(cid:4) = (cid:4)(cid:20)(cid:29)(cid:30) (cid:30)(cid:26)(cid:12)(cid:5)(cid:11)(cid:31) (cid:30)(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)!(cid:2)(cid:21)(cid:2)(cid:28)(cid:15)#(cid:2).(cid:30)(cid:2)#(cid:10)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)"#(cid:14)(cid:2)’(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:20)(cid:2)(cid:6)(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:2)!(cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:14)$(cid:8)(cid:14)(cid:14)#(cid:2)(cid:4)(cid:20)(cid:30)(cid:3)(cid:5)(cid:2)’’(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)!(cid:7)#(cid:14)(cid:20) (cid:3)(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)#(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6).(cid:2)0(cid:30)(cid:23)(cid:20)(cid:29)(cid:6)(cid:20) 1(cid:22),2 1(cid:28)!(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)&(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)$(cid:28)(cid:8)&(cid:2) (cid:28)(cid:16)"(cid:14)(cid:2)!(cid:11)(cid:10)*(cid:15)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)!(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17),(cid:4)(cid:23)(cid:27)(cid:4)(cid:24)(cid:30)1 DS20002084B-page 22  2008-2013 Microchip Technology Inc.

24AA08H/24LC08BH Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2008-2013 Microchip Technology Inc. DS20002084B-page 23

24AA08H/24LC08BH Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS20002084B-page 24  2008-2013 Microchip Technology Inc.

24AA08H/24LC08BH (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)(cid:15)(cid:16)(cid:6)(cid:10)(cid:8).(cid:10)(cid:6)(cid:12)$(cid:8)(cid:30)(cid:26)(cid:8)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:6)(cid:14)*(cid:6)/(cid:5)(cid:8)(cid:19)0(cid:30)(cid:20)(cid:8)(cid:21)(cid:8)-1(cid:22)1(cid:23)%2,(cid:8)(cid:24)(cid:24)(cid:8)(cid:25)(cid:26)(cid:7)(cid:27)(cid:8)(cid:28)((cid:15).(cid:30)(cid:29) (cid:30)(cid:26)(cid:12)(cid:5)(cid:31) 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)  2008-2013 Microchip Technology Inc. DS20002084B-page 25

24AA08H/24LC08BH APPENDIX A: REVISION HISTORY Revision A(4/2008) Original release. Revision B (11/2013) Correcting typo in TDFN markings and other miscellaneous corrections. DS20002084B-page 26  2008-2013 Microchip Technology Inc.

24AA08H/24LC08BH THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at Users of Microchip products can receive assistance www.microchip.com. This web site is used as a means through several channels: to make files and information easily available to • Distributor or Representative customers. Accessible by using your favorite Internet • Local Sales Office browser, the web site contains the following • Field Application Engineer (FAE) information: • Technical Support • Product Support – Data sheets and errata, application notes and sample programs, design Customers should contact their distributor, resources, user’s guides and hardware support representative or Field Application Engineer (FAE) for documents, latest software releases and archived support. Local sales offices are also available to help software customers. A listing of sales offices and locations is included in the back of this document. • General Technical Support – Frequently Asked Questions (FAQ), technical support requests, Technical support is available through the web site online discussion groups, Microchip consultant at: http://microchip.com/support program member listing • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions.  2008-2013 Microchip Technology Inc. DS20002084B-page 27

24AA08H/24LC08BH NOTES: DS20002084B-page 28  2008-2013 Microchip Technology Inc.

24AA08H/24LC08BH PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX Examples: Device Temperature Package a) 24AA08H-I/P: Industrial Temperature,1.7V, Range PDIP package b) 24AA08H-I/SN: Industrial Tempera- ture,1.7V, SOIC package Device: 24AA08H: = 1.7V, 8 Kbit I2C Serial EEPROM 24AA08HT:= 1.7V, 8 Kbit I2C Serial EEPROM c) 24AA08HT-I/OT: Industrial Temperature, 1.7V, SOT-23 package, Tape and Reel (Tape and Reel) 24LC08BH:= 2.5V, 8 Kbit I2C Serial EEPROM d) 24LC08BH-I/P: Industrial Temperature, 24LC08BHT:= 2.5V, 8 Kbit I2C Serial EEPROM 2.5V, PDIP package (Tape and Reel) e) 24LC08BH-E/SN: Automotive Temp.,2.5V SOIC package f) 24LC08BHT-I/OT: Industrial Temperature, Temperature I = -40°C to +85°C 2.5V, SOT-23 package, Tape and Reel Range: E = -40°C to +125°C Package: P = Plastic DIP (300 mil body), 8-lead SN = Plastic SOIC (3.90 mm body), 8-lead ST = Plastic TSSOP (4.4 mm), 8-lead MNY(1)= Plastic Dual Flat (TDFN), No lead package, 2x3 mm body, 8-lead MS = Plastic Micro Small Outline (MSOP), 8-lead OT = SOT-23, 5-lead (Tape and Reel only) Note 1: “Y” indicates a Nickel Palladium Gold (NiPdAu) finish.  2008-2013 Microchip Technology Inc. DS20002084B-page 29

24AA08H/24LC08BH NOTES: DS20002084B-page 30  2008-2013 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC, and may be superseded by updates. It is your responsibility to FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, ensure that your application meets with your specifications. PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash MICROCHIP MAKES NO REPRESENTATIONS OR and UNI/O are registered trademarks of Microchip Technology WARRANTIES OF ANY KIND WHETHER EXPRESS OR Incorporated in the U.S.A. and other countries. IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, INCLUDING BUT NOT LIMITED TO ITS CONDITION, MTP, SEEVAL and The Embedded Control Solutions QUALITY, PERFORMANCE, MERCHANTABILITY OR Company are registered trademarks of Microchip Technology FITNESS FOR PURPOSE. Microchip disclaims all liability Incorporated in the U.S.A. arising from this information and its use. Use of Microchip Silicon Storage Technology is a registered trademark of devices in life support and/or safety applications is entirely at Microchip Technology Inc. in other countries. the buyer’s risk, and the buyer agrees to defend, indemnify and Analog-for-the-Digital Age, Application Maestro, BodyCom, hold harmless Microchip from any and all damages, claims, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, suits, or expenses resulting from such use. No licenses are dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, conveyed, implicitly or otherwise, under any Microchip ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial intellectual property rights. Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O, Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA and Z-Scale are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. GestIC and ULPP are registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2008-2013, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 9781620776803 QUALITY MANAGEMENT SYSTEM Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and CERTIFIED BY DNV Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures == ISO/TS 16949 == are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.  2008-2013 Microchip Technology Inc. DS20002084B-page 31

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Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: M icrochip: 24LC08BHT-I/MS 24LC08BH-E/MS 24AA08H-I/P 24AA08H-I/SN 24LC08BHT-E/ST 24LC08BH-I/SN 24LC08BHT- I/OT 24LC08BHT-I/SN 24LC08BH-E/ST 24AA08H-I/MS 24LC08BH-I/MS 24AA08HT-I/ST 24AA08HT-I/OT 24LC08BHT-E/MS 24LC08BHT-I/ST 24LC08BH-E/P 24LC08BH-I/P 24LC08BH-E/SN 24AA08HT-I/SN 24AA08H- I/ST 24LC08BH-I/ST 24AA08HT-I/MS 24LC08BHT-E/SN 24LC08BHT-E/OT