24AA024H/24LC024H 2 2K I C™ Serial EEPROM with Half-Array Write Protect Device Selection Table Description: Part VCC Max. Temp. The Microchip Technology Inc. 24AA024H/24LC024H is Number Range Clock Range a 2Kbit Serial Electrically Erasable PROM with operation down to 1.7V. The device is organized as a 24AA024H 1.7V-5.5V 400kHz(1) I single block of 256 x8-bit memory with a 2-wire serial 24LC024H 2.5V-5.5V 1 MHz I, E interface. Low-current design permits operation with maximum standby and active currents of only 1 μA and Note1: 100 kHz for VCC < 1.8V 400 μA, respectively. The device has a page write capabilityfor up to 16 bytes of data. Functional address Features: lines allow the connection of up to eight 24AA024H/ 24LC024H devices on the same bus for up to 16Kbits • Single-Supply with Operation Down to 1.7V of contiguous EEPROM memory. The device is • Low-Power CMOS Technology: availablein the standard 8-pin PDIP, 8-pin SOIC (150 - 400 μA active current, max. mil), TSSOP, 2x3 TDFN and MSOP packages. - 1 μA standby current, max. Block Diagram • Organized as a Single Block of 256 Bytes (256 x 8) A0 A1 A2 WP • 2-Wire Serial Interface Bus, I2C™ Compatible HV Generator • Schmitt Trigger Inputs for Noise Suppression I/O Memory • Output Slope Control to Eliminate Ground Bounce • 100 kHz and 400 kHz Compatibility C Loongtircol CLoongtircol XDEC E EAPrrRaOyM • 1 MHz Compatibility (LC) • Page Write Buffer for up to 16 Bytes SDA SCL • Self-Timed Write Cycle (including Auto-Erase) Write-Protect • Hardware Write Protection for Half Array VCC Circuitry (80h-FFh) YDEC VSS • Address Lines Allow up to Eight Devices on Bus • 1 Million Erase/Write Cycles Sense Amp. R/W Control • ESD Protection > 4,000V • Data Retention > 200 Years • Factory Programming (QTP) Available Package Types • 8-pin PDIP, SOIC, TSSOP, TDFN and MSOP Packages PDIP, MSOP SOIC, TSSOP • Available for Extended Temperature Ranges: A0 1 8 VCC A0 1 8 VCC - Industrial (I): -40°C to +85°C A1 2 7 WP A1 2 7 WP - Automotive (E): -40°C to +125°C A2 3 6 SCL A2 3 6 SCL • Pb-Free and RoHS compliant VSS 4 5 SDA VSS 4 5 SDA TDFN A0 1 8 VCC A1 2 7 WP A2 3 6 SCL VSS 4 5 SDA © 2008 Microchip Technology Inc. DS22102A-page 1

24AA024H/24LC024H 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings (†) VCC.............................................................................................................................................................................6.5V All inputs and outputs w.r.t. VSS.........................................................................................................-0.6V to VCC +1.0V Storage temperature...............................................................................................................................-65°C to +150°C Ambient temperature with power applied................................................................................................-40°C to +125°C ESD protection on all pins......................................................................................................................................................≥ 4 kV † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. TABLE 1-1: DC CHARACTERISTICS Electrical Characteristics: DC CHARACTERISTICS Industrial (I): VCC = +1.7V to 5.5V TA = -40°C to +85°C Automotive (E): VCC = +2.5V to 5.5V TA = -40°C to +125°C Param. Sym. Characteristic Min. Max. Units Conditions No. D1 — A0, A1, A2, SCL, SDA — — — — and WP pins: D2 VIH High-level input voltage 0.7 VCC — V — D3 VIL Low-level input voltage — 0.3 VCC V — D4 VHYS Hysteresis of Schmitt 0.05 VCC — V (Note) Trigger inputs (SDA, SCL pins) D5 VOL Low-level output voltage — 0.40 V IOL = 3.0ma @ VCC = 4.5V IOL = 2.1ma @ VCC = 2.5V D6 ILI Input leakage current — ±1 μA VIN = VSS or VCC, WP = VSS D7 ILO Output leakage current — ±1 μA VOUT = VSS or VCC D8 CIN, Pin capacitance — 10 pF VCC = 5.0V (Note) COUT (all inputs/outputs) TA = 25°C, f = 1MHz D9 ICC Read Operating current — 400 μA VCC = 5.5V, SCL = 400kHz ICC Write — 3 mA VCC = 5.5V D10 ICCS Standby current — 1 μA VCC = 5.5V, SCL = SDA = VCC WP = VSS, A0, A1, A2 = VSS Note: This parameter is periodically sampled and not 100% tested. DS22102A-page 2 © 2008 Microchip Technology Inc.

24AA024H/24LC024H TABLE 1-2: AC CHARACTERISTICS Electrical Characteristics: AC CHARACTERISTICS Industrial (I): VCC = +1.7V to 5.5V TA = -40°C to +85°C Automotive (E): VCC = +2.5V to 5.5V TA = -40°C to +125°C Param. Symbol Characteristic Min. Max. Units Conditions No. 1 FCLK Clock frequency — 100 kHz 1.7V ≤ VCC < 1.8V — 400 1.8V ≤ VCC ≤ 5.5V — 1000 2.5V ≤ VCC ≤ 5.5V (24LC024H) 2 THIGH Clock high time 4000 — ns 1.7V ≤ VCC < 1.8V 600 — 1.8V ≤ VCC ≤ 5.5V 500 — 2.5V ≤ VCC ≤ 5.5V (24LC024H) 3 TLOW Clock low time 4700 — ns 1.7V ≤ VCC < 1.8V 1300 — 1.8V ≤ VCC ≤ 5.5V 500 — 2.5V ≤ VCC ≤ 5.5V (24LC024H) 4 TR SDA and SCL rise time (Note1) — 1000 ns 1.7V ≤ VCC < 1.8V — 300 1.8V ≤ VCC ≤ 5.5V — 300 2.5V ≤ VCC ≤ 5.5V (24LC024H) 5 TF SDA and SCL fall time (Note1) — 1000 ns 1.7V ≤ VCC < 1.8V — 300 1.8V ≤ VCC ≤ 5.5V — 300 2.5V ≤ VCC ≤ 5.5V (24LC024H) 6 THD:STA Start condition hold time 4000 — ns 1.7V ≤ VCC < 1.8V 600 — 1.8V ≤ VCC ≤ 5.5V 250 — 2.5V ≤ VCC ≤ 5.5V (24LC024H) 7 TSU:STA Start condition setup time 4700 — ns 1.7V ≤ VCC < 1.8V 600 — 1.8V ≤ VCC ≤ 5.5V 250 — 2.5V ≤ VCC ≤ 5.5V (24LC024H) 8 THD:DAT Data input hold time 0 — ns (Note2) 9 TSU:DAT Data input setup time 250 — ns 1.7V ≤ VCC < 1.8V 100 — 1.8V ≤ VCC ≤ 5.5V 100 — 2.5V ≤ VCC ≤ 5.5V (24LC024H) 10 TSU:STO Stop condition setup time 4000 — ns 1.7V ≤ VCC < 1.8V 600 — 1.8V ≤ VCC ≤ 5.5V 250 — 2.5V ≤ VCC ≤ 5.5V (24LC024H) 11 TSU:WP WP setup time 4000 — ns 1.7V ≤ VCC < 1.8V 600 — 1.8V ≤ VCC ≤ 5.5V 600 — 2.5V ≤ VCC ≤ 5.5V (24LC024H) 12 THD:WP WP hold time 4700 — ns 1.7V ≤ VCC < 1.8V 600 — 1.8V ≤ VCC ≤ 5.5V 600 — 2.5V ≤ VCC ≤ 5.5V (24LC024H) 13 TAA Output valid from clock (Note2) — 3500 ns 1.7V ≤ VCC < 1.8V — 900 1.8V ≤ VCC ≤ 5.5V — 400 2.5V ≤ VCC ≤ 5.5V (24LC024H) 14 TBUF Bus free time: Time the bus must be 1300 — ns 1.7V ≤ VCC < 1.8V free before a new transmission can 4700 — 1.8V ≤ VCC ≤ 5.5V start 4700 — 2.5V ≤ VCC ≤ 5.5V (24LC024H) 16 TSP Input filter spike suppression — 50 ns 24AA024H (SDA and SCL pins) (Note1 and Note3) 17 TWC Write cycle time (byte or page) — 5 ms — 18 — Endurance 1M — cycles 25°C, VCC = 5.5V, Block mode (Note4) Note 1: Not 100% tested. CB = total capacitance of one bus line in pF. 2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. 3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs, which provide improved noise spike suppres- sion. This eliminates the need for a TI specification for standard operation. 4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total Endurance™ Model which can be obtained from Microchip’s web site at www.microchip.com. © 2008 Microchip Technology Inc. DS22102A-page 3

24AA024H/24LC024H FIGURE 1-1: BUS TIMING DATA 5 4 2 D4 SCL 7 3 8 9 10 SDA 6 In 16 13 14 SDA Out (protected) WP 11 12 (unprotected) DS22102A-page 4 © 2008 Microchip Technology Inc.

24AA024H/24LC024H 2.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table2-1. TABLE 2-1: PIN FUNCTION TABLE 8-pin 8-pin 8-pin 8-pin 8-pin Name Function PDIP SOIC TSSOP MSOP TDFN A0 1 1 1 1 1 User Configurable Chip Select A1 2 2 2 2 2 User Configurable Chip Select A2 3 3 3 3 3 User Configurable Chip Select VSS 4 4 4 4 4 Ground SDA 5 5 5 5 5 Serial Data SCL 6 6 6 6 6 Serial Clock WP 7 7 7 7 7 Write-Protect Input VCC 8 8 8 8 8 +1.7V to 5.5V (24AA024H) +2.5V to 5.5V (24LC024H) 2.1 SDA Serial Data 2.4 WP This is a bidirectional pin used to transfer addresses WP is the hardware write-protect pin. It must be tied to and data into and out of the device. It is an open drain VCC or VSS. If tied to VCC, the hardware write protection terminal. Therefore, the SDA bus requires a pull-up is enabled and will protect half of the array (80h-FFh). resistor to VCC (typical 10 kΩ for 100 kHz, 2 kΩ for If the WP pin is tied to VSS the hardware write 400kHz). protection is disabled. For normal data transfer, SDA is allowed to change 2.5 Noise Protection only during SCL low. Changes during SCL high are reserved for indicating the Start and Stop conditions. The 24AA024H/24LC024H employs a VCC threshold detector circuit that disables the internal erase/write 2.2 SCL Serial Clock logic if the VCC is below 1.5 volts at nominal conditions. The SCL input is used to synchronize the data transfer The SCL and SDA inputs have Schmitt Trigger and to and from the device. filter circuits that suppress noise spikes to assure proper device operation even on a noisy bus. 2.3 A0, A1, A2 The A0, A1 and A2 inputs are used by the 24AA024H/ 24LC024H for multiple device operations. The levels on these inputs are compared with the corresponding bits in the slave address. The chip is selected if the compare is true. Up to eight 24AA024H/24LC024H devices may be connected to the same bus by using different Chip Select bit combinations. These inputs must be connected to either VCC or VSS. In most applications, the chip address inputs A0, A1 and A2 are hard-wired to logic ‘0’ or logic ‘1’. For applications in which these pins are controlled by a microcontroller or other programmable device, the chip address pins must be driven to logic ‘0’ or logic ‘1’ before normal device operation can proceed. © 2008 Microchip Technology Inc. DS22102A-page 5

24AA024H/24LC024H 3.0 FUNCTIONAL DESCRIPTION The 24AA024H/24LC024H supports a bidirectional, 2-wire bus and data transmission protocol. A device that sends data onto the bus is defined as transmitter, and a device receiving data as receiver. The bus has to be controlled by a master device that generates the Serial Clock (SCL), controls the bus access and generates the Start and Stop conditions while the 24AA024H/24LC024H works as slave. Both master and slave can operate as transmitter or receiver, but the master device determines which mode is activated. DS22102A-page 6 © 2008 Microchip Technology Inc.

24AA024H/24LC024H 4.0 BUS CHARACTERISTICS The data on the line must be changed during the low period of the clock signal. There is one bit of data per The following bus protocol has been defined: clock pulse. • Data transfer may be initiated only when the bus Each data transfer is initiated with a Start condition and is not busy. terminated with a Stop condition. The number of the • During data transfer, the data line must remain data bytes transferred between the Start and Stop stable whenever the clock line is high. Changes in conditions is determined by the master device and is, the data line while the clock line is high will be theoretically, unlimited, though only the last sixteen will interpreted as a Start or Stop condition. be stored when doing a write operation. When an overwritedoes occur, it will replace data in a first-in Accordingly, the following bus conditions have been first-out fashion. defined (Figure4-1). 4.5 Acknowledge 4.1 Bus Not Busy (A) Each receiving device, when addressed, is required to Both data and clock lines remain high. generate an acknowledge after the reception of each byte. The master device must generate an extra clock 4.2 Start Data Transfer (B) pulse which is associated with this Acknowledge bit. A high-to-low transition of the SDA line while the clock Note: The 24AA024H/24LC024H does not gen- (SCL) is high determines a Start condition. All erate any Acknowledge bits if an internal commands must be preceded by a Start condition. programming cycle is in progress. The device that acknowledges has to pull down the 4.3 Stop Data Transfer (C) SDA line during the Acknowledge clock pulse in such a A low-to-high transition of the SDA line while the clock way that the SDA line is stable low during the high (SCL) is high determines a Stop condition. All period of the acknowledge-related clock pulse. Of operations must be ended with a Stop condition. course, setup and hold times must be taken into account. A master must signal an end of data to the 4.4 Data Valid (D) slave by not generating an Acknowledge bit on the last byte that has been clocked out of the slave. In this case, The state of the data line represents valid data when, the slave must leave the data line high to enable the after a Start condition, the data line is stable for the master to generate the Stop condition (Figure4-2). duration of the high period of the clock signal. FIGURE 4-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS CHARACTERISTICS (A) (B) (C) (D) (C) (A) SCL SDA Start Address or Data Stop Condition Acknowledge Allowed Condition Valid to Change FIGURE 4-2: ACKNOWLEDGE TIMING Acknowledge Bit SCL 1 2 3 4 5 6 7 8 9 1 2 3 SDA Data from transmitter Data from transmitter Transmitter must release the SDA line at this point allowing Receiver must release the SDA line at this the Receiver to pull the SDA line low to acknowledge the point so the Transmitter can continue previous eight bits of data. sending data. © 2008 Microchip Technology Inc. DS22102A-page 7

24AA024H/24LC024H 5.0 DEVICE ADDRESSING FIGURE 5-1: CONTROL BYTE FORMAT Read/Write Bit A control byte is the first byte received following the Start condition from the master device (Figure5-1). The control byte consists of a four-bit control code; for Chip Select Control Code Bits the 24AA024H/24LC024H this is set as ‘1010’ binary for read and write operations. The next three bits of the control byte are the Chip Select bits (A2, A1, A0). The S 1 0 1 0 A2 A1 A0 R/W ACK Chip Select bits allow the use of up to eight 24AA024H/ 24LC024H devices on the same bus and are used to Slave Address select which device is accessed. The Chip Select bits in the control byte must correspond to the logic levels Start Bit Acknowledge Bit on the corresponding A2, A1 and A0 pins for the device to respond. These bits are in effect the three Most 5.1 Contiguous Addressing Across Significant bits of the word address. Multiple Devices The last bit of the control byte defines the operation to be performed. When set to a ‘1’, a read operation is The Chip Select bits A2, A1 and A0 can be used to selected. When set to a ‘0’, a write operation is expand the contiguous address space for up to 16K bits selected. Following the Start condition, the 24AA024H/ by adding up to eight 24AA024H/24LC024H devices on 24LC024H monitors the SDA bus, checking the control the same bus. In this case, software can use A0 of the byte being transmitted. Upon receiving a ‘1010’ code control byte as address bit A9, A1 as address bit A10, and appropriate Chip Select bits, the slave device and A2 as address bit A11. It is not possible to outputsan Acknowledge signal on the SDA line. sequentially read across device boundaries. Dependingon the state of the R/W bit, the 24AA024H/ 24LC024H will select a read or write operation. DS22102A-page 8 © 2008 Microchip Technology Inc.

24AA024H/24LC024H 6.0 WRITE OPERATIONS The higher order four bits of the word address remain constant. If the master should transmit more than 16 bytes prior to generating the Stop condition, the 6.1 Byte Write address counter will roll over and the previously Following the Start signal from the master, the device received data will be overwritten. As with the byte write code (4 bits), the Chip Select bits (3 bits) and theR/W operation,once the Stop condition is received, an bit (which is a logic low) are placed onto the bus by the internalwrite cycle will begin (Figure6-2). If an attempt master transmitter. The device will acknowledge this is made to write to the protected portion of the array control byte during the ninth clock pulse. The next byte when the hardware write protection has been enabled, transmitted by the master is the word address and will the device will acknowledge the command, but no data be written into the Address Pointer of the 24AA024H/ will be written. The write cycle time must be observed 24LC024H. After receiving another Acknowledge even if write protection is enabled. signalfrom the 24AA024H/24LC024H, the master device will transmit the data word to be written into the Note: Page write operations are limited to writing addressed memory location. The 24AA024H/ bytes within a single physical page, 24LC024H acknowledges again and the master regardless of the number of bytes generatesa Stop condition. This initiates the internal actually being written. Physical page write cycle and the 24AA024H/24LC024H will not boundaries start at addresses that are generateAcknowledge signals during this time integer multiples of the page buffer size (or (Figure6-1). If an attempt is made to write to the ‘page size’) and end at addresses that are protectedportion of the array when the hardware write integer multiples of [page size – 1]. If a protection has been enabled, the device will Page Write command attempts to write acknowledgethe command, but no data will be written. across a physical page boundary, the The write cycle time must be observed even if write result is that the data wraps around to the protection is enabled. beginning of the current page (overwriting data previously stored there), instead of 6.2 Page Write being written to the next page, as might be expected. It is therefore necessary that the The write-control byte, word address and the first data application software prevent page write byte are transmitted to the 24AA024H/24LC024H in the operations that would attempt to cross a same way as in a byte write. But instead of generating page boundary. a Stop condition, the master transmits up to 15 additionaldata bytes to the 24AA024H/24LC024H that 6.3 Write Protection are temporarily stored in the on-chip page buffer and will be written into the memory once the master has The WP pin must be tied to VCC or VSS. If tied to VCC, half of the array will be write-protected (80h-FFh). If the transmitted a Stop condition. Upon receipt of each word, the four lower order Address Pointer bits are WP pin is tied to VSS, write operations to all address locations are allowed. internally incremented by one. FIGURE 6-1: BYTE WRITE S S T Bus Activity Control Word T Master AR Byte Address Data O P T SDA Line S P A A A Bus Activity C C C K K K FIGURE 6-2: PAGE WRITE S Bus Activity T S Master A Control Word T R Byte Address (n) Data (n) Data (n + 1) Data (n + 15) O T P SDA Line S P A A A A A Bus Activity C C C C C K K K K K © 2008 Microchip Technology Inc. DS22102A-page 9

24AA024H/24LC024H 7.0 ACKNOWLEDGE POLLING FIGURE 7-1: ACKNOWLEDGE POLLING FLOW Since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus Send throughput). Once the Stop condition for a write Write Command command has been issued from the master, the device initiates the internally-timed write cycle and ACK polling can be initiated immediately. This involves the master Send Stop sending a Start condition followed by the control byte Condition to for a Write command (R/W = 0). If the device is still Initiate Write Cycle busy with the write cycle, no ACK will be returned. If no ACK is returned, the Start bit and control byte must be re-sent. If the cycle is complete, the device will return Send Start the ACK and the master can then proceed with the next Read or Write command. See Figure7-1 for a flow diagram of this operation. Send Control Byte with R/W = 0 Did Device No Acknowledge (ACK = 0)? Yes Next Operation DS22102A-page 10 © 2008 Microchip Technology Inc.

24AA024H/24LC024H 8.0 READ OPERATIONS Once the word address is sent, the master generates a Start condition following the acknowledge. This Read operations are initiated in the same way as write terminates the write operation, but not before the operations, with the exception that the R/W bit of the internal Address Pointer is set. The master then issues slave address is set to ‘1’. There are three basic types the control byte again but with the R/W bit set to a ‘1’. of read operations: current address read, random read The 24AA024H/24LC024H will then issue an and sequential read. acknowledgeand transmits the eight-bit data word. The master will not acknowledge the transfer, but does 8.1 Current Address Read generate a Stop condition and the 24AA024H/ 24LC024H discontinues transmission (Figure8-2). The 24AA024H/24LC024H contains an address After this command, the internal address counter will counterthat maintains the address of the last word point to the address location following the one that was accessed, internally incremented by one. Therefore, if just read. the previous read access was to address n, the next current address read operation would access data from 8.3 Sequential Read address n + 1. Upon receipt of the slave address with the R/W bit set to ‘1’, the 24AA024H/24LC024H issues Sequential reads are initiated in the same way as a an acknowledge and transmits the 8-bit data word. The random read except that after the 24AA024H/ master will not acknowledge the transfer, but does 24LC024H transmits the first data byte, the master generate a Stop condition and the 24AA024H/ issues an acknowledge as opposed to a Stop condition 24LC024H discontinues transmission (Figure8-1). in a random read. This directs the 24AA024H/ 24LC024H to transmit the next sequentially addressed 8.2 Random Read 8-bit word (Figure8-3). Random read operations allow the master to access To provide sequential reads, the 24AA024H/24LC024H any memory location in a random manner. To perform contains an internal Address Pointer which is this type of read operation, the word address must first incremented by one at the completion of each be set. This is done by sending the word address to the operation.This Address Pointer allows the entire 24AA024H/24LC024H as part of a write operation. memorycontents to be serially read during one operation.The internal Address Pointer will automaticallyroll over from address FFh to address 00h. FIGURE 8-1: CURRENT ADDRESS READ S T S Bus Activity A Control T Master R Byte Data O T P SDA Line S P A N Bus Activity C O K A C K © 2008 Microchip Technology Inc. DS22102A-page 11

24AA024H/24LC024H FIGURE 8-2: RANDOM READ S S T T S Bus Activity A Control Word A Control T Master R Byte Address (n) R Byte Data (n) O T T P S S P SDA Line A A A N C C C O Bus Activity K K K A C K FIGURE 8-3: SEQUENTIAL READ S Bus Activity Control T Master Byte Data (n) Data (n + 1) Data (n + 2) Data (n + X) O P SDA Line P A A A A N C C C C O Bus Activity K K K K A C K DS22102A-page 12 © 2008 Microchip Technology Inc.

24AA024H/24LC024H 9.0 PACKAGING INFORMATION 9.1 Package Marking Information 8-Lead PDIP (300 mil) Example: XXXXXXXX 24LC024H T/XXXNNN I/P e 3 12F YYWW 0821 8-Lead SOIC (3.90 mm) Example: XXXXXXXT 24L024HI XXXXYYWW SN e 3 0821 NNN 12F 8-Lead TSSOP Example: XXXX L24H TYWW I821 NNN 12F 8-Lead MSOP Example: XXXXT 4L24HI YWWNNN 82112F 8-Lead 2x3 TDFN Example: XXX AF4 YWW 821 NN 12 © 2008 Microchip Technology Inc. DS22102A-page 13

24AA024H/24LC024H 1st Line Marking Codes Part Number TSSOP MSOP TDFN I E I E I E 24AA024H A24H A24H 4A24HI 4A24HE AF1 AF2 24LC024H L24H L24H 4L24HI 4L24HE AF4 AF5 Legend: XX...X Part number or part number code T Temperature (I, E) Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code (2 characters for small packages) e3 Pb-free JEDEC designator for Matte Tin (Sn) Note: For very small packages with no room for the Pb-free JEDEC designator e3 , the marking will only appear on the outer carton or reel label. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. Note: Please visit www.microchip.com/Pbfree for the latest information on Pb-free conversion. *Standard OTP marking consists of Microchip part number, year code, week code, and traceability code. DS22102A-page 14 © 2008 Microchip Technology Inc.

24AA024H/24LC024H (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)(cid:15)(cid:16)(cid:6)(cid:10)(cid:8)(cid:17)(cid:18)(cid:3)(cid:4)(cid:13)(cid:18)(cid:5)(cid:8)(cid:19)(cid:9)(cid:20)(cid:8)(cid:21)(cid:8)(cid:22)(cid:23)(cid:23)(cid:8)(cid:24)(cid:13)(cid:10)(cid:8)(cid:25)(cid:26)(cid:7)(cid:27)(cid:8)(cid:28)(cid:9)(cid:15)(cid:17)(cid:9)(cid:29) (cid:30)(cid:26)(cid:12)(cid:5)(cid:31) 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) N NOTE1 E1 1 2 3 D E A A2 L A1 c e eB b1 b 6(cid:15)(cid:7)&! (cid:19)7,8.(cid:22) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:2)9(cid:7)’(cid:7)&! (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7"’)(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)(cid:31)(cid:7)(cid:15)! 7 < (cid:31)(cid:7)&(cid:8)(cid:11) (cid:14) (cid:20)(cid:30)(cid:4)(cid:4)(cid:2)1(cid:22), (cid:13)(cid:10)(cid:12)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)&(cid:7)(cid:15)(cid:17)(cid:2)(cid:31)(cid:16)(cid:28)(cid:15)(cid:14) (cid:25) = = (cid:20)(cid:3)(cid:30)(cid:4) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:25)(cid:3) (cid:20)(cid:30)(cid:30)(cid:29) (cid:20)(cid:30)-(cid:4) (cid:20)(cid:30)(cid:24)(cid:29) 1(cid:28)!(cid:14)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)&(cid:7)(cid:15)(cid:17)(cid:2)(cid:31)(cid:16)(cid:28)(cid:15)(cid:14) (cid:25)(cid:30) (cid:20)(cid:4)(cid:30)(cid:29) = = (cid:22)(cid:11)(cid:10)"(cid:16)#(cid:14)(cid:9)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:11)(cid:10)"(cid:16)#(cid:14)(cid:9)(cid:2)>(cid:7)#&(cid:11) . (cid:20)(cid:3)(cid:24)(cid:4) (cid:20)-(cid:30)(cid:4) (cid:20)-(cid:3)(cid:29) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)>(cid:7)#&(cid:11) .(cid:30) (cid:20)(cid:3)(cid:23)(cid:4) (cid:20)(cid:3)(cid:29)(cid:4) (cid:20)(cid:3)<(cid:4) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21) (cid:20)-(cid:23)< (cid:20)-?(cid:29) (cid:20)(cid:23)(cid:4)(cid:4) (cid:13)(cid:7)(cid:12)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)&(cid:7)(cid:15)(cid:17)(cid:2)(cid:31)(cid:16)(cid:28)(cid:15)(cid:14) 9 (cid:20)(cid:30)(cid:30)(cid:29) (cid:20)(cid:30)-(cid:4) (cid:20)(cid:30)(cid:29)(cid:4) 9(cid:14)(cid:28)#(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:8) (cid:20)(cid:4)(cid:4)< (cid:20)(cid:4)(cid:30)(cid:4) (cid:20)(cid:4)(cid:30)(cid:29) 6(cid:12)(cid:12)(cid:14)(cid:9)(cid:2)9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) )(cid:30) (cid:20)(cid:4)(cid:23)(cid:4) (cid:20)(cid:4)?(cid:4) (cid:20)(cid:4)(cid:5)(cid:4) 9(cid:10)*(cid:14)(cid:9)(cid:2)9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) ) (cid:20)(cid:4)(cid:30)(cid:23) (cid:20)(cid:4)(cid:30)< (cid:20)(cid:4)(cid:3)(cid:3) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)(cid:26)(cid:10)*(cid:2)(cid:22)(cid:12)(cid:28)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:2)+ (cid:14)1 = = (cid:20)(cid:23)-(cid:4) (cid:30)(cid:26)(cid:12)(cid:5)(cid:11)(cid:31) (cid:30)(cid:20) (cid:31)(cid:7)(cid:15)(cid:2)(cid:30)(cid:2) (cid:7)!"(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)#(cid:14)$(cid:2)%(cid:14)(cid:28)&"(cid:9)(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)((cid:2))"&(cid:2)’"!&(cid:2))(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)*(cid:7)&(cid:11)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)&(cid:8)(cid:11)(cid:14)#(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) +(cid:2)(cid:22)(cid:7)(cid:17)(cid:15)(cid:7)%(cid:7)(cid:8)(cid:28)(cid:15)&(cid:2),(cid:11)(cid:28)(cid:9)(cid:28)(cid:8)&(cid:14)(cid:9)(cid:7)!&(cid:7)(cid:8)(cid:20) -(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)!(cid:2)(cid:21)(cid:2)(cid:28)(cid:15)#(cid:2).(cid:30)(cid:2)#(cid:10)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)"#(cid:14)(cid:2)’(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:20)(cid:2)(cid:6)(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:2)!(cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:14)$(cid:8)(cid:14)(cid:14)#(cid:2)(cid:20)(cid:4)(cid:30)(cid:4)/(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)!(cid:7)#(cid:14)(cid:20) (cid:23)(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)#(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6).(cid:2)0(cid:30)(cid:23)(cid:20)(cid:29)(cid:6)(cid:20) 1(cid:22),2(cid:2)1(cid:28)!(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)&(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)$(cid:28)(cid:8)&(cid:2) (cid:28)(cid:16)"(cid:14)(cid:2)!(cid:11)(cid:10)*(cid:15)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)!(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17),(cid:4)(cid:23)(cid:27)(cid:4)(cid:30)<1 © 2008 Microchip Technology Inc. DS22102A-page 15

24AA024H/24LC024H (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8) (cid:24)(cid:6)(cid:10)(cid:10)(cid:8)!(cid:16)(cid:12)(cid:10)(cid:13)(cid:18)(cid:5)(cid:8)(cid:19) (cid:30)(cid:20)(cid:8)(cid:21)(cid:8)(cid:30)(cid:6)""(cid:26)#$(cid:8)(cid:22)%&(cid:23)(cid:8)(cid:24)(cid:24)(cid:8)(cid:25)(cid:26)(cid:7)(cid:27)(cid:8)(cid:28) !(cid:17)’(cid:29) (cid:30)(cid:26)(cid:12)(cid:5)(cid:31) 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) D e N E E1 NOTE1 1 2 3 b h α h c A A2 φ A1 L L1 β 6(cid:15)(cid:7)&! (cid:6)(cid:19)99(cid:19)(cid:6).(cid:13).(cid:26)(cid:22) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:2)9(cid:7)’(cid:7)&! (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7"’)(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)(cid:31)(cid:7)(cid:15)! 7 < (cid:31)(cid:7)&(cid:8)(cid:11) (cid:14) (cid:30)(cid:20)(cid:3)(cid:5)(cid:2)1(cid:22), : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)8(cid:14)(cid:7)(cid:17)(cid:11)& (cid:25) = = (cid:30)(cid:20)(cid:5)(cid:29) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:25)(cid:3) (cid:30)(cid:20)(cid:3)(cid:29) = = (cid:22)&(cid:28)(cid:15)#(cid:10)%%(cid:2)(cid:2)+ (cid:25)(cid:30) (cid:4)(cid:20)(cid:30)(cid:4) = (cid:4)(cid:20)(cid:3)(cid:29) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)>(cid:7)#&(cid:11) . ?(cid:20)(cid:4)(cid:4)(cid:2)1(cid:22), (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)>(cid:7)#&(cid:11) .(cid:30) -(cid:20)(cid:24)(cid:4)(cid:2)1(cid:22), : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21) (cid:23)(cid:20)(cid:24)(cid:4)(cid:2)1(cid:22), ,(cid:11)(cid:28)’%(cid:14)(cid:9)(cid:2)@(cid:10)(cid:12)&(cid:7)(cid:10)(cid:15)(cid:28)(cid:16)A (cid:11) (cid:4)(cid:20)(cid:3)(cid:29) = (cid:4)(cid:20)(cid:29)(cid:4) 3(cid:10)(cid:10)&(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) 9 (cid:4)(cid:20)(cid:23)(cid:4) = (cid:30)(cid:20)(cid:3)(cid:5) 3(cid:10)(cid:10)&(cid:12)(cid:9)(cid:7)(cid:15)& 9(cid:30) (cid:30)(cid:20)(cid:4)(cid:23)(cid:2)(cid:26).3 3(cid:10)(cid:10)&(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14) (cid:3) (cid:4)B = <B 9(cid:14)(cid:28)#(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:8) (cid:4)(cid:20)(cid:30)(cid:5) = (cid:4)(cid:20)(cid:3)(cid:29) 9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) ) (cid:4)(cid:20)-(cid:30) = (cid:4)(cid:20)(cid:29)(cid:30) (cid:6)(cid:10)(cid:16)#(cid:2)(cid:21)(cid:9)(cid:28)%&(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14)(cid:2)(cid:13)(cid:10)(cid:12) (cid:4) (cid:29)B = (cid:30)(cid:29)B (cid:6)(cid:10)(cid:16)#(cid:2)(cid:21)(cid:9)(cid:28)%&(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14)(cid:2)1(cid:10)&&(cid:10)’ (cid:5) (cid:29)B = (cid:30)(cid:29)B (cid:30)(cid:26)(cid:12)(cid:5)(cid:11)(cid:31) (cid:30)(cid:20) (cid:31)(cid:7)(cid:15)(cid:2)(cid:30)(cid:2) (cid:7)!"(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)#(cid:14)$(cid:2)%(cid:14)(cid:28)&"(cid:9)(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)((cid:2))"&(cid:2)’"!&(cid:2))(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)*(cid:7)&(cid:11)(cid:7)(cid:15)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)&(cid:8)(cid:11)(cid:14)#(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) +(cid:2)(cid:22)(cid:7)(cid:17)(cid:15)(cid:7)%(cid:7)(cid:8)(cid:28)(cid:15)&(cid:2),(cid:11)(cid:28)(cid:9)(cid:28)(cid:8)&(cid:14)(cid:9)(cid:7)!&(cid:7)(cid:8)(cid:20) -(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)!(cid:2)(cid:21)(cid:2)(cid:28)(cid:15)#(cid:2).(cid:30)(cid:2)#(cid:10)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)"#(cid:14)(cid:2)’(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:20)(cid:2)(cid:6)(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:2)!(cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:14)$(cid:8)(cid:14)(cid:14)#(cid:2)(cid:4)(cid:20)(cid:30)(cid:29)(cid:2)’’(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)!(cid:7)#(cid:14)(cid:20) (cid:23)(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)#(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6).(cid:2)0(cid:30)(cid:23)(cid:20)(cid:29)(cid:6)(cid:20) 1(cid:22),2 1(cid:28)!(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)&(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)$(cid:28)(cid:8)&(cid:2) (cid:28)(cid:16)"(cid:14)(cid:2)!(cid:11)(cid:10)*(cid:15)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)!(cid:20) (cid:26).32 (cid:26)(cid:14)%(cid:14)(cid:9)(cid:14)(cid:15)(cid:8)(cid:14)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)((cid:2)"!"(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)((cid:2)%(cid:10)(cid:9)(cid:2)(cid:7)(cid:15)%(cid:10)(cid:9)’(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:12)"(cid:9)(cid:12)(cid:10)!(cid:14)!(cid:2)(cid:10)(cid:15)(cid:16)(cid:18)(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17),(cid:4)(cid:23)(cid:27)(cid:4)(cid:29)(cid:5)1 DS22102A-page 16 © 2008 Microchip Technology Inc.

24AA024H/24LC024H (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8) (cid:24)(cid:6)(cid:10)(cid:10)(cid:8)!(cid:16)(cid:12)(cid:10)(cid:13)(cid:18)(cid:5)(cid:8)(cid:19) (cid:30)(cid:20)(cid:8)(cid:21)(cid:8)(cid:30)(cid:6)""(cid:26)#$(cid:8)(cid:22)%&(cid:23)(cid:8)(cid:24)(cid:24)(cid:8)(cid:25)(cid:26)(cid:7)(cid:27)(cid:8)(cid:28) !(cid:17)’(cid:29) (cid:30)(cid:26)(cid:12)(cid:5)(cid:31) 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) © 2008 Microchip Technology Inc. DS22102A-page 17

24AA024H/24LC024H (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)()(cid:13)(cid:18)(cid:8) )"(cid:13)(cid:18)*(cid:8) (cid:24)(cid:6)(cid:10)(cid:10)(cid:8)!(cid:16)(cid:12)(cid:10)(cid:13)(cid:18)(cid:5)(cid:8)(cid:19) ((cid:20)(cid:8)(cid:21)(cid:8)+%+(cid:8)(cid:24)(cid:24)(cid:8)(cid:25)(cid:26)(cid:7)(cid:27)(cid:8)(cid:28)( !(cid:9)(cid:29) (cid:30)(cid:26)(cid:12)(cid:5)(cid:31) 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) D N E E1 NOTE1 1 2 b e c A A2 φ A1 L1 L 6(cid:15)(cid:7)&! (cid:6)(cid:19)99(cid:19)(cid:6).(cid:13).(cid:26)(cid:22) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:2)9(cid:7)’(cid:7)&! (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7"’)(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)(cid:31)(cid:7)(cid:15)! 7 < (cid:31)(cid:7)&(cid:8)(cid:11) (cid:14) (cid:4)(cid:20)?(cid:29)(cid:2)1(cid:22), : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)8(cid:14)(cid:7)(cid:17)(cid:11)& (cid:25) = = (cid:30)(cid:20)(cid:3)(cid:4) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:25)(cid:3) (cid:4)(cid:20)<(cid:4) (cid:30)(cid:20)(cid:4)(cid:4) (cid:30)(cid:20)(cid:4)(cid:29) (cid:22)&(cid:28)(cid:15)#(cid:10)%%(cid:2) (cid:25)(cid:30) (cid:4)(cid:20)(cid:4)(cid:29) = (cid:4)(cid:20)(cid:30)(cid:29) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)>(cid:7)#&(cid:11) . ?(cid:20)(cid:23)(cid:4)(cid:2)1(cid:22), (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)>(cid:7)#&(cid:11) .(cid:30) (cid:23)(cid:20)-(cid:4) (cid:23)(cid:20)(cid:23)(cid:4) (cid:23)(cid:20)(cid:29)(cid:4) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21) (cid:3)(cid:20)(cid:24)(cid:4) -(cid:20)(cid:4)(cid:4) -(cid:20)(cid:30)(cid:4) 3(cid:10)(cid:10)&(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) 9 (cid:4)(cid:20)(cid:23)(cid:29) (cid:4)(cid:20)?(cid:4) (cid:4)(cid:20)(cid:5)(cid:29) 3(cid:10)(cid:10)&(cid:12)(cid:9)(cid:7)(cid:15)& 9(cid:30) (cid:30)(cid:20)(cid:4)(cid:4)(cid:2)(cid:26).3 3(cid:10)(cid:10)&(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14) (cid:3) (cid:4)B = <B 9(cid:14)(cid:28)#(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:8) (cid:4)(cid:20)(cid:4)(cid:24) = (cid:4)(cid:20)(cid:3)(cid:4) 9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) ) (cid:4)(cid:20)(cid:30)(cid:24) = (cid:4)(cid:20)-(cid:4) (cid:30)(cid:26)(cid:12)(cid:5)(cid:11)(cid:31) (cid:30)(cid:20) (cid:31)(cid:7)(cid:15)(cid:2)(cid:30)(cid:2) (cid:7)!"(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)#(cid:14)$(cid:2)%(cid:14)(cid:28)&"(cid:9)(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)((cid:2))"&(cid:2)’"!&(cid:2))(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)*(cid:7)&(cid:11)(cid:7)(cid:15)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)&(cid:8)(cid:11)(cid:14)#(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)!(cid:2)(cid:21)(cid:2)(cid:28)(cid:15)#(cid:2).(cid:30)(cid:2)#(cid:10)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)"#(cid:14)(cid:2)’(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:20)(cid:2)(cid:6)(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:2)!(cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:14)$(cid:8)(cid:14)(cid:14)#(cid:2)(cid:4)(cid:20)(cid:30)(cid:29)(cid:2)’’(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)!(cid:7)#(cid:14)(cid:20) -(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)#(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6).(cid:2)0(cid:30)(cid:23)(cid:20)(cid:29)(cid:6)(cid:20) 1(cid:22),2 1(cid:28)!(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)&(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)$(cid:28)(cid:8)&(cid:2) (cid:28)(cid:16)"(cid:14)(cid:2)!(cid:11)(cid:10)*(cid:15)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)!(cid:20) (cid:26).32 (cid:26)(cid:14)%(cid:14)(cid:9)(cid:14)(cid:15)(cid:8)(cid:14)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)((cid:2)"!"(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)((cid:2)%(cid:10)(cid:9)(cid:2)(cid:7)(cid:15)%(cid:10)(cid:9)’(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:12)"(cid:9)(cid:12)(cid:10)!(cid:14)!(cid:2)(cid:10)(cid:15)(cid:16)(cid:18)(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17),(cid:4)(cid:23)(cid:27)(cid:4)<?1 DS22102A-page 18 © 2008 Microchip Technology Inc.

24AA024H/24LC024H (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8),(cid:13)(cid:14)"(cid:26)(cid:8) (cid:24)(cid:6)(cid:10)(cid:10)(cid:8)!(cid:16)(cid:12)(cid:10)(cid:13)(cid:18)(cid:5)(cid:8)(cid:9)(cid:6)(cid:14)*(cid:6)-(cid:5)(cid:8)(cid:19), (cid:20)(cid:8)(cid:28), !(cid:9)(cid:29) (cid:30)(cid:26)(cid:12)(cid:5)(cid:31) 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) D N E E1 NOTE1 1 2 e b c A A2 φ A1 L1 L 6(cid:15)(cid:7)&! (cid:6)(cid:19)99(cid:19)(cid:6).(cid:13).(cid:26)(cid:22) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:2)9(cid:7)’(cid:7)&! (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7"’)(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)(cid:31)(cid:7)(cid:15)! 7 < (cid:31)(cid:7)&(cid:8)(cid:11) (cid:14) (cid:4)(cid:20)?(cid:29)(cid:2)1(cid:22), : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)8(cid:14)(cid:7)(cid:17)(cid:11)& (cid:25) = = (cid:30)(cid:20)(cid:30)(cid:4) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:25)(cid:3) (cid:4)(cid:20)(cid:5)(cid:29) (cid:4)(cid:20)<(cid:29) (cid:4)(cid:20)(cid:24)(cid:29) (cid:22)&(cid:28)(cid:15)#(cid:10)%%(cid:2) (cid:25)(cid:30) (cid:4)(cid:20)(cid:4)(cid:4) = (cid:4)(cid:20)(cid:30)(cid:29) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)>(cid:7)#&(cid:11) . (cid:23)(cid:20)(cid:24)(cid:4)(cid:2)1(cid:22), (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)>(cid:7)#&(cid:11) .(cid:30) -(cid:20)(cid:4)(cid:4)(cid:2)1(cid:22), : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21) -(cid:20)(cid:4)(cid:4)(cid:2)1(cid:22), 3(cid:10)(cid:10)&(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) 9 (cid:4)(cid:20)(cid:23)(cid:4) (cid:4)(cid:20)?(cid:4) (cid:4)(cid:20)<(cid:4) 3(cid:10)(cid:10)&(cid:12)(cid:9)(cid:7)(cid:15)& 9(cid:30) (cid:4)(cid:20)(cid:24)(cid:29)(cid:2)(cid:26).3 3(cid:10)(cid:10)&(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14) (cid:3) (cid:4)B = <B 9(cid:14)(cid:28)#(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:8) (cid:4)(cid:20)(cid:4)< = (cid:4)(cid:20)(cid:3)- 9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) ) (cid:4)(cid:20)(cid:3)(cid:3) = (cid:4)(cid:20)(cid:23)(cid:4) (cid:30)(cid:26)(cid:12)(cid:5)(cid:11)(cid:31) (cid:30)(cid:20) (cid:31)(cid:7)(cid:15)(cid:2)(cid:30)(cid:2) (cid:7)!"(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)#(cid:14)$(cid:2)%(cid:14)(cid:28)&"(cid:9)(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)((cid:2))"&(cid:2)’"!&(cid:2))(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)*(cid:7)&(cid:11)(cid:7)(cid:15)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)&(cid:8)(cid:11)(cid:14)#(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)!(cid:2)(cid:21)(cid:2)(cid:28)(cid:15)#(cid:2).(cid:30)(cid:2)#(cid:10)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)"#(cid:14)(cid:2)’(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:20)(cid:2)(cid:6)(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:2)!(cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:14)$(cid:8)(cid:14)(cid:14)#(cid:2)(cid:4)(cid:20)(cid:30)(cid:29)(cid:2)’’(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)!(cid:7)#(cid:14)(cid:20) -(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)#(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6).(cid:2)0(cid:30)(cid:23)(cid:20)(cid:29)(cid:6)(cid:20) 1(cid:22),2 1(cid:28)!(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)&(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)$(cid:28)(cid:8)&(cid:2) (cid:28)(cid:16)"(cid:14)(cid:2)!(cid:11)(cid:10)*(cid:15)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)!(cid:20) (cid:26).32 (cid:26)(cid:14)%(cid:14)(cid:9)(cid:14)(cid:15)(cid:8)(cid:14)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)((cid:2)"!"(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)((cid:2)%(cid:10)(cid:9)(cid:2)(cid:7)(cid:15)%(cid:10)(cid:9)’(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:12)"(cid:9)(cid:12)(cid:10)!(cid:14)!(cid:2)(cid:10)(cid:15)(cid:16)(cid:18)(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17),(cid:4)(cid:23)(cid:27)(cid:30)(cid:30)(cid:30)1 © 2008 Microchip Technology Inc. DS22102A-page 19

24AA024H/24LC024H (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)(cid:15)(cid:16)(cid:6)(cid:10)(cid:8).(cid:10)(cid:6)(cid:12)$(cid:8)(cid:30)(cid:26)(cid:8)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:6)(cid:14)*(cid:6)-(cid:5)(cid:8)(cid:19),(cid:30)(cid:20)(cid:8)(cid:21)(cid:8)/0(cid:22)0(cid:23)%12(cid:8)(cid:24)(cid:24)(cid:8)(cid:25)(cid:26)(cid:7)(cid:27)(cid:8)(cid:28)((cid:15).(cid:30)(cid:29) (cid:30)(cid:26)(cid:12)(cid:5)(cid:31) 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) DS22102A-page 20 © 2008 Microchip Technology Inc.

24AA024H/24LC024H (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)(cid:15)(cid:16)(cid:6)(cid:10)(cid:8).(cid:10)(cid:6)(cid:12)$(cid:8)(cid:30)(cid:26)(cid:8)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:6)(cid:14)*(cid:6)-(cid:5)(cid:8)(cid:19),(cid:30)(cid:20)(cid:8)(cid:21)(cid:8)/0(cid:22)0(cid:23)%12(cid:8)(cid:24)(cid:24)(cid:8)(cid:25)(cid:26)(cid:7)(cid:27)(cid:8)(cid:28)((cid:15).(cid:30)(cid:29) (cid:30)(cid:26)(cid:12)(cid:5)(cid:31) 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) © 2008 Microchip Technology Inc. DS22102A-page 21

24AA024H/24LC024H REVISION HISTORY Revision A (08/2008) Original release. DS22102A-page 22 © 2008 Microchip Technology Inc.

24AA024H/24LC024H THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at Users of Microchip products can receive assistance www.microchip.com. This web site is used as a means through several channels: to make files and information easily available to • Distributor or Representative customers. Accessible by using your favorite Internet • Local Sales Office browser, the web site contains the following • Field Application Engineer (FAE) information: • Technical Support • Product Support – Data sheets and errata, • Development Systems Information Line application notes and sample programs, design resources, user’s guides and hardware support Customers should contact their distributor, documents, latest software releases and archived representative or field application engineer (FAE) for software support. Local sales offices are also available to help • General Technical Support – Frequently Asked customers. A listing of sales offices and locations is Questions (FAQ), technical support requests, included in the back of this document. online discussion groups, Microchip consultant Technical support is available through the web site program member listing at: http://support.microchip.com • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions. © 2008 Microchip Technology Inc. DS22102A-page 23

24AA024H/24LC024H READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod- uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: Technical Publications Manager Total Pages Sent ________ RE: Reader Response From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y N Device: 24AA024H/24LC024H Literature Number: DS22102A Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS22102A-page 24 © 2008 Microchip Technology Inc.

24AA024H/24LC024H PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX Examples: a) 24AA024H-I/P: Industrial Temperature, Device Temperature Package 1.7V, PDIP package. Range b) 24AA024H-I/SN: Industrial Temperature, 1.7V, SOIC Package. Device: 24AA024H: 1.7V, 2Kbit Addressable Serial EEPROM c) 24AA024HT-I/ST: Industrial Temperature, 24AA024HT: 1.7V, 2Kbit Addressable Serial EEPROM 1.7V, TSSOP Package, Tape and Reel (Tape and Reel) 24LC024H: 2.5V, 2Kbit Addressable Serial EEPROM 24LC024HT: 2.5V, 2Kbit Addressable Serial EEPROM a) 24LC024H-I/P: Industrial Temperature, (Tape and Reel) 2.5V, PDIP Package. b) 24LC024HT-E/SN: Automotive Temper- Temperature Range: I = -40°C to +85°C ature, 2.5V, SOIC Package, Tape and E = -40°C to +125°C Reel c) 24LC024HT-I/MS: Industrial Tempera- Package: P = Plastic DIP, (300 mil Body), 8-lead ture, 2.5V, MSOP Package, Tape and SN = Plastic SOIC, (3.90 mm Body) Reel. ST = TSSOP, (4.4 mm Body), 8-lead MS = MSOP, (Plastic Micro Small Outline), 8-lead MNY(1)= TDFN, (2x3x0.75 mm Body), 8-lead Note 1: “Y” indicates a Nickel Palladium Gold (NiPdAu) finish. © 2008 Microchip Technology Inc. DS22102A-page 25

24AA024H/24LC024H NOTES: DS22102A-page 26 © 2008 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, Accuron, and may be superseded by updates. It is your responsibility to dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, ensure that your application meets with your specifications. PICSTART, rfPIC and SmartShunt are registered trademarks MICROCHIP MAKES NO REPRESENTATIONS OR of Microchip Technology Incorporated in the U.S.A. and other WARRANTIES OF ANY KIND WHETHER EXPRESS OR countries. IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, FilterLab, Linear Active Thermistor, MXDEV, MXLAB, INCLUDING BUT NOT LIMITED TO ITS CONDITION, SEEVAL, SmartSensor and The Embedded Control Solutions QUALITY, PERFORMANCE, MERCHANTABILITY OR Company are registered trademarks of Microchip Technology FITNESS FOR PURPOSE. Microchip disclaims all liability Incorporated in the U.S.A. arising from this information and its use. Use of Microchip Analog-for-the-Digital Age, Application Maestro, CodeGuard, devices in life support and/or safety applications is entirely at dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, the buyer’s risk, and the buyer agrees to defend, indemnify and ECONOMONITOR, FanSense, In-Circuit Serial hold harmless Microchip from any and all damages, claims, Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB suits, or expenses resulting from such use. No licenses are Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM, conveyed, implicitly or otherwise, under any Microchip PICDEM.net, PICtail, PIC32 logo, PowerCal, PowerInfo, intellectual property rights. PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2008, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. © 2008 Microchip Technology Inc. DS22102A-page 27

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