24AA1025/24LC1025/24FC1025 2 1024K I C™ CMOS Serial EEPROM Device Selection Table: This device is capable of both random and sequential reads. Reads may be sequential within address bound- Part VCC Max. Clock Temp aries 0000h to FFFFh and 10000h to 1FFFFh. Number Range Frequency Ranges Functional address lines allow up to four devices on the 24AA1025 1.7-5.5V 400kHz† I same data bus. This allows for up to 4Mbits total system EEPROM memory. This device is available in 24LC1025 2.5-5.5V 400kHz* I, E the standard 8-pin PDIP and SOIJ packages. 24FC1025 2.5-5.5V 1MHz I †100kHz for VCC < 2.5V. Package Type *100 kHz for VCC < 4.5V, E-temp. PDIP A0 1 8 VCC Features: A1 2 7 WP • Single supply with operation down to 1.7V for 24AAXX devices, 2.5V for 24LCXX devices A2 3 6 SCL (cid:129) Low-power CMOS technology: VSS 4 5 SDA - Read current 1 mA, typical - Standby current 100 nA, typical SOIJ (cid:129) 2-wire serial interface, I 2C™ compatible A0 1 8 VCC (cid:129) Cascadable up to four devices (cid:129) Schmitt Trigger inputs for noise suppression A1 2 7 WP (cid:129) Output slope control to eliminate ground bounce A2 3 6 SCL (cid:129) 100 kHz and 400 kHz clock compatibility VSS 4 5 SDA (cid:129) 1 MHz clock for FC versions (cid:129) Page write time 3 ms, typical (cid:129) Self-timed erase/write cycle Block Diagram (cid:129) 128-byte page write buffer (cid:129) Hardware write-protect A0A1 WP HVGenerator (cid:129) ESD protection >400V (cid:129) More than 1 million erase/write cycles (cid:129) Data retention >200 years I/O Memory EEPROM (cid:129) Factory programming available Control Control XDEC Array Logic Logic (cid:129) Packages include 8-lead PDIP, SOIJ Page Latches (cid:129) Pb-free and RoHS compliant (cid:129) Temperature ranges: I/O SCL - Industrial (I): -40°C to +85°C YDEC - Automotive (E):-40°C to +125°C SDA Description: VCC VSS Sense AMP The Microchip Technology Inc. 24AA1025/24LC1025/ R/W Control 24FC1025 (24XX1025*) is a 128K x 8 (1024K bit) Serial Electrically Erasable PROM, capable of opera- tion across a broad voltage range (1.8V to 5.5V). It has been developed for advanced, low-power applications such as personal communications or data acquisition. This device has both byte write and page write *24XX1025 is used in this document as a generic part number capability of up to 128 bytes of data. for the 24AA1025/24LC1025/24FC1025 devices. Preliminary © 2007 Microchip Technology Inc. DS21941E-page 1

24AA1025/24LC1025/24FC1025 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings(†) VCC.............................................................................................................................................................................6.5V All inputs and outputs w.r.t. VSS.........................................................................................................-0.6V to VCC +1.0V Storage temperature...............................................................................................................................-65°C to +150°C Ambient temperature with power applied................................................................................................-40°C to +125°C ESD protection on all pins......................................................................................................................................................≥ 4kV † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. TABLE 1-1: DC CHARACTERISTICS Industrial (I): VCC = +1.7V to 5.5V TA = -40°C to +85°C DC CHARACTERISTICS Automotive (E): VCC = +2.5V to 5.5VTA = -40°C to +125°C Param. Sym. Characteristic Min. Max. Units Conditions No. D1 A0, A1, SCL, SDA and — — — WP pins: D2 VIH High-level input voltage 0.7 VCC — V D3 VIL Low-level input voltage — 0.3 VCC V VCC ≥ 2.5V 0.2 VCC V VCC < 2.5V D4 VHYS Hysteresis of Schmitt 0.05 VCC — V VCC ≥ 2.5V (Note) Trigger inputs (SDA, SCL pins) D5 VOL Low-level output voltage — 0.40 V IOL = 3.0mA @ VCC = 4.5V IOL = 2.1mA @ VCC = 2.5V D6 ILI Input leakage current — ±1 μA VIN = VSS or VCC, WP = VSS VIN = VSS or VCC, WP = VCC D7 ILO Output leakage current — ±1 μA VOUT = VSS or VCC D8 CIN, Pin capacitance — 10 pF VCC = 5.0V (Note) COUT (all inputs/outputs) TA = 25°C, FCLK = 1MHz D9 ICC Read Operating current — 450 μA VCC = 5.5V, SCL = 400kHz ICC Write — 5 mA VCC = 5.5V D10 ICCS Standby current — 5 μA TA = -40°C to 85°C SCL = SDA = VCC = 5.5V A0, A1, WP = VSS, A2 = VCC Note: This parameter is periodically sampled and not 100% tested. Preliminary DS21941E-page 2 © 2007 Microchip Technology Inc.

24AA1025/24LC1025/24FC1025 TABLE 1-2: AC CHARACTERISTICS Industrial (I): VCC = +1.7V to 5.5V TA = -40°C to +85°C AC CHARACTERISTICS Automotive (E): VCC = +2.5V to 5.5V TA = -40°C to +125°C Param. Sym. Characteristic Min. Max. Units Conditions No. 1 FCLK Clock frequency — 100 kHz 1.7V ≤ VCC ≤ 2.5V — 400 2.5V ≤ VCC ≤ 5.5V (Note 5) — 1000 2.5V ≤ VCC ≤ 5.5V (24FC1025 only) 2 THIGH Clock high time 4000 — ns 1.7V ≤ VCC ≤ 2.5V 600 — 2.5V ≤ VCC ≤ 5.5V 500 — 2.5V ≤ VCC ≤ 5.5V (24FC1025 only) 3 TLOW Clock low time 4700 — ns 1.7V ≤ VCC ≤ 2.5V 1300 — 2.5V ≤ VCC ≤ 5.5V 500 — 2.5V ≤ VCC ≤ 5.5V (24FC1025 only) 4 TR SDA and SCL rise time — 1000 ns 1.7V ≤ VCC ≤ 2.5V (Note1) — 300 2.5V ≤ VCC ≤ 5.5V — 300 2.5V ≤ VCC ≤ 5.5V (24FC1025 only) 5 TF SDA and SCL fall time — 300 ns All except, 24FC1025 (Note1) — 100 2.5V ≤ VCC ≤ 5.5V (24FC1025 only) 6 THD:STA Start condition hold time 4000 — ns 1.7V ≤ VCC ≤ 2.5V 600 — 2.5V ≤ VCC ≤ 5.5V 250 — 2.5V ≤ VCC ≤ 5.5V (24FC1025 only) 7 TSU:STA Start condition setup time 4700 — ns 1.7V ≤ VCC ≤ 2.5V 600 — 2.5V ≤ VCC ≤ 5.5V 250 — 2.5V ≤ VCC ≤ 5.5V (24FC1025 only) 8 THD:DAT Data input hold time 0 — ns (Note2) 9 TSU:DAT Data input setup time 250 — ns 1.7V ≤ VCC ≤ 2.5V 100 — 2.5V ≤ VCC ≤ 5.5V 100 — 2.5V ≤ VCC ≤ 5.5V (24FC1025 only) 10 TSU:STO Stop condition setup time 4000 — ns 1.7V ≤ VCC ≤ 2.5V 600 — 2.5V ≤ VCC ≤ 5.5V 250 — 2.5V ≤ VCC ≤ 5.5V (24FC1025 only) 11 TSU:WP WP setup time 4000 — ns 1.7V ≤ VCC ≤ 2.5V 600 — 2.5V ≤ VCC ≤ 5.5V 600 — 2.5V ≤ VCC ≤ 5.5V (24FC1025 only) 12 THD:WP WP hold time 4700 — ns 1.7V ≤ VCC ≤ 2.5V 1300 — 2.5V ≤ VCC ≤ 5.5V 1300 — 2.5V ≤ VCC ≤ 5.5V (24FC1025 only) 13 TAA Output valid from clock — 3500 ns 1.7V ≤ VCC ≤ 2.5V (Note2) — 900 2.5V ≤ VCC ≤ 5.5V — 400 2.5V ≤ VCC ≤ 5.5V (24FC1025 only) 14 TBUF Bus free time: Time the bus 4700 — ns 1.7V ≤ VCC ≤ 2.5V must be free before a new 1300 — 2.5V ≤ VCC ≤ 5.5V transmission can start 500 — 2.5V ≤ VCC ≤ 5.5V (24FC1025 only) 15 TOF Output fall time from VIH 10 + 0.1CB 250 ns All except, 24FC1025 (Note1) minimum to VIL maximum 250 24FC1025 (Note1) CB ≤ 100pF 16 TSP Input filter spike suppression — 50 ns All except, 24FC1025 (Notes1 and3) (SDA and SCL pins) Note 1: Not 100% tested. CB = total capacitance of one bus line in pF. 2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. 3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs which provide improved noise spike suppression. This eliminates the need for a TI specification for standard operation. 4: This parameter is not tested but established by characterization. For endurance estimates in a specific application, please consult the Total Endurance™ Model which can be obtained from Microchip’s web site at www.microchip.com. 5: Max. clock frequency is 100 kHz for E-temp devices <4.5V. 1.7-2.5V (100 kHz) timings must be used. Preliminary © 2007 Microchip Technology Inc. DS21941E-page 3

24AA1025/24LC1025/24FC1025 Industrial (I): VCC = +1.7V to 5.5V TA = -40°C to +85°C AC CHARACTERISTICS (Continued) Automotive (E): VCC = +2.5V to 5.5V TA = -40°C to +125°C Param. Sym. Characteristic Min. Max. Units Conditions No. 17 TWC Write cycle time (byte or page) — 5 ms 3 ms, typical 18 Endurance 1 M — cycles 25°C (Note4) Note 1: Not 100% tested. CB = total capacitance of one bus line in pF. 2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. 3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs which provide improved noise spike suppression. This eliminates the need for a TI specification for standard operation. 4: This parameter is not tested but established by characterization. For endurance estimates in a specific application, please consult the Total Endurance™ Model which can be obtained from Microchip’s web site at www.microchip.com. 5: Max. clock frequency is 100 kHz for E-temp devices <4.5V. 1.7-2.5V (100 kHz) timings must be used. FIGURE 1-1: BUS TIMING DATA 5 4 2 D4 SCL 7 3 8 9 10 SDA 6 IN 16 13 14 SDA OUT (protected) WP 11 12 (unprotected) Preliminary DS21941E-page 4 © 2007 Microchip Technology Inc.

24AA1025/24LC1025/24FC1025 2.0 PIN DESCRIPTIONS 2.4 Serial Clock (SCL) The descriptions of the pins are listed in Table2-1. This input is used to synchronize the data transfer from and to the device. TABLE 2-1: PIN FUNCTION TABLE 2.5 Write-Protect (WP) Name PDIP SOIJ Function A0 1 1 User Configurable Chip Select This pin must be connected to either VSS or VCC. If tied to VSS, write operations are enabled. If tied to VCC, A1 2 2 User Configurable Chip Select write operations are inhibited, but read operations are A2 3 3 Non-Configurable Chip Select. not affected. This pin must be hard-wired to logical 1 state (VCC). Device 3.0 FUNCTIONAL DESCRIPTION will not operate with this pin left floating or held to logical 0 The 24XX1025 supports a bidirectional 2-wire bus and (VSS). data transmission protocol. A device that sends data VSS 4 4 Ground onto the bus is defined as a transmitter and a device receiving data, as a receiver. The bus must be SDA 5 5 Serial Data controlled by a master device which generates the SCL 6 6 Serial Clock Serial Clock (SCL), controls the bus access, and WP 7 7 Write-Protect Input generates the Start and Stop conditions while the VCC 8 8 +1.7 to 5.5V (24AA1025) 24XX1025 works as a slave. Both master and slave +2.5 to 5.5V (24LC1025) can operate as a transmitter or receiver, but the master +2.5 to 5.5V (24FC1025) device determines which mode is activated. 2.1 A0, A1 Chip Address Inputs The A0, A1 inputs are used by the 24XX1025 for multi- ple device operations. The levels on these inputs are compared with the corresponding bits in the slave address. The chip is selected if the comparison is true. Up to four devices may be connected to the same bus by using different Chip Select bit combinations. In most applications, the chip address inputs A0 and A1 are hard-wired to logic ‘0’ or logic ‘1’. For applications in which these pins are controlled by a microcontroller or other programmable device, the chip address pins must be driven to logic ‘0’ or logic ‘1’ before normal device operation can proceed. 2.2 A2 Chip Address Input The A2 input is non-configurable Chip Select. This pin must be tied to VCC in order for this device to operate. 2.3 Serial Data (SDA) This is a bidirectional pin used to transfer addresses and data into and data out of the device. It is an open- drain terminal, therefore, the SDA bus requires a pull- up resistor to VCC (typical 10kΩ for 100kHz, 2kΩ for 400kHz and 1MHz). For normal data transfer SDA is allowed to change only during SCL low. Changes during SCL high are reserved for indicating the Start and Stop conditions. Preliminary © 2007 Microchip Technology Inc. DS21941E-page 5

24AA1025/24LC1025/24FC1025 4.0 BUS CHARACTERISTICS The data on the line must be changed during the low period of the clock signal. There is one bit of data per The following bus protocol has been defined: clock pulse. (cid:129) Data transfer may be initiated only when the bus Each data transfer is initiated with a Start condition and is not busy. terminated with a Stop condition. The number of the (cid:129) During data transfer, the data line must remain data bytes transferred between the Start and Stop stable whenever the clock line is high. Changes in conditions is determined by the master device. the data line while the clock line is high will be interpreted as a Start or Stop condition. 4.5 Acknowledge Accordingly, the following bus conditions have been Each receiving device, when addressed, is obliged to defined (Figure4-1). generate an Acknowledge signal after the reception of each byte. The master device must generate an extra 4.1 Bus Not Busy (A) clock pulse which is associated with this Acknowledge bit. Both data and clock lines remain high. Note: The 24XX1025 does not generate any 4.2 Start Data Transfer (B) Acknowledge bits if an internal program- ming cycle is in progress, however, the A high-to-low transition of the SDA line while the clock control byte that is being polled must (SCL) is high determines a Start condition. All match the control byte used to initiate the commands must be preceded by a Start condition. write cycle. A device that acknowledges must pull-down the SDA 4.3 Stop Data Transfer (C) line during the Acknowledge clock pulse in such a way A low-to-high transition of the SDA line while the clock that the SDA line is stable low during the high period of (SCL) is high determines a Stop condition. All the acknowledge related clock pulse. Of course, setup operations must end with a Stop condition. and hold times must be taken into account. During reads, a master must signal an end of data to the slave 4.4 Data Valid (D) by NOT generating an Acknowledge bit on the last byte that has been clocked out of the slave. In this case, the The state of the data line represents valid data when, slave (24XX1025) will leave the data line high to enable after a Start condition, the data line is stable for the the master to generate the Stop condition. duration of the high period of the clock signal. FIGURE 4-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS (A) (B) (D) (D) (C) (A) SCL SDA Start Address or Data Stop Condition Acknowledge Allowed Condition Valid To Change FIGURE 4-2: ACKNOWLEDGE TIMING Acknowledge Bit SCL 1 2 3 4 5 6 7 8 9 1 2 3 SDA Data from transmitter Data from transmitter Transmitter must release the SDA line at this point Receiver must release the SDA line at this point allowing the Receiver to pull the SDA line low to so the Transmitter can continue sending data. acknowledge the previous eight bits of data. Preliminary DS21941E-page 6 © 2007 Microchip Technology Inc.

24AA1025/24LC1025/24FC1025 5.0 DEVICE ADDRESSING FIGURE 5-1: CONTROL BYTE FORMAT A control byte is the first byte received following the Start condition from the master device (Figure5-1). Read/Write Bit The control byte consists of a 4-bit control code; for the Block Chip 24XX1025, this is set as ‘1010’ binary for read and Select Select write operations. The next bit of the control byte is the Control Code Bits Bits block select bit (B0). This bit acts as the A16 address bit for accessing the entire array. The next two bits of S 1 0 1 0 B0 A1 A0 R/W ACK the control byte are the Chip Select bits (A1, A0). The Chip Select bits allow the use of up to four 24XX1025 Slave Address devices on the same bus and are used to select which device is accessed. The Chip Select bits in the control Start Bit Acknowledge Bit byte must correspond to the logic levels on the corre- sponding A1 and A0 pins for the device to respond. These bits are in effect the two Most Significant bits of 5.1 Contiguous Addressing Across the word address. Multiple Devices The last bit of the control byte defines the operation to be performed. When set to a one, a read operation is The Chip Select bits A1, A0 can be used to expand the selected, and when set to a zero, a write operation is contiguous address space for up to 4Mbit by adding up selected. The next two bytes received define the to four 24XX1025’s on the same bus. In this case, address of the first data byte (Figure5-2). The upper software can use A0 of the control byte as address bit address bits are transferred first, followed by the Less A16 and A1 as address bit A17. It is not possible to Significant bits. sequentially read across device boundaries. Following the Start condition, the 24XX1025 monitors Each device has internal addressing boundary the SDA bus checking the device type identifier being limitations. This divides each part into two segments of transmitted. Upon receiving a ‘1010’ code and appro- 512K bits. The block select bit ‘B0’ controls access to priate device select bits, the slave device outputs an each “half”. Acknowledge signal on the SDA line. Depending on the Sequential read operations are limited to 512K blocks. state of the R/W bit, the 24XX1025 will select a read or To read through four devices on the same bus, eight write operation. random Read commands must be given. This device has an internal addressing boundary limitation that is divided into two segments of 512K bits. Block select bit ‘B0’ to control access to each segment. FIGURE 5-2: ADDRESS SEQUENCE BIT ASSIGNMENTS Control Byte Address High Byte Address Low Byte B A A A A A A A A A A A A 1 0 1 0 0 1 0 R/W 15 14 13 12 11 10 9 8 7 (cid:129) (cid:129) (cid:129) (cid:129) (cid:129) (cid:129) 0 Control Block Chip Code Select Select X = “don’t care” bit Bit Bits Preliminary © 2007 Microchip Technology Inc. DS21941E-page 7

24AA1025/24LC1025/24FC1025 6.0 WRITE OPERATIONS 6.3 Write Protection The WP pin allows the user to write-protect the entire 6.1 Byte Write array (00000-1FFFF) when the pin is tied to VCC. If tied Following the Start condition from the master, the to VSS the write protection is disabled. The WP pin is sampled at the Stop bit for every Write command control code (four bits), the block select (one bit), the (Figure1-1). Toggling the WP pin after the Stop bit will Chip Select (two bits), and the R/W bit (which is a logic have no effect on the execution of the write cycle. low) are clocked onto the bus by the master transmitter. This indicates to the addressed slave receiver that the Note: Page write operations are limited to writing address high byte will follow after it has generated an bytes within a single physical page, Acknowledge bit during the ninth clock cycle. There- regardless of the number of bytes actually fore, the next byte transmitted by the master is the being written. Physical page boundaries high-order byte of the word address and will be written start at addresses that are integer into the Address Pointer of the 24XX1025. The next multiples of the page buffer size (or ‘page byte is the Least Significant Address Byte. After receiv- size’) and end at addresses that are ing another Acknowledge signal from the 24XX1025, integer multiples of [page size – 1]. If a the master device will transmit the data word to be writ- Page Write command attempts to write ten into the addressed memory location. The across a physical page boundary, the 24XX1025 acknowledges again and the master gener- result is that the data wraps around to the ates a Stop condition. This initiates the internal write beginning of the current page (overwriting cycle and during this time, the 24XX1025 will not gen- data previously stored there), instead of erate Acknowledge signals as long as the control byte being written to the next page as might be being polled matches the control byte that was used to expected. It is therefore, necessary for the initiate the write (Figure6-1). If an attempt is made to application software to prevent page write write to the array with the WP pin held high, the device operations that would attempt to cross a will acknowledge the command, but no write cycle will page boundary. occur, no data will be written and the device will immediately accept a new command. After a byte Write command, the internal address counter will point to the address location following the one that was just written. 6.2 Page Write The write control byte, word address and the first data byte are transmitted to the 24XX1025 in the same way as in a byte write. But instead of generating a Stop condition, the master transmits up to 127 additional bytes, which are temporarily stored in the on-chip page buffer and will be written into memory after the master has transmitted a Stop condition. After receipt of each word, the seven lower Address Pointer bits are inter- nally incremented by one. If the master should transmit more than 128 bytes prior to generating the Stop con- dition, the address counter will roll over and the previ- ously received data will be overwritten. As with the byte write operation, once the Stop condition is received, an internal write cycle will begin (Figure6-2). If an attempt is made to write to the array with the WP pin held high, the device will acknowledge the command, but no write cycle will occur, no data will be written and the device will immediately accept a new command. Preliminary DS21941E-page 8 © 2007 Microchip Technology Inc.

24AA1025/24LC1025/24FC1025 FIGURE 6-1: BYTE WRITE S BUS ACTIVITY T S Control Address Address MASTER A T R Byte High Byte Low Byte Data O T P SDA LINE S1 0 1 0B0 A1A0 0 P A A A A BUS ACTIVITY C C C C K K K K X = “don’t care” bit FIGURE 6-2: PAGE WRITE S T S BUS ACTIVITY A Control Address Address T MASTER R Byte High Byte Low Byte Data Byte 0 Data Byte 127 O T P SDA LINE S10 1 0B0A1A0 0 P A A A A A BUS ACTIVITY C C C C C K K K K K X = “don’t care” bit Preliminary © 2007 Microchip Technology Inc. DS21941E-page 9

24AA1025/24LC1025/24FC1025 7.0 ACKNOWLEDGE POLLING FIGURE 7-1: ACKNOWLEDGE POLLING FLOW Since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete. (This feature can be used to maximize bus throughput.) Once the Stop condition for a Write Send command has been issued from the master, the device Write Command initiates the internally timed write cycle. ACK polling can be initiated immediately. This involves the master sending a Start condition, followed by the control byte for a Write command (R/W = 0). If the device is still Send Stop busy with the write cycle, then no ACK will be returned. Condition to If no ACK is returned, then the Start bit and control byte Initiate Write Cycle must be resent. If the cycle is complete, then the device will return the ACK and the master can then proceed with the next Read or Write command. See Figure7-1 Send Start for flow diagram. Note: Care must be taken when polling the 24XX1025. The control byte that was used Send Control Byte to initiate the write needs to match the with R/W = 0 control byte used for polling. Did Device No Acknowledge (ACK = 0)? Yes Next Operation Preliminary DS21941E-page 10 © 2007 Microchip Technology Inc.

24AA1025/24LC1025/24FC1025 8.0 READ OPERATION 8.2 Random Read Read operations are initiated in the same way as write Random read operations allow the master to access operations with the exception that the R/W bit of the any memory location in a random manner. To perform control byte is set to one. There are three basic types this type of read operation, first the word address must of read operations: current address read, random read, be set. This is done by sending the word address to the and sequential read. 24XX1025 as part of a write operation (R/W bit set to 0). After the word address is sent, the master gener- 8.1 Current Address Read ates a Start condition following the acknowledge. This terminates the write operation, but not before the inter- The 24XX1025 contains an address counter that main- nal Address Pointer is set. Then, the master issues the tains the address of the last word accessed, internally control byte again, but with the R/W bit set to a one. incremented by one. Therefore, if the previous read The 24XX1025 will then issue an acknowledge and access was to address n (n is any legal address), the transmit the 8-bit data word. The master will not next current address read operation would access data acknowledge the transfer, but does generate a Stop from address n + 1. condition which causes the 24XX1025 to discontinue Upon receipt of the control byte with R/W bit set to one, transmission (Figure8-2). After a random Read the 24XX1025 issues an acknowledge and transmits command, the internal address counter will point to the the 8-bit data word. The master will not acknowledge address location following the one that was just read. the transfer, but does generate a Stop condition and the 24XX1025 discontinues transmission (Figure8-1). 8.3 Sequential Read Sequential reads are initiated in the same way as a FIGURE 8-1: CURRENT ADDRESS random read except that after the 24XX1025 transmits READ the first data byte, the master issues an acknowledge as opposed to the Stop condition used in a random S T S read. This acknowledge directs the 24XX1025 to trans- BUS ACTIVITY A Control Data T MASTER R Byte Byte O mit the next sequentially addressed 8-bit word T P (Figure8-3). Following the final byte transmitted to the SDA LINE S 1 0 1 0 B AA 1 P master, the master will NOT generate an acknowledge, 0 1 0 but will generate a Stop condition. To provide sequen- A N BUS ACTIVITY C O tial reads, the 24XX1025 contains an internal Address K A Pointer which is incremented by one at the completion C of each operation. This Address Pointer allows half the K memory contents to be serially read during one opera- tion. Sequential read address boundaries are 0000h to FFFFh and 10000h to 1FFFFh. The internal Address Pointer will automatically roll over from address FFFF to address 0000 if the master acknowledges the byte received from the array address, 1FFFF. The internal address counter will automatically roll over from address 1FFFFh to address 10000h if the master acknowledges the byte received from the array address, 1FFFFh. Preliminary © 2007 Microchip Technology Inc. DS21941E-page 11

24AA1025/24LC1025/24FC1025 FIGURE 8-2: RANDOM READ S S BUS ACTIVITY T T S Control Address Address Control Data MASTER A A T R Byte High Byte Low Byte R Byte Byte O T T P SDA LINE S 1 0 1 0 B A A 0 S 1 0 1 0 B A A1 P 0 1 0 0 1 0 A A A A N BUS ACTIVITY C C C C O K K K K A C K FIGURE 8-3: SEQUENTIAL READ Control S BUS ACTIVITY T MASTER Byte Data n Data n + 1 Data n + 2 Data n + X O P SDA LINE P A A A A N C C C C O BUS ACTIVITY K K K K A C K Preliminary DS21941E-page 12 © 2007 Microchip Technology Inc.

24AA1025/24LC1025/24FC1025 9.0 PACKAGING INFORMATION 9.1 Package Marking Information 8-Lead PDIP (300 mil) Example: XXXXXXXX 24LC1025 TXXXXNNN I/P e 3 13F YYWW 0601 8-Lead SOIJ (5.28 mm) Example: XXXXXXXX 24LC1025 TXXXXXXX I/SMe3 YYWWNNN 0510 13F Legend: XX...X Part number or part number code T Temperature (I, E) Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code (2 characters for small packages) e3 Pb-free JEDEC designator for Matte Tin (Sn) Note: For very small packages with no room for the Pb-free JEDEC designator e 3 , the marking will only appear on the outer carton or reel label. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. * Standard marking consists of Microchip part number, year code, week code, traceability code (facility code, mask rev#, and assembly code). For marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. Preliminary © 2007 Microchip Technology Inc. DS21941E-page 13

24AA1025/24LC1025/24FC1025 8-Lead Plastic Dual In-Line (P or PA) – 300 mil Body [PDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging N NOTE 1 E1 1 2 3 D E A A2 L A1 c e eB b1 b Units INCHES Dimension Limits MIN NOM MAX Number of Pins N 8 Pitch e .100 BSC Top to Seating Plane A – – .210 Molded Package Thickness A2 .115 .130 .195 Base to Seating Plane A1 .015 – – Shoulder to Shoulder Width E .290 .310 .325 Molded Package Width E1 .240 .250 .280 Overall Length D .348 .365 .400 Tip to Seating Plane L .115 .130 .150 Lead Thickness c .008 .010 .015 Upper Lead Width b1 .040 .060 .070 Lower Lead Width b .014 .018 .022 Overall Row Spacing § eB – – .430 Notes: 1. Pin 1 visual index feature may vary, but must be located with the hatched area. 2. § Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. MicrochipTechnologyDrawingC04-018B Preliminary DS21941E-page 14 © 2007 Microchip Technology Inc.

24AA1025/24LC1025/24FC1025 8-Lead Plastic Small Outline (SM) – Medium, 5.28 mm Body [SOIJ] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D N E E1 1 2 e b α c φ A A2 β A1 L Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Pins N 8 Pitch e 1.27 BSC Overall Height A 1.77 – 2.03 Molded Package Thickness A2 1.75 – 1.98 Standoff § A1 0.05 – 0.25 Overall Width E 7.62 – 8.26 Molded Package Width E1 5.11 – 5.38 Overall Length D 5.13 – 5.33 Foot Length L 0.51 – 0.76 Foot Angle φ 0° – 8° Lead Thickness c 0.15 – 0.25 Lead Width b 0.36 – 0.51 Mold Draft Angle Top α – – 15° Mold Draft Angle Bottom β – – 15° Notes: 1. SOIJ, JEITA/EIAJ Standard, formerly called SOIC. 2. § Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25 mm per side. MicrochipTechnologyDrawingC04-056B Preliminary © 2007 Microchip Technology Inc. DS21941E-page 15

24AA1025/24LC1025/24FC1025 APPENDIX A: REVISION HISTORY Revision A Original release. Revision B Section 1.0 Electrical Characteristics: revised Ambient Temperature; Revised Table 1-1; Revised Section 2.1 and Section 2.5. Revision C Revised Features, Maximum Read Current and Table 1-1, D9; Revised Table 2-1, VCC; Revised Section 6.3. Revision D (01/2007) Revised Device Selection Table; Features Section; Changed 1.8V to 1.7V; Revised Tables 1-1, 1-2, 2-1; Revised Product ID System; Replaced Package Drawings. Revision E (03/2007) Replaced Package Drawings (Rev. AM). Preliminary DS21941E-page 16 © 2007 Microchip Technology Inc.

24AA1025/24LC1025/24FC1025 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at Users of Microchip products can receive assistance www.microchip.com. This web site is used as a means through several channels: to make files and information easily available to (cid:129) Distributor or Representative customers. Accessible by using your favorite Internet (cid:129) Local Sales Office browser, the web site contains the following (cid:129) Field Application Engineer (FAE) information: (cid:129) Technical Support (cid:129) Product Support – Data sheets and errata, (cid:129) Development Systems Information Line application notes and sample programs, design resources, user’s guides and hardware support Customers should contact their distributor, documents, latest software releases and archived representative or field application engineer (FAE) for software support. Local sales offices are also available to help (cid:129) General Technical Support – Frequently Asked customers. A listing of sales offices and locations is Questions (FAQ), technical support requests, included in the back of this document. online discussion groups, Microchip consultant Technical support is available through the web site program member listing at: http://support.microchip.com (cid:129) Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions. Preliminary © 2007 Microchip Technology Inc. DS21941E-page 17

24AA1025/24LC1025/24FC1025 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod- uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: Technical Publications Manager Total Pages Sent ________ RE: Reader Response From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y N Device: 24AA1025/24LC1025/24FC1025 Literature Number: DS21941E Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? Preliminary DS21941E-page 18 © 2007 Microchip Technology Inc.

24AA1025/24LC1025/24FC1025 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX Examples: Device Temperature Package a) 24AA1025T-I/SM: Tape and Reel, Industrial Range Temperature, SOIJ package. b) 24LC1025-I/P: Industrial Temperature, PDIP package. Device: 24AA1025: = 1024K Bit 1.7V I2C CMOS Serial EEPROM c) 24LC1025-E/SM: Extended Temperature, 24AA1025T:= 1024K Bit 1.7V I2C CMOS Serial EEPROM SOIJ package. (Tape and Reel) 24LC1025: = 1024K Bit 2.5V I2C CMOS Serial EEPROM d) 24LC1025T-I/SM: Tape and Reel, Industrial 24LC1025T:= 1024K Bit 2.5V I2C CMOS Serial EEPROM Temperature, SOIJ package. (Tape and Reel) 24FC1025: = 1024K Bit 2.5V I2C CMOS Serial EEPROM 24FC1025T:= 1024K Bit 2.5V I2C CMOS Serial EEPROM (Tape and Reel) Temperature I = -40°C to +85°C Range: E = -40°C to +125°C Package: P = Plastic DIP (300 mil Body), 8-lead SM = Plastic SOIJ (5.28 mm Body), 8-lead Preliminary © 2007 Microchip Technology Inc. DS21941E-page 19

24AA1025/24LC1025/24FC1025 NOTES: Preliminary DS21941E-page 20 © 2007 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices: (cid:129) Microchip products meet the specification contained in their particular Microchip Data Sheet. (cid:129) Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. (cid:129) There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. (cid:129) Microchip is willing to work with the customer who is concerned about the integrity of their code. (cid:129) Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, Accuron, and may be superseded by updates. It is your responsibility to dsPIC, KEELOQ, KEELOQ logo, microID, MPLAB, PIC, ensure that your application meets with your specifications. PICmicro, PICSTART, PROMATE, PowerSmart, rfPIC, and MICROCHIP MAKES NO REPRESENTATIONS OR SmartShunt are registered trademarks of Microchip WARRANTIES OF ANY KIND WHETHER EXPRESS OR Technology Incorporated in the U.S.A. and other countries. IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, AmpLab, FilterLab, Linear Active Thermistor, Migratable INCLUDING BUT NOT LIMITED TO ITS CONDITION, Memory, MXDEV, MXLAB, PS logo, SEEVAL, SmartSensor QUALITY, PERFORMANCE, MERCHANTABILITY OR and The Embedded Control Solutions Company are FITNESS FOR PURPOSE. Microchip disclaims all liability registered trademarks of Microchip Technology Incorporated arising from this information and its use. Use of Microchip in the U.S.A. devices in life support and/or safety applications is entirely at Analog-for-the-Digital Age, Application Maestro, CodeGuard, the buyer’s risk, and the buyer agrees to defend, indemnify and dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, hold harmless Microchip from any and all damages, claims, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, suits, or expenses resulting from such use. No licenses are In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, conveyed, implicitly or otherwise, under any Microchip MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit, intellectual property rights. PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2007, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona, Gresham, Oregon and Mountain View, California. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. Preliminary © 2007 Microchip Technology Inc. DS21941E-page 21

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Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: M icrochip: 24AA1025-I/P 24AA1025-I/SM 24AA1025T-I/SM 24FC1025-I/P 24FC1025-I/SM 24FC1025T-I/SM 24LC1025-E/P 24LC1025-E/SM 24LC1025-I/P 24LC1025-I/SM 24LC1025T-E/SM 24LC1025T-I/SM