24AA256/24LC256/24FC256 2 256K I C™ CMOS Serial EEPROM Device Selection Table • Temperature Ranges: - Industrial (I): -40C to +85C Part VCC Max. Clock Temp. - Automotive (E): -40C to +125C Number Range Frequency Ranges 24AA256 1.7-5.5V 400kHz(1) I, E Description: 24LC256 2.5-5.5V 400kHz I, E The Microchip Technology Inc. 24AA256/24LC256/ 24FC256 1.7-5.5V 1MHz(2) I 24FC256 (24XX256*) is a 32K x 8 (256 Kbit) Serial Electrically Erasable PROM, capable of operation Note 1: 100kHz for VCC < 2.5V. across a broad voltage range (1.7V to 5.5V). It has 2: 400kHz for VCC < 2.5V. been developed for advanced, low-power applications such as personal communications or data acquisition. Features: This device also has a page write capability of up to 64 • Single Supply with Operation Down to 1.7V for bytes of data. This device is capable of both random 24AA256 and 24FC256 Devices, 2.5V for and sequential reads up to the 256K boundary. 24LC256 Devices Functional address lines allow up to eight devices on • Low-Power CMOS Technology: the same bus, for up to 2Mbit address space. This device is available in the standard 8-pin plastic DIP, - Read current: 400 uA max. at 5.5V, 400 kHz SOIC, SOIJ, TSSOP, MSOP, DFN and TDFN pack- - Standby current: 1uA max. at 3.6V, I-temp ages. The 24AA256 is also available in the 8-lead Chip • 2-Wire Serial Interface, I2C™ Compatible Scale package. • Cascadable up to Eight Devices Block Diagram • Schmitt Trigger Inputs for Noise Suppression • Output Slope Control to Eliminate Ground Bounce A0A1A2WP HV Generator • 100 kHz and 400 kHz Clock Compatibility • Page Write Time 5 ms Max. • Self-Timed Erase/Write Cycle I/O Memory EEPROM • 64-Byte Page Write Buffer Control Control XDEC Array Logic Logic • Hardware Write-Protect Page Latches • ESD Protection >4000V • More than One Million Erase/Write Cycles I/O SCL • Data Retention >200 years YDEC • Factory Programming Available SDA • Packages Include 8-lead PDIP, SOIC, SOIJ, DFN, TDFN, TSSOP and MSOP VCC • RoHS Compliant VSS Sense Amp. R/W Control Package Types PDIP/SOIC/SOIJ TSSOP/MSOP(1) DFN/TDFN CS (Chip Scale)(2) A0 1 8 VCC A0 1 8 VCC A0 1 8 VCC VCC A1 A0 1 2 3 AA12 23 24XX256 76 WSCPL AA12 23 24XX256 76 WSCPL VAAS12S 432 24XX256 567 WSSCDPLA WP SD6A4S7CL5 8VSS A2 VSS 4 5 SDA VSS 4 5 SDA (TOP DOWN VIEW, BALLS NOT VISIBLE) Note 1: * Pins A0 and A1 are no connects for the MSOP package only. Note 2: Available in I-temp, “AA” only. *24XX256 is used in this document as a generic part number for the 24AA256/24LC256/24FC256 devices.  1998-2013 Microchip Technology Inc. DS20001203U-page 1

24AA256/24LC256/24FC256 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings(†) VCC.............................................................................................................................................................................6.5V All inputs and outputs w.r.t. VSS.........................................................................................................-0.6V to VCC +1.0V Storage temperature...............................................................................................................................-65°C to +150°C Ambient temperature with power applied................................................................................................-40°C to +125°C ESD protection on all pins 4kV † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. TABLE 1-1: DC CHARACTERISTICS Electrical Characteristics: DC CHARACTERISTICS Industrial (I): VCC = +1.7V to 5.5V TA = -40°C to +85°C Automotive (E): VCC = +1.7V to 5.5V TA = -40°C to +125°C Param. Sym. Characteristic Min. Max. Units Conditions No. — A0, A1, A2, SCL, SDA — — — — and WP pins: D1 VIH High-level input voltage 0.7 VCC — V — D2 VIL Low-level input voltage — 0.3 VCC V VCC  2.5V 0.2 VCC V VCC < 2.5V D3 VHYS Hysteresis of Schmitt 0.05 VCC — V VCC  2.5V (Note) Trigger inputs (SDA, SCL pins) D4 VOL Low-level output voltage — 0.40 V IOL = 3.0mA @ VCC = 4.5V IOL = 2.1mA @ VCC = 2.5V D5 ILI Input leakage current — ±1 A VIN = VSS or VCC, WP = VSS VIN = VSS or VCC, WP = VCC D6 ILO Output leakage current — ±1 A VOUT = VSS or VCC D7 CIN, Pin capacitance — 10 pF VCC = 5.0V (Note) COUT (all inputs/outputs) TA = 25°C, FCLK = 1MHz D8 ICC Read Operating current — 400 A VCC = 5.5V, SCL = 400kHz ICC Write — 3 mA VCC = 5.5V D9 ICCS Standby current — 1.5 A TA = -40°C to +85°C SCL = SDA = VCC = 5.5V A0, A1, A2, WP = VSS — 1 A TA = -40°C to +85°C SCL = SDA = VCC = 3.6V A0, A1, A2, WP = VSS — 5 A TA = -40°C to +125°C SCL = SDA = VCC = 5.5V A0, A1, A2, WP = VSS Note: This parameter is periodically sampled and not 100% tested. DS20001203U-page 2  1998-2013 Microchip Technology Inc.

24AA256/24LC256/24FC256 TABLE 1-2: AC CHARACTERISTICS Electrical Characteristics: AC CHARACTERISTICS Industrial (I): VCC = +1.7V to 5.5V TA = -40°C to +85°C Automotive (E): VCC = +1.7V to 5.5V TA = -40°C to +125°C Param. Sym. Characteristic Min. Max. Units Conditions No. 1 FCLK Clock frequency — 100 kHz 1.7V  VCC  2.5V — 400 2.5V  VCC  5.5V — 400 1.7V  VCC  2.5V 24FC256 — 1000 2.5V  VCC  5.5V 24FC256 2 THIGH Clock high time 4000 — ns 1.7V  VCC  2.5V 600 — 2.5V  VCC  5.5V 600 — 1.7V  VCC  2.5V 24FC256 500 — 2.5V  VCC  5.5V 24FC256 3 TLOW Clock low time 4700 — ns 1.7V  VCC  2.5V 1300 — 2.5V  VCC  5.5V 1300 — 1.7V  VCC  2.5V 24FC256 500 — 2.5V  VCC  5.5V 24FC256 4 TR SDA and SCL rise time — 1000 ns 1.7V  VCC  2.5V (Note1) — 300 2.5V  VCC  5.5V — 300 1.7V  VCC  5.5V 24FC256 5 TF SDA and SCL fall time — 300 ns All except, 24FC256 (Note1) — 100 1.7V  VCC  5.5V 24FC256 6 THD:STA Start condition hold time 4000 — ns 1.7V  VCC  2.5V 600 — 2.5V  VCC  5.5V 600 — 1.7V  VCC  2.5V 24FC256 250 — 2.5V  VCC  5.5V 24FC256 7 TSU:STA Start condition setup time 4700 — ns 1.7V  VCC  2.5V 600 — 2.5V  VCC  5.5V 600 — 1.7V  VCC  2.5V 24FC256 250 — 2.5V  VCC  5.5V 24FC256 8 THD:DAT Data input hold time 0 — ns (Note2) 9 TSU:DAT Data input setup time 250 — ns 1.7V  VCC  2.5V 100 — 2.5V  VCC  5.5V 100 — 1.7V  VCC  5.5V 24FC256 10 TSU:STO Stop condition setup time 4000 — ns 1.7V  VCC  2.5V 600 — 2.5V  VCC  5.5V 600 — 1.7V  VCC  2.5V 24FC256 250 — 2.5V  VCC  5.5V 24FC256 11 TSU:WP WP setup time 4000 — ns 1.7V  VCC  2.5V 600 — 2.5V  VCC  5.5V 600 — 1.7V  VCC  5.5V 24FC256 12 THD:WP WP hold time 4700 — ns 1.7V  VCC  2.5V 1300 — 2.5V  VCC  5.5V 1300 — 1.7V  VCC  5.5V 24FC256 Note 1: Not 100% tested. CB = total capacitance of one bus line in pF. 2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. 3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs, which provide improved noise spike suppression. This eliminates the need for a TI specification for standard operation. 4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total Endurance™ Model, which can be obtained from Microchip’s web site at www.microchip.com.  1998-2013 Microchip Technology Inc. DS20001203U-page 3

24AA256/24LC256/24FC256 Electrical Characteristics: AC CHARACTERISTICS (Continued) Industrial (I): VCC = +1.7V to 5.5V TA = -40°C to +85°C Automotive (E): VCC = +1.7V to 5.5V TA = -40°C to +125°C Param. Sym. Characteristic Min. Max. Units Conditions No. 13 TAA Output valid from clock — 3500 ns 1.7V  VCC  2.5V (Note2) — 900 2.5V  VCC  5.5V — 900 1.7V  VCC  2.5V 24FC256 — 400 2.5V  VCC  5.5V 24FC256 14 TBUF Bus free time: Time the bus 4700 — ns 1.7V  VCC  2.5V must be free before a new 1300 — 2.5V  VCC  5.5V transmission can start 1300 — 1.7V  VCC  2.5V 24FC256 500 — 2.5V  VCC  5.5V 24FC256 15 TOF Output fall time from VIH 10 + 0.1CB 250 ns All except, 24FC256 (Note1) minimum to VIL maximum 250 CB  100pF 16 TSP Input filter spike suppression — 50 ns All except, 24FC256 (Notes1 (SDA and SCL pins) and3) 17 TWC Write cycle time (byte or — 5 ms — page) 18 — Endurance 1,000,000 — cycles Page mode, 25°C, 5.5V (Note4) Note 1: Not 100% tested. CB = total capacitance of one bus line in pF. 2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. 3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs, which provide improved noise spike suppression. This eliminates the need for a TI specification for standard operation. 4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total Endurance™ Model, which can be obtained from Microchip’s web site at www.microchip.com. FIGURE 1-1: BUS TIMING DATA 5 4 2 D3 SCL 7 3 8 9 10 SDA 6 IN 16 13 14 SDA OUT (protected) WP 11 12 (unprotected) DS20001203U-page 4  1998-2013 Microchip Technology Inc.

24AA256/24LC256/24FC256 2.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table2-1. TABLE 2-1: PIN FUNCTION TABLE Name PDIP SOIC SOIJ TSSOP MSOP DFN TDFN CS Function A0 1 1 1 1 — 1 1 3 User Configurable Chip Select A1 2 2 2 2 — 2 2 2 User Configurable Chip Select (NC) — — — — 1, 2 — — — Not Connected A2 3 3 3 3 3 3 3 5 User Configurable Chip Select VSS 4 4 4 4 4 4 4 8 Ground SDA 5 5 5 5 5 5 5 6 Serial Data SCL 6 6 6 6 6 6 6 7 Serial Clock WP 7 7 7 7 7 7 7 4 Write-Protect Input VCC 8 8 8 8 8 8 8 1 +1.7V to 5.5V (24AA256) +2.5V to 5.5V (24LC256) +1.7V to 5.5V (24FC256) Note: Exposed pad on DFN/TDFN can be connected to VSS or left floating. 2.1 A0, A1, A2 Chip Address Inputs 2.3 Serial Clock (SCL) The A0, A1 and A2 inputs are used by the 24XX256 for This input is used to synchronize the data transfer to multiple device operations. The levels on these inputs and from the device. are compared with the corresponding bits in the slave address. The chip is selected if the compare is true. 2.4 Write-Protect (WP) For the MSOP package only, pins A0 and A1 are not This pin must be connected to either VSS or VCC. If tied connected. to VSS, write operations are enabled. If tied to VCC, Up to eight devices (two for the MSOP package) may write operations are inhibited but read operations are be connected to the same bus by using different Chip not affected. Select bit combinations. These inputs must be connected to either VCC or VSS. 3.0 FUNCTIONAL DESCRIPTION In most applications, the chip address inputs A0, A1 and A2 are hard-wired to logic ‘0’ or logic ‘1’. For The 24XX256 supports a bidirectional 2-wire bus and applications in which these pins are controlled by a data transmission protocol. A device that sends data microcontroller or other programmable device, the chip onto the bus is defined as a transmitter and a device address pins must be driven to logic ‘0’ or logic ‘1’ receiving data as a receiver. The bus must be before normal device operation can proceed. controlled by a master device which generates the Serial Clock (SCL), controls the bus access, and 2.2 Serial Data (SDA) generates the Start and Stop conditions while the 24XX256 works as a slave. Both master and slave can This is a bidirectional pin used to transfer addresses operate as a transmitter or receiver, but the master and data into and out of the device. It is an open drain device determines which mode is activated. terminal. Therefore, the SDA bus requires a pull-up resistor to VCC (typical 10k for 100kHz, 2kfor 400kHz and 1MHz). For normal data transfer, SDA is allowed to change only during SCL low. Changes during SCL high are reserved for indicating the Start and Stop conditions.  1998-2013 Microchip Technology Inc. DS20001203U-page 5

24AA256/24LC256/24FC256 4.0 BUS CHARACTERISTICS 4.4 Data Valid (D) The following bus protocol has been defined: The state of the data line represents valid data when, after a Start condition, the data line is stable for the • Data transfer may be initiated only when the bus duration of the high period of the clock signal. is not busy. • During data transfer, the data line must remain The data on the line must be changed during the low stable whenever the clock line is high. Changes in period of the clock signal. There is one bit of data per the data line, while the clock line is high, will be clock pulse. interpreted as a Start or Stop condition. Each data transfer is initiated with a Start condition and Accordingly, the following bus conditions have been terminated with a Stop condition. The number of the defined (Figure4-1). data bytes transferred between the Start and Stop conditions is determined by the master device. 4.1 Bus Not Busy (A) 4.5 Acknowledge Both data and clock lines remain high. Each receiving device, when addressed, is obliged to generate an Acknowledge signal after the reception of 4.2 Start Data Transfer (B) each byte. The master device must generate an extra A high-to-low transition of the SDA line while the clock clock pulse which is associated with this Acknowledge (SCL) is high, determines a Start condition. All bit. commands must be preceded by a Start condition. Note: The 24XX256 does not generate any Acknowledge bits if an internal 4.3 Stop Data Transfer (C) programming cycle is in progress. A low-to-high transition of the SDA line, while the clock A device that acknowledges must pull down the SDA (SCL) is high, determines a Stop condition. All line during the acknowledge clock pulse in such a way operations must end with a Stop condition. that the SDA line is stable low during the high period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. During reads, a master must signal an end of data to the slave by NOT generating an Acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave (24XX256) will leave the data line high to enable the master to generate the Stop condition. DS20001203U-page 6  1998-2013 Microchip Technology Inc.

24AA256/24LC256/24FC256 FIGURE 4-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS (A) (B) (D) (D) (C) (A) SCL SDA Start Address or Data Stop Condition Acknowledge Allowed Condition Valid to Change FIGURE 4-2: ACKNOWLEDGE TIMING Acknowledge Bit SCL 1 2 3 4 5 6 7 8 9 1 2 3 SDA Data from transmitter Data from transmitter Transmitter must release the SDA line at this point, Receiver must release the SDA line allowing the Receiver to pull the SDA line low to at this point so the Transmitter can acknowledge the previous eight bits of data. continue sending data.  1998-2013 Microchip Technology Inc. DS20001203U-page 7

24AA256/24LC256/24FC256 5.0 DEVICE ADDRESSING FIGURE 5-1: CONTROL BYTE FORMAT A control byte is the first byte received following the Start condition from the master device (Figure5-1). Read/Write Bit The control byte consists of a 4-bit control code. For the 24XX256, this is set as ‘1010’ binary for read and Chip Select write operations. The next three bits of the control byte Control Code Bits are the Chip Select bits (A2, A1, A0). The Chip Select bits allow the use of up to eight 24XX256 devices on S 1 0 1 0 A2 A1 A0 R/W ACK the same bus and are used to select which device is accessed. The Chip Select bits in the control byte must Slave Address correspond to the logic levels on the corresponding A2, A1 and A0 pins for the device to respond. These bits Start Bit Acknowledge Bit are, in effect, the three Most Significant bits of the word address. For the MSOP package, the A0 and A1 pins are not 5.1 Contiguous Addressing Across connected. During device addressing, the A0 and A1 Multiple Devices Chip Select bits (Figures 5-1 and 5-2) should be set to ‘0’. Only two 24XX256 MSOP packages can be The Chip Select bits A2, A1 and A0 can be used to connected to the same bus. expand the contiguous address space for up to 2Mbit by adding up to eight 24XX256 devices on the same The last bit of the control byte defines the operation to bus. In this case, software can use A0 of the control be performed. When set to a one, a read operation is byte as address bit A15; A1 as address bit A16; and A2 selected. When set to a zero, a write operation is as address bit A17. It is not possible to sequentially selected. The next two bytes received define the read across device boundaries. address of the first data byte (Figure5-2). Because only A14…A0 are used, the upper address bits are a For the MSOP package, up to two 24XX256 devices “don’t care.” The upper address bits are transferred can be added for up to 512Kbit of address space. In first, followed by the Less Significant bits. this case, software can use A2 of the control byte as address bit A17. Bits A0 (A15) and A1 (A16) of the Following the Start condition, the 24XX256 monitors control byte must always be set to a logic ‘0’ for the the SDA bus checking the device type identifier being MSOP. transmitted. Upon receiving a ‘1010’ code and appropriate device select bits, the slave device outputs an Acknowledge signal on the SDA line. Depending on the state of the R/W bit, the 24XX256 will select a read or write operation. FIGURE 5-2: ADDRESS SEQUENCE BIT ASSIGNMENTS Control Byte Address High Byte Address Low Byte A A A A A A A A A A A A 1 0 1 0 2 1 0 R/W x 14 13 12 11 10 9 8 7 • • • • • • 0 Control Chip x = “don’t care” bit Code Select Bits DS20001203U-page 8  1998-2013 Microchip Technology Inc.

24AA256/24LC256/24FC256 6.0 WRITE OPERATIONS 6.3 Write Protection The WP pin allows the user to write-protect the entire 6.1 Byte Write array (0000-7FFF) when the pin is tied to VCC. If tied to Following the Start condition from the master, the VSS the write protection is disabled. The WP pin is sampled at the Stop bit for every Write command control code (four bits), the Chip Select (three bits) and (Figure1-1). Toggling the WP pin after the Stop bit will the R/W bit (which is a logic low) are clocked onto the have no effect on the execution of the write cycle. bus by the master transmitter. This indicates to the addressed slave receiver that the address high byte will Note: Page write operations are limited to follow after it has generated an Acknowledge bit during writing bytes within a single physical page, the ninth clock cycle. Therefore, the next byte regardless of the number of bytes transmitted by the master is the high-order byte of the actually being written. Physical page word address and will be written into the Address boundaries start at addresses that are Pointer of the 24XX256. The next byte is the Least integer multiples of the page buffer size Significant Address Byte. After receiving another (or ‘page size’) and end at addresses that Acknowledge signal from the 24XX256, the master are integer multiples of [page size – 1]. If device will transmit the data word to be written into the a Page Write command attempts to write addressed memory location. The 24XX256 acknowl- across a physical page boundary, the edges again and the master generates a Stop result is that the data wraps around to the condition. This initiates the internal write cycle and beginning of the current page (overwriting during this time, the 24XX256 will not generate data previously stored there), instead of Acknowledge signals (Figure6-1). If an attempt is being written to the next page, as might be made to write to the array with the WP pin held high, the expected. It is, therefore, necessary for device will acknowledge the command but no write the application software to prevent page cycle will occur, no data will be written, and the device write operations that would attempt to will immediately accept a new command. After a byte cross a page boundary. Write command, the internal address counter will point to the address location following the one that was just written. Note: When doing a write of less than 64 bytes the data in the rest of the page is refreshed along with the data bytes being written. This will force the entire page to endure a write cycle, for this reason endurance is specified per page. 6.2 Page Write The write control byte, word address and the first data byte are transmitted to the 24XX256 in much the same way as in a byte write. The exception is that instead of generating a Stop condition, the master transmits up to 63 additional bytes, which are temporarily stored in the on-chip page buffer, and will be written into memory once the master has transmitted a Stop condition. Upon receipt of each word, the six lower Address Pointer bits are internally incremented by one. If the master should transmit more than 64 bytes prior to generating the Stop condition, the address counter will roll over and the previously received data will be over- written. As with the byte write operation, once the Stop condition is received, an internal write cycle will begin (Figure6-2). If an attempt is made to write to the array with the WP pin held high, the device will acknowledge the command, but no write cycle will occur, no data will be written and the device will immediately accept a new command.  1998-2013 Microchip Technology Inc. DS20001203U-page 9

24AA256/24LC256/24FC256 FIGURE 6-1: BYTE WRITE S Bus Activity T S Control Address Address Master A T R Byte High Byte Low Byte Data O SDA Line T P AAA S1 0 1 0 2 1 0 0 x P Bus Activity A A A A x = “don’t care” bit C C C C K K K K FIGURE 6-2: PAGE WRITE S Bus Activity T S Master A Control Address Address T R Byte High Byte Low Byte Data Byte 0 Data Byte 63 O T P SDA Line AAA S10 1 0 2 1 0 0 x P Bus Activity A A A A A C C C C C x = “don’t care” bit K K K K K DS20001203U-page 10  1998-2013 Microchip Technology Inc.

24AA256/24LC256/24FC256 7.0 ACKNOWLEDGE POLLING FIGURE 7-1: ACKNOWLEDGE POLLING FLOW Since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (This feature can be used to maximize bus throughput). Once the Stop condition for a Write Send command has been issued from the master, the device Write Command initiates the internally timed write cycle. ACK polling can be initiated immediately. This involves the master sending a Start condition, followed by the control byte Send Stop for a Write command (R/W = 0). If the device is still Condition to busy with the write cycle, then no ACK will be returned. Initiate Write Cycle If no ACK is returned, the Start bit and control byte must be resent. If the cycle is complete, then the device will return the ACK and the master can then proceed with the next Read or Write command. See Figure7-1 for Send Start flow diagram. Send Control Byte with R/W = 0 Did Device NO Acknowledge (ACK = 0)? YES Next Operation  1998-2013 Microchip Technology Inc. DS20001203U-page 11

24AA256/24LC256/24FC256 8.0 READ OPERATION 8.2 Random Read Read operations are initiated in much the same way as Random read operations allow the master to access write operations, with the exception that the R/W bit of any memory location in a random manner. To perform the control byte is set to ‘1’. There are three basic types this type of read operation, the word address must first of read operations: current address read, random read be set. This is done by sending the word address to the and sequential read. 24XX256 as part of a write operation (R/W bit set to ‘0’). Once the word address is sent, the master gener- 8.1 Current Address Read ates a Start condition following the acknowledge. This terminates the write operation, but not before the The 24XX256 contains an address counter that main- internal Address Pointer is set. The master then issues tains the address of the last word accessed, internally the control byte again, but with the R/W bit set to a one. incremented by ‘1’. Therefore, if the previous read The 24XX256 will then issue an acknowledge and access was to address ‘n’ (n is any legal address), the transmit the 8-bit data word. The master will not next current address read operation would access data acknowledge the transfer, though it does generate a from address n + 1. Stop condition, which causes the 24XX256 to discon- Upon receipt of the control byte with R/W bit set to ‘1’, tinue transmission (Figure8-2). After a random Read the 24XX256 issues an acknowledge and transmits the command, the internal address counter will point to the 8-bit data word. The master will not acknowledge the address location following the one that was just read. transfer, but does generate a Stop condition and the 24XX256 discontinues transmission (Figure8-1). 8.3 Sequential Read Sequential reads are initiated in the same way as a FIGURE 8-1: CURRENT ADDRESS random read except that after the 24XX256 transmits READ the first data byte, the master issues an acknowledge S as opposed to the Stop condition used in a random Bus Activity TA Control Data ST read. This acknowledge directs the 24XX256 to Master R Byte Byte O transmit the next sequentially addressed 8-bit word T P (Figure8-3). Following the final byte transmitted to the SDA Line A AA S 1 0 1 0 1 P master, the master will NOT generate an acknowledge, 2 1 0 A N but will generate a Stop condition. To provide sequen- Bus Activity C O tial reads, the 24XX256 contains an internal Address K A Pointer which is incremented by one at the completion C of each operation. This Address Pointer allows the K entire memory contents to be serially read during one operation. The internal Address Pointer will automatically roll over from address 7FFF to address 0000 if the master acknowledges the byte received from the array address 7FFF. FIGURE 8-2: RANDOM READ S S Bus Activity T T S Control Address Address Control Data Master A A T R Byte High Byte Low Byte R Byte Byte O T T P SDA Line S1 0 1 0 AAA0 x S1 0 1 0 AAA1 P 2 1 0 2 1 0 A A A A N Bus Activity C C C C O K K K K A x = “don’t care” bit C K DS20001203U-page 12  1998-2013 Microchip Technology Inc.

24AA256/24LC256/24FC256 FIGURE 8-3: SEQUENTIAL READ Control S Bus Activity T Master Byte Data (n) Data (n + 1) Data (n + 2) Data (n + x) O P SDA Line P A A A A N C C C C O Bus Activity K K K K A C K  1998-2013 Microchip Technology Inc. DS20001203U-page 13

24AA256/24LC256/24FC256 9.0 PACKAGING INFORMATION 9.1 Package Marking Information 8-Lead PDIP (300 mil) Example: XXXXXXXX 24AA256 T/XXXNNN I/P e 3 017 YYWW 1346 8-Lead SOIC (3.90 mm) Example: XXXXXXXT 24LC256I XXXXYYWW SN e 3 1346 NNN 017 8-Lead SOIJ (5.28 mm) Example: XXXXXXXX 24LC256 T/XXXXXX I/SM e3 YYWWNNN 1346017 Legend: XX...X Part number or part number code T Temperature (I, E) Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code (2 characters for small packages) e3 JEDEC® designator for Matte Tin (Sn) Note: For very small packages with no room for the JEDEC designator e3 , the marking will only appear on the outer carton or reel label. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. *Standard device marking consists of Microchip part number, year code, week code, and traceability code. For device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. DS20001203U-page 14  1998-2013 Microchip Technology Inc.

24AA256/24LC256/24FC256 Package Marking Information (Continued) 8-Lead TSSOP Example: XXXX 4LD TYWW I346 NNN 017 8-Lead MSOP Example: XXXXXT 4L256I YWWNNN 346017 8-Lead DFN-S Example: XXXXXXX 24LC256 T/XXXXX I/MFe3 YYWW 1346 017 NNN 8-Lead TDFN Example: XXX EF4 YWW 1346 NN 017 8-Lead Chip Scale Example: XXX 249 XYYW A134 WNNN 6017 First Line Marking Codes Part TDFN No. PDIP SOIC SOIJ TSSOP MSOP DFN CSP I Temp. E Temp. 24AA256 24AA256 24AA256T 24AA256 4AD 4A256T 24AA256 — — 249 24LC256 24LC256 24LC256T 24LC256 4LD 4L256T 24LC256 EF4 — — 24FC256 24FC256 24FC256T 24FC256 4FD 4F256T 24FC256 — — — Note: T = Temperature grade (I, E)  1998-2013 Microchip Technology Inc. DS20001203U-page 15

24AA256/24LC256/24FC256 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)(cid:15)(cid:16)(cid:6)(cid:10)(cid:8)(cid:17)(cid:18)(cid:3)(cid:4)(cid:13)(cid:18)(cid:5)(cid:8)(cid:19)(cid:9)(cid:20)(cid:8)(cid:21)(cid:8)(cid:22)(cid:23)(cid:23)(cid:8)(cid:24)(cid:13)(cid:10)(cid:8)(cid:25)(cid:26)(cid:7)(cid:27)(cid:8)(cid:28)(cid:9)(cid:15)(cid:17)(cid:9)(cid:29) (cid:30)(cid:26)(cid:12)(cid:5)(cid:31) 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) N NOTE1 E1 1 2 3 D E A A2 L A1 c e eB b1 b 6(cid:15)(cid:7)&! (cid:19)7,8.(cid:22) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:2)9(cid:7)’(cid:7)&! (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7"’)(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)(cid:31)(cid:7)(cid:15)! 7 < (cid:31)(cid:7)&(cid:8)(cid:11) (cid:14) (cid:20)(cid:30)(cid:4)(cid:4)(cid:2)1(cid:22), (cid:13)(cid:10)(cid:12)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)&(cid:7)(cid:15)(cid:17)(cid:2)(cid:31)(cid:16)(cid:28)(cid:15)(cid:14) (cid:25) = = (cid:20)(cid:3)(cid:30)(cid:4) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:25)(cid:3) (cid:20)(cid:30)(cid:30)(cid:29) (cid:20)(cid:30)-(cid:4) (cid:20)(cid:30)(cid:24)(cid:29) 1(cid:28)!(cid:14)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)&(cid:7)(cid:15)(cid:17)(cid:2)(cid:31)(cid:16)(cid:28)(cid:15)(cid:14) (cid:25)(cid:30) (cid:20)(cid:4)(cid:30)(cid:29) = = (cid:22)(cid:11)(cid:10)"(cid:16)#(cid:14)(cid:9)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:11)(cid:10)"(cid:16)#(cid:14)(cid:9)(cid:2)>(cid:7)#&(cid:11) . (cid:20)(cid:3)(cid:24)(cid:4) (cid:20)-(cid:30)(cid:4) (cid:20)-(cid:3)(cid:29) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)>(cid:7)#&(cid:11) .(cid:30) (cid:20)(cid:3)(cid:23)(cid:4) (cid:20)(cid:3)(cid:29)(cid:4) (cid:20)(cid:3)<(cid:4) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21) (cid:20)-(cid:23)< (cid:20)-?(cid:29) (cid:20)(cid:23)(cid:4)(cid:4) (cid:13)(cid:7)(cid:12)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)&(cid:7)(cid:15)(cid:17)(cid:2)(cid:31)(cid:16)(cid:28)(cid:15)(cid:14) 9 (cid:20)(cid:30)(cid:30)(cid:29) (cid:20)(cid:30)-(cid:4) (cid:20)(cid:30)(cid:29)(cid:4) 9(cid:14)(cid:28)#(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:8) (cid:20)(cid:4)(cid:4)< (cid:20)(cid:4)(cid:30)(cid:4) (cid:20)(cid:4)(cid:30)(cid:29) 6(cid:12)(cid:12)(cid:14)(cid:9)(cid:2)9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) )(cid:30) (cid:20)(cid:4)(cid:23)(cid:4) (cid:20)(cid:4)?(cid:4) (cid:20)(cid:4)(cid:5)(cid:4) 9(cid:10)*(cid:14)(cid:9)(cid:2)9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) ) (cid:20)(cid:4)(cid:30)(cid:23) (cid:20)(cid:4)(cid:30)< (cid:20)(cid:4)(cid:3)(cid:3) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)(cid:26)(cid:10)*(cid:2)(cid:22)(cid:12)(cid:28)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:2)+ (cid:14)1 = = (cid:20)(cid:23)-(cid:4) (cid:30)(cid:26)(cid:12)(cid:5)(cid:11)(cid:31) (cid:30)(cid:20) (cid:31)(cid:7)(cid:15)(cid:2)(cid:30)(cid:2) (cid:7)!"(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)#(cid:14)$(cid:2)%(cid:14)(cid:28)&"(cid:9)(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)((cid:2))"&(cid:2)’"!&(cid:2))(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)*(cid:7)&(cid:11)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)&(cid:8)(cid:11)(cid:14)#(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) +(cid:2)(cid:22)(cid:7)(cid:17)(cid:15)(cid:7)%(cid:7)(cid:8)(cid:28)(cid:15)&(cid:2),(cid:11)(cid:28)(cid:9)(cid:28)(cid:8)&(cid:14)(cid:9)(cid:7)!&(cid:7)(cid:8)(cid:20) -(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)!(cid:2)(cid:21)(cid:2)(cid:28)(cid:15)#(cid:2).(cid:30)(cid:2)#(cid:10)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)"#(cid:14)(cid:2)’(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:20)(cid:2)(cid:6)(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:2)!(cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:14)$(cid:8)(cid:14)(cid:14)#(cid:2)(cid:20)(cid:4)(cid:30)(cid:4)/(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)!(cid:7)#(cid:14)(cid:20) (cid:23)(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)#(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6).(cid:2)0(cid:30)(cid:23)(cid:20)(cid:29)(cid:6)(cid:20) 1(cid:22),2(cid:2)1(cid:28)!(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)&(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)$(cid:28)(cid:8)&(cid:2) (cid:28)(cid:16)"(cid:14)(cid:2)!(cid:11)(cid:10)*(cid:15)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)!(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17),(cid:4)(cid:23)(cid:27)(cid:4)(cid:30)<1 DS20001203U-page 16  1998-2013 Microchip Technology Inc.

24AA256/24LC256/24FC256 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  1998-2013 Microchip Technology Inc. DS20001203U-page 17

24AA256/24LC256/24FC256 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS20001203U-page 18  1998-2013 Microchip Technology Inc.

24AA256/24LC256/24FC256 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8) (cid:24)(cid:6)(cid:10)(cid:10)(cid:8)!(cid:16)(cid:12)(cid:10)(cid:13)(cid:18)(cid:5)(cid:8)(cid:19) (cid:30)(cid:20)(cid:8)(cid:21)(cid:8)(cid:30)(cid:6)""(cid:26)#$(cid:8)(cid:22)%&(cid:23)(cid:8)(cid:24)(cid:24)(cid:8)(cid:25)(cid:26)(cid:7)(cid:27)(cid:8)(cid:28) !(cid:17)’(cid:29) (cid:30)(cid:26)(cid:12)(cid:5)(cid:31) 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)  1998-2013 Microchip Technology Inc. DS20001203U-page 19

24AA256/24LC256/24FC256 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS20001203U-page 20  1998-2013 Microchip Technology Inc.

24AA256/24LC256/24FC256 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  1998-2013 Microchip Technology Inc. DS20001203U-page 21

24AA256/24LC256/24FC256 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS20001203U-page 22  1998-2013 Microchip Technology Inc.

24AA256/24LC256/24FC256 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)()(cid:13)(cid:18)(cid:8) )"(cid:13)(cid:18)*(cid:8) (cid:24)(cid:6)(cid:10)(cid:10)(cid:8)!(cid:16)(cid:12)(cid:10)(cid:13)(cid:18)(cid:5)(cid:8)(cid:19) ((cid:20)(cid:8)(cid:21)(cid:8)+%+(cid:8)(cid:24)(cid:24)(cid:8)(cid:25)(cid:26)(cid:7)(cid:27)(cid:8)(cid:28)( !(cid:9)(cid:29) (cid:30)(cid:26)(cid:12)(cid:5)(cid:31) 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) D N E E1 NOTE1 1 2 b e c φ A A2 A1 L1 L 6(cid:15)(cid:7)&! (cid:6)(cid:19)99(cid:19)(cid:6).(cid:13).(cid:26)(cid:22) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:2)9(cid:7)’(cid:7)&! (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7"’)(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)(cid:31)(cid:7)(cid:15)! 7 < (cid:31)(cid:7)&(cid:8)(cid:11) (cid:14) (cid:4)(cid:20)?(cid:29)(cid:2)1(cid:22), : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)8(cid:14)(cid:7)(cid:17)(cid:11)& (cid:25) = = (cid:30)(cid:20)(cid:3)(cid:4) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:25)(cid:3) (cid:4)(cid:20)<(cid:4) (cid:30)(cid:20)(cid:4)(cid:4) (cid:30)(cid:20)(cid:4)(cid:29) (cid:22)&(cid:28)(cid:15)#(cid:10)%%(cid:2) (cid:25)(cid:30) (cid:4)(cid:20)(cid:4)(cid:29) = (cid:4)(cid:20)(cid:30)(cid:29) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)>(cid:7)#&(cid:11) . ?(cid:20)(cid:23)(cid:4)(cid:2)1(cid:22), (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)>(cid:7)#&(cid:11) .(cid:30) (cid:23)(cid:20)-(cid:4) (cid:23)(cid:20)(cid:23)(cid:4) (cid:23)(cid:20)(cid:29)(cid:4) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21) (cid:3)(cid:20)(cid:24)(cid:4) -(cid:20)(cid:4)(cid:4) -(cid:20)(cid:30)(cid:4) 3(cid:10)(cid:10)&(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) 9 (cid:4)(cid:20)(cid:23)(cid:29) (cid:4)(cid:20)?(cid:4) (cid:4)(cid:20)(cid:5)(cid:29) 3(cid:10)(cid:10)&(cid:12)(cid:9)(cid:7)(cid:15)& 9(cid:30) (cid:30)(cid:20)(cid:4)(cid:4)(cid:2)(cid:26).3 3(cid:10)(cid:10)&(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14) (cid:3) (cid:4)R = <R 9(cid:14)(cid:28)#(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:8) (cid:4)(cid:20)(cid:4)(cid:24) = (cid:4)(cid:20)(cid:3)(cid:4) 9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) ) (cid:4)(cid:20)(cid:30)(cid:24) = (cid:4)(cid:20)-(cid:4) (cid:30)(cid:26)(cid:12)(cid:5)(cid:11)(cid:31) (cid:30)(cid:20) (cid:31)(cid:7)(cid:15)(cid:2)(cid:30)(cid:2) (cid:7)!"(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)#(cid:14)$(cid:2)%(cid:14)(cid:28)&"(cid:9)(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)((cid:2))"&(cid:2)’"!&(cid:2))(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)*(cid:7)&(cid:11)(cid:7)(cid:15)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)&(cid:8)(cid:11)(cid:14)#(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)!(cid:2)(cid:21)(cid:2)(cid:28)(cid:15)#(cid:2).(cid:30)(cid:2)#(cid:10)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)"#(cid:14)(cid:2)’(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:20)(cid:2)(cid:6)(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:2)!(cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:14)$(cid:8)(cid:14)(cid:14)#(cid:2)(cid:4)(cid:20)(cid:30)(cid:29)(cid:2)’’(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)!(cid:7)#(cid:14)(cid:20) -(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)#(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6).(cid:2)0(cid:30)(cid:23)(cid:20)(cid:29)(cid:6)(cid:20) 1(cid:22),2 1(cid:28)!(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)&(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)$(cid:28)(cid:8)&(cid:2) (cid:28)(cid:16)"(cid:14)(cid:2)!(cid:11)(cid:10)*(cid:15)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)!(cid:20) (cid:26).32 (cid:26)(cid:14)%(cid:14)(cid:9)(cid:14)(cid:15)(cid:8)(cid:14)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)((cid:2)"!"(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)((cid:2)%(cid:10)(cid:9)(cid:2)(cid:7)(cid:15)%(cid:10)(cid:9)’(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:12)"(cid:9)(cid:12)(cid:10)!(cid:14)!(cid:2)(cid:10)(cid:15)(cid:16)(cid:18)(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17),(cid:4)(cid:23)(cid:27)(cid:4)<?1  1998-2013 Microchip Technology Inc. DS20001203U-page 23

24AA256/24LC256/24FC256 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS20001203U-page 24  1998-2013 Microchip Technology Inc.

24AA256/24LC256/24FC256 Note: For the mostcurrent package drawings,please seetheMicrochip Packaging Specification located at http://www.microchip.com/packaging  1998-2013 Microchip Technology Inc. DS20001203U-page 25

24AA256/24LC256/24FC256 Note: For the mostcurrent package drawings,please seetheMicrochip Packaging Specification located at http://www.microchip.com/packaging DS20001203U-page 26  1998-2013 Microchip Technology Inc.

24AA256/24LC256/24FC256 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  1998-2013 Microchip Technology Inc. DS20001203U-page 27

24AA256/24LC256/24FC256 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)(cid:15)(cid:16)(cid:6)(cid:10)(cid:8),(cid:10)(cid:6)(cid:12)$(cid:8)(cid:30)(cid:26)(cid:8)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:6)(cid:14)*(cid:6)-(cid:5)(cid:8)(cid:19).,(cid:20)(cid:8)(cid:21)(cid:8)/01(cid:8)(cid:24)(cid:24)(cid:8)(cid:25)(cid:26)(cid:7)(cid:27)(cid:8)(cid:28)(cid:15),(cid:30)(cid:3) (cid:29) (cid:30)(cid:26)(cid:12)(cid:5)(cid:31) 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) (cid:2) e D L b N N K E E2 EXPOSEDPAD NOTE1 NOTE1 1 2 2 1 D2 TOPVIEW BOTTOMVIEW A A3 A1 NOTE2 6(cid:15)(cid:7)&! (cid:6)(cid:19)99(cid:19)(cid:6).(cid:13).(cid:26)(cid:22) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:2)9(cid:7)’(cid:7)&! (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7"’)(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)(cid:31)(cid:7)(cid:15)! 7 < (cid:31)(cid:7)&(cid:8)(cid:11) (cid:14) (cid:30)(cid:20)(cid:3)(cid:5)(cid:2)1(cid:22), : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)8(cid:14)(cid:7)(cid:17)(cid:11)& (cid:25) (cid:4)(cid:20)<(cid:4) (cid:4)(cid:20)<(cid:29) (cid:30)(cid:20)(cid:4)(cid:4) (cid:22)&(cid:28)(cid:15)#(cid:10)%%(cid:2) (cid:25)(cid:30) (cid:4)(cid:20)(cid:4)(cid:4) (cid:4)(cid:20)(cid:4)(cid:30) (cid:4)(cid:20)(cid:4)(cid:29) ,(cid:10)(cid:15)&(cid:28)(cid:8)&(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:25)- (cid:4)(cid:20)(cid:3)(cid:4)(cid:2)(cid:26).3 : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21) (cid:29)(cid:20)(cid:4)(cid:4)(cid:2)1(cid:22), : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)>(cid:7)#&(cid:11) . ?(cid:20)(cid:4)(cid:4)(cid:2)1(cid:22), .$(cid:12)(cid:10)!(cid:14)#(cid:2)(cid:31)(cid:28)#(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21)(cid:3) -(cid:20)(cid:24)(cid:4) (cid:23)(cid:20)(cid:4)(cid:4) (cid:23)(cid:20)(cid:30)(cid:4) .$(cid:12)(cid:10)!(cid:14)#(cid:2)(cid:31)(cid:28)#(cid:2)>(cid:7)#&(cid:11) .(cid:3) (cid:3)(cid:20)(cid:3)(cid:4) (cid:3)(cid:20)-(cid:4) (cid:3)(cid:20)(cid:23)(cid:4) ,(cid:10)(cid:15)&(cid:28)(cid:8)&(cid:2)>(cid:7)#&(cid:11) ) (cid:4)(cid:20)-(cid:29) (cid:4)(cid:20)(cid:23)(cid:4) (cid:4)(cid:20)(cid:23)< ,(cid:10)(cid:15)&(cid:28)(cid:8)&(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) 9 (cid:4)(cid:20)(cid:29)(cid:4) (cid:4)(cid:20)?(cid:4) (cid:4)(cid:20)(cid:5)(cid:29) ,(cid:10)(cid:15)&(cid:28)(cid:8)&(cid:27)&(cid:10)(cid:27).$(cid:12)(cid:10)!(cid:14)#(cid:2)(cid:31)(cid:28)# U (cid:4)(cid:20)(cid:3)(cid:4) = = (cid:30)(cid:26)(cid:12)(cid:5)(cid:11)(cid:31) (cid:30)(cid:20) (cid:31)(cid:7)(cid:15)(cid:2)(cid:30)(cid:2) (cid:7)!"(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)#(cid:14)$(cid:2)%(cid:14)(cid:28)&"(cid:9)(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)((cid:2))"&(cid:2)’"!&(cid:2))(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)*(cid:7)&(cid:11)(cid:7)(cid:15)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)&(cid:8)(cid:11)(cid:14)#(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) (cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2)(cid:11)(cid:28) (cid:14)(cid:2)(cid:10)(cid:15)(cid:14)(cid:2)(cid:10)(cid:9)(cid:2)’(cid:10)(cid:9)(cid:14)(cid:2)(cid:14)$(cid:12)(cid:10)!(cid:14)#(cid:2)&(cid:7)(cid:14)(cid:2))(cid:28)(cid:9)!(cid:2)(cid:28)&(cid:2)(cid:14)(cid:15)#!(cid:20) -(cid:20) (cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)(cid:7)!(cid:2)!(cid:28)*(cid:2)!(cid:7)(cid:15)(cid:17)"(cid:16)(cid:28)&(cid:14)#(cid:20) (cid:23)(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)#(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6).(cid:2)0(cid:30)(cid:23)(cid:20)(cid:29)(cid:6)(cid:20) 1(cid:22),2 1(cid:28)!(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)&(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)$(cid:28)(cid:8)&(cid:2) (cid:28)(cid:16)"(cid:14)(cid:2)!(cid:11)(cid:10)*(cid:15)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)!(cid:20) (cid:26).32 (cid:26)(cid:14)%(cid:14)(cid:9)(cid:14)(cid:15)(cid:8)(cid:14)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)((cid:2)"!"(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)((cid:2)%(cid:10)(cid:9)(cid:2)(cid:7)(cid:15)%(cid:10)(cid:9)’(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:12)"(cid:9)(cid:12)(cid:10)!(cid:14)!(cid:2)(cid:10)(cid:15)(cid:16)(cid:18)(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17),(cid:4)(cid:23)(cid:27)(cid:30)(cid:3)(cid:3)1 DS20001203U-page 28  1998-2013 Microchip Technology Inc.

24AA256/24LC256/24FC256 (cid:30)(cid:26)(cid:12)(cid:5)(cid:31) 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)  1998-2013 Microchip Technology Inc. DS20001203U-page 29

24AA256/24LC256/24FC256 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS20001203U-page 30  1998-2013 Microchip Technology Inc.

24AA256/24LC256/24FC256 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  1998-2013 Microchip Technology Inc. DS20001203U-page 31

24AA256/24LC256/24FC256 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)(cid:15)(cid:16)(cid:6)(cid:10)(cid:8),(cid:10)(cid:6)(cid:12)$(cid:8)(cid:30)(cid:26)(cid:8)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:6)(cid:14)*(cid:6)-(cid:5)(cid:8)(cid:19).(cid:30)(cid:20)(cid:8)(cid:21)(cid:8)20(cid:22)0(cid:23)%31(cid:8)(cid:24)(cid:24)(cid:8)(cid:25)(cid:26)(cid:7)(cid:27)(cid:8)(cid:28)((cid:15),(cid:30)(cid:29) (cid:30)(cid:26)(cid:12)(cid:5)(cid:31) 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) DS20001203U-page 32  1998-2013 Microchip Technology Inc.

24AA256/24LC256/24FC256 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  1998-2013 Microchip Technology Inc. DS20001203U-page 33

24AA256/24LC256/24FC256 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS20001203U-page 34  1998-2013 Microchip Technology Inc.

24AA256/24LC256/24FC256 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  1998-2013 Microchip Technology Inc. DS20001203U-page 35

24AA256/24LC256/24FC256 APPENDIX A: REVISION HISTORY Revision L Corrections to Section 1.0, Electrical Characteristics. Revision M Added 1.8V 400 kHz option for 24FC256. Revision N Revised Sections 2.1 and 2.4. Removed 14-Lead TSSOP Package. Revision P Revised Features; Changed 1.8V voltage to 1.7V; Replaced Package Drawings; Revised markings (8-lead SOIC); Revised Product ID System. Revision Q (05/10) Revised Table 1-1, Table 1-2, Section 6.1; Updated Package Drawings. Revision R (07/2011) Added Chip Scale package. Revision S (12/2012) Revise Automotive E temp. Revision T (04/2013) Added TDFN Package. Revision U (11/2013) Updated Idds. DS20001203U-page 36  1998-2013 Microchip Technology Inc.

24AA256/24LC256/24FC256 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at Users of Microchip products can receive assistance www.microchip.com. This web site is used as a means through several channels: to make files and information easily available to • Distributor or Representative customers. Accessible by using your favorite Internet • Local Sales Office browser, the web site contains the following informa- • Field Application Engineer (FAE) tion: • Technical Support • Product Support – Data sheets and errata, appli- cation notes and sample programs, design Customers should contact their distributor, representa- resources, user’s guides and hardware support tive or Field Application Engineer (FAE) for support. documents, latest software releases and archived Local sales offices are also available to help custom- software ers. A listing of sales offices and locations is included in the back of this document. • General Technical Support – Frequently Asked Questions (FAQ), technical support requests, Technical support is available through the web site online discussion groups, Microchip consultant at: http://microchip.com/support program member listing • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Micro- chip sales offices, distributors and factory repre- sentatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a spec- ified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Cus- tomer Change Notification” and follow the registration instructions.  1998-2013 Microchip Technology Inc. DS20001203U-page 37

24AA256/24LC256/24FC256 NOTES: DS20001203U-page 38  1998-2013 Microchip Technology Inc.

24AA256/24LC256/24FC256 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. Examples: PART NO. X /XX a) 24AA256-I/P: Industrial Temp., Device Temperature Package 1.7V, PDIP package. Range b) 24AA256T-I/SN: Tape and Reel, Industrial Temp., 1.7V, SOIC Device: 24AA256: 256 Kbit 1.7V I2C Serial package. EEPROM c) 24AA256-I/ST: Industrial Temp., 24AA256T: 256 Kbit 1.7V I2C Serial 1.7V, TSSOP package. EEPROM Tape and Reel) 24LC256: 256 Kbit 2.5V I2C Serial d) 24AA256-I/MS: Industrial Temp., EEPROM 1.7V, MSOP package. 24LC256T: 256 Kbit 2.5V I2C Serial e) 24LC256-E/P: Extended Temp., EEPROM Tape and Reel) 2.5V, PDIP package. 24FC256: 256 Kbit High Speed I2C Serial f) 24LC256-I/SN: Industrial Temp., EEPROM 2.5V, SOIC package. 24FC256T: 256 Kbit High Speed I2C Serial g) 24LC256T-I/SN: Tape and Reel, EEPROM Tape and Reel) Industrial Temp., 2.5V, SOIC package. Temperature I = -40C to +85C h) 24LC256-I/MS: Industrial Temp, Range: E = -40C to +125C 2.5V, MSOP package. i) 24FC256-I/P: Industrial Temp, Package: P = Plastic DIP (300 mil body), 8-lead 1.7V, High Speed, PDIP package. SN = Plastic SOIC (3.90 mm body), 8-lead j) 24FC256-I/SN: Industrial Temp, SM = Plastic SOIJ (5.28 mm body), 8-lead 1.7V, High Speed, SOIC package. ST = Plastic TSSOP (4.4 mm), 8-lead k) 24FC256T-I/SN: Tape and Reel, MF = Dual, Flat, No Lead (DFN)(6x5 mm Industrial Temp, 1.7V, High Speed, body), 8-lead SOIC package. MS = Plastic Micro Small Outline (MSOP), 8-lead l) 24AA256T-CS16K: Industrial Temp, MNY(2)=Dual, Flat, No Lead (TDFN) (2x3 mm 1.7V, CS package, Tape and Reel. body), 8-lead m) 24AA256T-E/SN: Tape and Reel, CS16K(1) = Chip Scale (CS), 8-lead (I-temp, Extended Temp., 1.7V, SOIC “AA”, Tape and Reel only) package. Note1: “16K” indicates 160K technology. 2: “Y” indicates a Nickel Palladium Gold (NiPdAu) finish.  1998-2013 Microchip Technology Inc. DS20001203U-page 39

24AA256/24LC256/24FC256 NOTES: DS20001203U-page 40  1998-2013 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC, and may be superseded by updates. It is your responsibility to FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, ensure that your application meets with your specifications. PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash MICROCHIP MAKES NO REPRESENTATIONS OR and UNI/O are registered trademarks of Microchip Technology WARRANTIES OF ANY KIND WHETHER EXPRESS OR Incorporated in the U.S.A. and other countries. IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, INCLUDING BUT NOT LIMITED TO ITS CONDITION, MTP, SEEVAL and The Embedded Control Solutions QUALITY, PERFORMANCE, MERCHANTABILITY OR Company are registered trademarks of Microchip Technology FITNESS FOR PURPOSE. Microchip disclaims all liability Incorporated in the U.S.A. arising from this information and its use. Use of Microchip Silicon Storage Technology is a registered trademark of devices in life support and/or safety applications is entirely at Microchip Technology Inc. in other countries. the buyer’s risk, and the buyer agrees to defend, indemnify and Analog-for-the-Digital Age, Application Maestro, BodyCom, hold harmless Microchip from any and all damages, claims, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, suits, or expenses resulting from such use. No licenses are dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, conveyed, implicitly or otherwise, under any Microchip ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial intellectual property rights. Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O, Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA and Z-Scale are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. GestIC and ULPP are registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 1998-2013, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 9781620776827 QUALITY MANAGEMENT SYSTEM Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and CERTIFIED BY DNV Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures == ISO/TS 16949 == are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.  1998-2013 Microchip Technology Inc. DS20001203U-page 41

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Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: M icrochip: 24LC256-I/STG 24FC256T-I/SN 24FC256T-I/ST 24FC256T-I/SM 24FC256T-I/MS 24AA256T-I/ST 24AA256T-I/SN 24AA256T-I/SM 24AA256T-I/MS 24AA256T-I/SMG 24LC256T-I/SMG 24LC256-E/P 24FC256-I/P 24LC256-E/MS 24LC256-E/MF 24LC256-I/P 24LC256-I/SM 24LC256-I/ST 24LC256-E/SM 24LC256-E/ST 24FC256-I/SM 24FC256-I/MS 24FC256-I/MF 24FC256-I/ST 24FC256-I/SN 24AA256-I/SM 24AA256-I/SN 24AA256-I/ST 24FC256T-I/SMG 24LC256T-E/MS 24LC256T-E/SN 24LC256T-E/ST 24LC256T-E/SM 24AA256-I/P 24FC256- I/SMG 24AA256-I/MS 24AA256-I/MF 24AA256T/SM 24LC256-I/SNG 24LC256-I/SMG 24LC256T-I/ST 24LC256T- I/SN 24LC256T-I/SM 24AA256/SM 24AA256-I/SMG 24LC256-E/SN 24LC256-I/PG 24LC256-I/MF 24LC256-I/SN 24LC256-I/MS 24FC256T-I/MF 24AA256T-I/MF 24LC256T-E/MF 24LC256T-I/MF 24AA256UID-I/SN 24AA256T- E/MS 24AA256-E/MS 24AA256T-E/ST 24AA256-E/SN 24AA256UIDT-I/SN 24AA256T-E/SN 24AA256-E/P 24AA256UID-I/P 24AA256T-E/MNY 24LC256T-I/MNY 24AA256T-I/CS16K 24AA256-E/SM 24AA256T-E/MF 24AA256-E/ST 24FC256T-I/MNY 24AA256UIDT-I/ST 24AA256UID-I/ST 24AA256T-E/SM 24AA256T-I/MNY 24LC256T-E/MNY 24AA256-E/MF