24AA1025/24LC1025/24FC1025 2 1024K I C™ Serial EEPROM Device Selection Table: This device is capable of both random and sequential reads. Reads may be sequential within address Part VCC Max. Clock Temp. boundaries 0000h to FFFFh and 10000h to 1FFFFh. Number Range Frequency Ranges Functional address lines allow up to four devices on the 24AA1025 1.7-5.5V 400kHz† I same data bus. This allows for up to 4Mbits total system EEPROM memory. This device is available in 24LC1025 2.5-5.5V 400kHz* I, E the standard 8-pin PDIP, SOIC and SOIJ packages. 24FC1025 1.8-5.5V 1MHz‡ I †100kHz for VCC < 2.5V Package Type *100 kHz for VCC < 4.5V, E-temp ‡400 kHz for VCC < 2.5V PDIP A0 1 8 VCC Features: A1 2 7 WP • Low-Power CMOS Technology: A2* 3 6 SCL - Read current 450 A, maximum VSS 4 5 SDA - Standby current 5 A, maximum • 2-Wire Serial Interface, I2C™ Compatible SOIJ/SOIC • Cascadable up to Four Devices A0 1 8 VCC • Schmitt Trigger Inputs for Noise Suppression • Output Slope Control to Eliminate Ground Bounce A1 2 7 WP • 100 kHz and 400 kHz Clock Compatibility A2* 3 6 SCL • 1 MHz Clock for FC Versions VSS 4 5 SDA • Page Write Time 3 ms, typical • Self-Timed Erase/Write Cycle *A2 must be tied to VCC. • 128-Byte Page Write Buffer • Hardware Write-Protect Block Diagram • ESD Protection >4000V • More than 1 Million Erase/Write Cycles A0A1 WP HVGenerator • Data Retention >200 Years • Factory Programming Available • Packages include 8-lead PDIP, SOIJ and SOIC I/O Memory EEPROM Control Control XDEC Array • Pb-Free and RoHS Compliant Logic Logic • Temperature Ranges: Page Latches - Industrial (I): -40C to +85C I/O - Automotive (E): -40C to +125C SCL YDEC SDA Description: The Microchip Technology Inc. 24AA1025/24LC1025/ VCC 24FC1025 (24XX1025*) is a 128K x 8 (1024K bit) VSS Sense AMP R/W Control Serial Electrically Erasable PROM, capable of operation across a broad voltage range (1.7V to 5.5V). It has been developed for advanced, low-power *24XX1025 is used in this document as a generic part number applications such as personal communications or data for the 24AA1025/24LC1025/24FC1025 devices. acquisition. This device has both byte write and page write capability of up to 128 bytes of data.  2005-2013 Microchip Technology Inc. DS20001941L-page 1

24AA1025/24LC1025/24FC1025 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings(†) VCC.............................................................................................................................................................................6.5V All inputs and outputs w.r.t. VSS..........................................................................................................-0.6V to VCC+1.0V Storage temperature...............................................................................................................................-65°C to +150°C Ambient temperature with power applied................................................................................................-40°C to +125°C ESD protection on all pins 4kV † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. TABLE 1-1: DC CHARACTERISTICS Industrial (I): VCC = +1.7V to 5.5V TA = -40°C to +85°C DC CHARACTERISTICS Automotive (E): VCC = +2.5V to 5.5V TA = -40°C to +125°C Param. Sym. Characteristic Min. Max. Units Conditions No. — A1, A2, SCL, SDA and — — — WP pins: D1 VIH High-level input voltage 0.7 VCC — V D2 VIL Low-level input voltage — 0.3 VCC V VCC 2.5V 0.2 VCC V VCC < 2.5V D3 VHYS Hysteresis of Schmitt 0.05 VCC — V VCC  2.5V (Note) Trigger inputs (SDA, SCL pins) D4 VOL Low-level output voltage — 0.40 V IOL = 3.0mA @ VCC = 4.5V IOL = 2.1mA @ VCC = 2.5V D5 ILI Input leakage current — ±1 A VIN = VSS or VCC VIN = VSS or VCC D6 ILO Output leakage current — ±1 A VOUT = VSS or VCC D7 CIN, Pin capacitance — 10 pF VCC = 5.0V (Note) COUT (all inputs/outputs) TA = 25°C, FCLK = 1MHz D8 ICC Read Operating current — 450 A VCC = 5.5V, SCL = 400kHz ICC Write — 5 mA VCC = 5.5V D9 ICCS Standby current — 5 A SCL, SDA, VCC = 5.5V A1, A2, WP = VSS Note: This parameter is periodically sampled and not 100% tested. DS20001941L-page 2  2005-2013 Microchip Technology Inc.

24AA1025/24LC1025/24FC1025 TABLE 1-2: AC CHARACTERISTICS Industrial (I): VCC = +1.7V to 5.5V TA = -40°C to +85°C AC CHARACTERISTICS Automotive (E):Vcc = +2.5V to 5.5V TA = -40°C to +125°C Param. Sym. Characteristic Min. Max. Units Conditions No. 1 FCLK Clock frequency — 100 kHz 1.7V  VCC  2.5V — 100 2.5V  VCC  4.5V, E-temp — 400 2.5V  VCC  5.5V — 400 1.8V  VCC  2.5V (24FC1025 only) — 1000 2.5V  VCC  5.5V (24FC1025 only) 2 THIGH Clock high time 4000 — ns 1.7V  VCC  2.5V 4000 — 2.5V  VCC  4.5V, E-temp 600 — 2.5V  VCC  5.5V 600 — 1.8V  VCC  2.5V (24FC1025 only) 500 — 2.5V  VCC  5.5V (24FC1025 only) 3 TLOW Clock low time 4700 — ns 1.7V  VCC  2.5V 4700 — 2.5V  VCC  4.5V, E-temp 1300 — 2.5V  VCC  5.5V 1300 — 1.8V  VCC  2.5V (24FC1025 only) 500 — 2.5V  VCC  5.5V (24FC1025 only) 4 TR SDA and SCL rise time — 1000 ns 1.7V  VCC  2.5V (Note1) — 1000 2.5V  VCC  4.5V, E-temp — 300 2.5V  VCC  5.5V — 300 1.8V  VCC  2.5V (24FC1025 only) — 300 2.5V  VCC  5.5V (24FC1025 only) 5 TF SDA and SCL fall time — 300 ns All except 24FC1025 (Note1) — 100 1.8V  VCC  5.5V (24FC1025 only) 6 THD:STA Start condition hold time 4000 — ns 1.7V  VCC  2.5V 4000 — 2.5V  VCC  4.5V, E-temp 600 — 2.5V  VCC  5.5V 600 — 1.8V  VCC  2.5V (24FC1025 only) 250 — 2.5V  VCC  5.5V (24FC1025 only) 7 TSU:STA Start condition setup time 4700 — ns 1.7V  VCC  2.5V 4700 — 2.5V  VCC  4.5V, E-temp 600 — 2.5V  VCC  5.5V 600 — 1.8V  VCC  2.5V (24FC1025 only) 250 — 2.5V  VCC  5.5V (24FC1025 only) 8 THD:DAT Data input hold time 0 — ns (Note2) 9 TSU:DAT Data input setup time 250 — ns 1.7V  VCC  2.5V 250 — 2.5V  VCC  4.5V, E-temp 100 — 2.5V  VCC  5.5V 100 — 1.8V  VCC  2.5V (24FC1025 only) 100 — 2.5V  VCC  5.5V (24FC1025 only) 10 TSU:STO Stop condition setup time 4000 — ns 1.7V  VCC  2.5V 4000 — 2.5V  VCC  4.5V, E-temp 600 — 2.5V  VCC  5.5V 600 — 1.8V  VCC  2.5V (24FC1025 only) 250 — 2.5V  VCC  5.5V (24FC1025 only) Note 1: Not 100% tested. CB = total capacitance of one bus line in pF. 2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. 3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs which provide improved noise spike suppression. This eliminates the need for a TI specification for standard operation. 4: This parameter is not tested but established by characterization. For endurance estimates in a specific application, please consult the Total Endurance™ Model which can be obtained from Microchip’s web site at www.microchip.com.  2005-2013 Microchip Technology Inc. DS20001941L-page 3

24AA1025/24LC1025/24FC1025 Industrial (I): VCC = +1.7V to 5.5V TA = -40°C to +85°C AC CHARACTERISTICS (Continued) Automotive (E):Vcc = +2.5V to 5.5V TA = -40°C to +125°C Param. Sym. Characteristic Min. Max. Units Conditions No. 11 TSU:WP WP setup time 4000 — ns 1.7V  VCC  2.5V 4000 — 2.5V  VCC  4.5V, E-temp 600 — 2.5V  VCC  5.5V 600 — 1.8V  VCC  2.5V (24FC1025 only) 600 — 2.5V  VCC  5.5V (24FC1025 only) 12 THD:WP WP hold time 4700 — ns 1.7V  VCC  2.5V 4700 — 2.5V  VCC  4.5V, E-temp 1300 — 2.5V  VCC  5.5V 1300 — 1.8V  VCC  2.5V (24FC1025 only) 1300 — 2.5V  VCC  5.5V (24FC1025 only) 13 TAA Output valid from clock — 3500 ns 1.7V  VCC  2.5V (Note2) — 3500 2.5V  VCC  4.5V, E-temp — 900 2.5V  VCC  5.5V — 900 1.8V  VCC  2.5V (24FC1025 only) — 400 2.5V  VCC  5.5V (24FC1025 only) 14 TBUF Bus free time: Time the bus 4700 — ns 1.7V  VCC  2.5V must be free before a new 4700 — 2.5V  VCC  4.5V, E-temp transmission can start 1300 — 2.5V  VCC  5.5V 1300 — 1.8V  VCC  2.5V (24FC1025 only) 500 — 2.5V  VCC  5.5V (24FC1025 only) 15 TSP Input filter spike suppression — 50 ns All except 24FC1025 (Note1 and Note3) (SDA and SCL pins) 16 TWC Write cycle time (byte or page) — 5 ms — 17 Endurance 1,000,000 — cycles Page mode, 25°C, VCC = 5.5V (Note4) Note 1: Not 100% tested. CB = total capacitance of one bus line in pF. 2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. 3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs which provide improved noise spike suppression. This eliminates the need for a TI specification for standard operation. 4: This parameter is not tested but established by characterization. For endurance estimates in a specific application, please consult the Total Endurance™ Model which can be obtained from Microchip’s web site at www.microchip.com. FIGURE 1-1: BUS TIMING DATA 5 4 2 D3 SCL 7 3 8 9 10 SDA 6 IN 15 13 14 SDA OUT (protected) WP 11 12 (unprotected) DS20001941L-page 4  2005-2013 Microchip Technology Inc.

24AA1025/24LC1025/24FC1025 2.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table2-1. TABLE 2-1: PIN FUNCTION TABLE Name PDIP SOIJ SOIC Function A0 1 1 1 User Configurable Chip Select A1 2 2 2 User Configurable Chip Select A2 3 3 3 Non-Configurable Chip Select. This pin must be hard-wired to logical 1 state (VCC). Operation will be undefined with this pin left floating or held to logical 0 (VSS). VSS 4 4 4 Ground SDA 5 5 5 Serial Data SCL 6 6 6 Serial Clock WP 7 7 7 Write-Protect Input VCC 8 8 8 +1.7 to 5.5V (24AA1025) +2.5 to 5.5V (24LC1025) +1.8 to 5.5V (24FC1025) 2.1 A0, A1 Chip Address Inputs 2.3 Serial Data (SDA) The A0 and A1 inputs are used by the 24XX1025 for This is a bidirectional pin used to transfer addresses multiple device operations. The levels on these inputs and data into and data out of the device. It is an open- are compared with the corresponding bits in the slave drain terminal, therefore, the SDA bus requires a pull- address. The chip is selected if the comparison is true. up resistor to VCC (typical 10k for 100kHz, 2kfor 400kHz and 1MHz). Up to four devices may be connected to the same bus by using different Chip Select bit combinations. In most For normal data transfer SDA is allowed to change only applications, the chip address inputs A0 and A1 are during SCL low. Changes during SCL high are hard-wired to logic ‘0’ or logic ‘1’. For applications in reserved for indicating the Start and Stop conditions. which these pins are controlled by a microcontroller or other programmable device, the chip address pins 2.4 Serial Clock (SCL) must be driven to logic ‘0’ or logic ‘1’ before normal device operation can proceed. This input is used to synchronize the data transfer from and to the device. 2.2 A2 Chip Address Input 2.5 Write-Protect (WP) The A2 input is non-configurable Chip Select. This pin must be tied to VCC in order for this device to operate. This pin must be connected to either VSS or VCC. If tied If left floating or tied to VSS, device operation will be to VSS, write operations are enabled. If tied to VCC, undefined. write operations are inhibited, but read operations are not affected.  2005-2013 Microchip Technology Inc. DS20001941L-page 5

24AA1025/24LC1025/24FC1025 3.0 FUNCTIONAL DESCRIPTION The 24XX1025 supports a bidirectional 2-wire bus and data transmission protocol. A device that sends data onto the bus is defined as a transmitter and a device receiving data as a receiver. The bus must be controlled by a master device which generates the Serial Clock (SCL), controls the bus access, and generates the Start and Stop conditions while the 24XX1025 works as a slave. Both master and slave can operate as a transmitter or receiver, but the master device determines which mode is activated. DS20001941L-page 6  2005-2013 Microchip Technology Inc.

24AA1025/24LC1025/24FC1025 4.0 BUS CHARACTERISTICS The data on the line must be changed during the low period of the clock signal. There is one bit of data per The following bus protocol has been defined: clock pulse. • Data transfer may be initiated only when the bus Each data transfer is initiated with a Start condition and is not busy. terminated with a Stop condition. The number of the • During data transfer, the data line must remain data bytes transferred between the Start and Stop stable whenever the clock line is high. Changes in conditions is determined by the master device. the data line while the clock line is high will be interpreted as a Start or Stop condition. 4.5 Acknowledge Accordingly, the following bus conditions have been Each receiving device, when addressed, is obliged to defined (Figure4-1). generate an Acknowledge signal after the reception of each byte. The master device must generate an extra 4.1 Bus Not Busy (A) clock pulse which is associated with this Acknowledge bit. Both data and clock lines remain high. Note: The 24XX1025 does not generate any 4.2 Start Data Transfer (B) Acknowledge bits if an internal program- ming cycle is in progress, however, the A high-to-low transition of the SDA line while the clock control byte that is being polled must (SCL) is high determines a Start condition. All match the control byte used to initiate the commands must be preceded by a Start condition. write cycle. A device that acknowledges must pull-down the SDA 4.3 Stop Data Transfer (C) line during the Acknowledge clock pulse in such a way A low-to-high transition of the SDA line while the clock that the SDA line is stable low during the high period of (SCL) is high determines a Stop condition. All the acknowledge related clock pulse. Of course, setup operations must end with a Stop condition. and hold times must be taken into account. During reads, a master must signal an end of data to the slave 4.4 Data Valid (D) by NOT generating an Acknowledge bit on the last byte that has been clocked out of the slave. In this case, the The state of the data line represents valid data when, slave (24XX1025) will leave the data line high to enable after a Start condition, the data line is stable for the the master to generate the Stop condition. duration of the high period of the clock signal. FIGURE 4-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS (A) (B) (D) (D) (C) (A) SCL SDA Start Address or Data Stop Condition Acknowledge Allowed Condition Valid To Change FIGURE 4-2: ACKNOWLEDGE TIMING Acknowledge Bit SCL 1 2 3 4 5 6 7 8 9 1 2 3 SDA Data from transmitter Data from transmitter The transmitter must release the SDA line at this The receiver must release the SDA line at this point allowing the receiver to pull the SDA line low point so the transmitter can continue sending to acknowledge the previous eight bits of data. data.  2005-2013 Microchip Technology Inc. DS20001941L-page 7

24AA1025/24LC1025/24FC1025 5.0 DEVICE ADDRESSING FIGURE 5-1: CONTROL BYTE FORMAT A control byte is the first byte received following the Start condition from the master device (Figure5-1). Read/Write Bit The control byte consists of a 4-bit control code; for the Block Chip 24XX1025, this is set as ‘1010’ binary for read and Select Select write operations. The next bit of the control byte is the Control Code Bits Bits block select bit (B0). This bit acts as the A16 address bit for accessing the entire array. The next two bits of S 1 0 1 0 B0 A1 A0 R/W ACK the control byte are the Chip Select bits (A1, A0). The Chip Select bits allow the use of up to four 24XX1025 Slave Address devices on the same bus and are used to select which device is accessed. The Chip Select bits in the control Start Bit Acknowledge Bit byte must correspond to the logic levels on the corresponding A1 and A0 pins for the device to respond. These bits are in effect the two Most 5.1 Contiguous Addressing Across Significant bits (MSb) of the word address. Multiple Devices The last bit of the control byte defines the operation to be performed. When set to a one, a read operation is The Chip Select bits A1 and A0 can be used to expand selected, and when set to a zero, a write operation is the contiguous address space for up to 4Mbit by add- selected. The next two bytes received define the ing up to four 24XX1025’s on the same bus. In this address of the first data byte (Figure5-2). The upper case, software can use A0 of the control byte as address bits are transferred first, followed by the Least address bit A17 and A1 as address bit A18. It is not Significant bits (LSb). possible to sequentially read across device boundar- ies. Following the Start condition, the 24XX1025 monitors the SDA bus checking the device type identifier being Each device has internal addressing boundary transmitted. Upon receiving a ‘1010’ code and limitations. This divides each part into two segments of appropriate device select bits, the slave device outputs 512K bits. The block select bit ‘B0’ controls access to an Acknowledge signal on the SDA line. Depending on each “half”. the state of the R/W bit, the 24XX1025 will select a read Sequential read operations are limited to 512K blocks. or write operation. To read through four devices on the same bus, eight This device has an internal addressing boundary random Read commands must be given. limitation that is divided into two segments of 512K bits. Block select bit ‘B0’ to control access to each segment. FIGURE 5-2: ADDRESS SEQUENCE BIT ASSIGNMENTS Control Byte Address High Byte Address Low Byte B A A A A A A A A A A A A 1 0 1 0 0 1 0 R/W 15 14 13 12 11 10 9 8 7 • • • • • • 0 Control Block Chip Code Select Select X = “don’t care” bit Bit Bits DS20001941L-page 8  2005-2013 Microchip Technology Inc.

24AA1025/24LC1025/24FC1025 6.0 WRITE OPERATIONS 6.2 Page Write The write control byte, word address and the first data 6.1 Byte Write byte are transmitted to the 24XX1025 in the same way as in a byte write. But instead of generating a Stop Following the Start condition from the master, the condition, the master transmits up to 127 additional control code (four bits), the block select (one bit), the bytes, which are temporarily stored in the on-chip page Chip Select (two bits), and the R/W bit (which is a logic buffer and will be written into memory after the master low) are clocked onto the bus by the master transmitter. has transmitted a Stop condition. After receipt of each This indicates to the addressed slave receiver that the word, the seven lower Address Pointer bits are address high byte will follow after it has generated an internally incremented by one. If the master should Acknowledge bit during the ninth clock cycle. transmit more than 128 bytes prior to generating the Therefore, the next byte transmitted by the master is Stop condition, the address counter will roll over and the high-order byte of the word address and will be the previously received data will be overwritten. As with written into the Address Pointer of the 24XX1025. The the byte write operation, once the Stop condition is next byte is the Least Significant Address Byte. After received, an internal write cycle will begin (Figure6-2). receiving another Acknowledge signal from the If an attempt is made to write to the array with the WP 24XX1025, the master device will transmit the data pin held high, the device will acknowledge the word to be written into the addressed memory location. command, but no write cycle will occur, no data will be The 24XX1025 acknowledges again and the master written and the device will immediately accept a new generates a Stop condition. This initiates the internal command. write cycle and during this time, the 24XX1025 will not generate Acknowledge signals as long as the control 6.3 Write Protection byte being polled matches the control byte that was used to initiate the write (Figure6-1). If an attempt is The WP pin allows the user to write-protect the entire made to write to the array with the WP pin held high, the array (00000-1FFFF) when the pin is tied to VCC. If tied device will acknowledge the command, but no write to VSS the write protection is disabled. The WP pin is cycle will occur, no data will be written and the device sampled at the Stop bit for every Write command will immediately accept a new command. After a byte (Figure1-1). Toggling the WP pin after the Stop bit will Write command, the internal address counter will point have no effect on the execution of the write cycle. to the address location following the one that was just written. Note: Page write operations are limited to writ- ing bytes within a single physical page, regardless of the number of bytes actually Note: When doing a write of less than 128 bytes being written. Physical page boundaries the data in the rest of the page is start at addresses that are integer refreshed along with the data bytes being multiples of the page buffer size (or ‘page written. This will force the entire page to size’) and end at addresses that are endure a write cycle, for this reason integer multiples of [page size – 1]. If a endurance is specified per page. Page Write command attempts to write across a physical page boundary, the result is that the data wraps around to the beginning of the current page (overwriting data previously stored there), instead of being written to the next page as might be expected. It is therefore necessary for the application software to prevent page write operations that would attempt to cross a page boundary.  2005-2013 Microchip Technology Inc. DS20001941L-page 9

24AA1025/24LC1025/24FC1025 FIGURE 6-1: BYTE WRITE S BUS ACTIVITY T S Control Address Address MASTER A T R Byte High Byte Low Byte Data O T P SDA LINE S1 0 1 0B0A1A0 0 P A A A A BUS ACTIVITY C C C C K K K K X = “don’t care” bit FIGURE 6-2: PAGE WRITE S T S BUS ACTIVITY A Control Address Address T MASTER R Byte High Byte Low Byte Data Byte 0 Data Byte 127 O T P SDA LINE S10 1 0B0A1A00 P A A A A A BUS ACTIVITY C C C C C K K K K K X = “don’t care” bit DS20001941L-page 10  2005-2013 Microchip Technology Inc.

24AA1025/24LC1025/24FC1025 7.0 ACKNOWLEDGE POLLING FIGURE 7-1: ACKNOWLEDGE POLLING FLOW Since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete. (This feature can be used to maximize bus throughput.) Once the Stop condition for a Write Send command has been issued from the master, the device Write Command initiates the internally timed write cycle. ACK polling can be initiated immediately. This involves the master sending a Start condition, followed by the control byte for a Write command (R/W = 0). If the device is still Send Stop busy with the write cycle, then no ACK will be returned. Condition to If no ACK is returned, then the Start bit and control byte Initiate Write Cycle must be resent. If the cycle is complete, then the device will return the ACK and the master can then proceed with the next Read or Write command. See Figure7-1 Send Start for flow diagram. Note: Care must be taken when polling the 24XX1025. The control byte that was Send Control Byte used to initiate the write needs to match with R/W = 0 the control byte used for polling. Did Device No Acknowledge (ACK = 0)? Yes Next Operation  2005-2013 Microchip Technology Inc. DS20001941L-page 11

24AA1025/24LC1025/24FC1025 8.0 READ OPERATION 8.2 Random Read Read operations are initiated in the same way as write Random read operations allow the master to access operations with the exception that the R/W bit of the any memory location in a random manner. To perform control byte is set to one. There are three basic types this type of read operation, first the word address must of read operations: current address read, random read be set. This is done by sending the word address to the and sequential read. 24XX1025 as part of a write operation (R/W bit set to 0). After the word address is sent, the master 8.1 Current Address Read generates a Start condition following the acknowledge. This terminates the write operation, but not before the The 24XX1025 contains an address counter that internal Address Pointer is set. Then, the master issues maintains the address of the last word accessed, the control byte again, but with the R/W bit set to a one. internally incremented by one. Therefore, if the The 24XX1025 will then issue an acknowledge and previous read access was to address n (n is any legal transmit the 8-bit data word. The master will not address), the next current address read operation acknowledge the transfer, but does generate a Stop would access data from address n + 1. condition which causes the 24XX1025 to discontinue Upon receipt of the control byte with R/W bit set to one, transmission (Figure8-2). After a random Read the 24XX1025 issues an acknowledge and transmits command, the internal address counter will point to the the 8-bit data word. The master will not acknowledge address location following the one that was just read. the transfer, but does generate a Stop condition and the 24XX1025 discontinues transmission (Figure8-1). 8.3 Sequential Read Sequential reads are initiated in the same way as a FIGURE 8-1: CURRENT ADDRESS random read except that after the 24XX1025 transmits READ the first data byte, the master issues an acknowledge as opposed to the Stop condition used in a random S T S read. This acknowledge directs the 24XX1025 to BUS ACTIVITY A Control Data T MASTER R Byte Byte O transmit the next sequentially addressed 8-bit word T P (Figure8-3). Following the final byte transmitted to the SDA LINE S 1 0 1 0 B AA 1 P master, the master will NOT generate an acknowledge, 0 1 0 but will generate a Stop condition. To provide A N BUS ACTIVITY C O sequential reads, the 24XX1025 contains an internal K A Address Pointer which is incremented by one at the C completion of each operation. This Address Pointer K allows half the memory contents to be serially read during one operation. Sequential read address boundaries are 00000h to 0FFFFh and 10000h to 1FFFFh. The internal Address Pointer will automatically roll over from address 0FFFFh to address 00000h if the master acknowledges the byte received from the array address, 0FFFFh. The internal address counter will automatically roll over from address 1FFFFh to address 10000h if the master acknowledges the byte received from the array address, 1FFFFh. DS20001941L-page 12  2005-2013 Microchip Technology Inc.

24AA1025/24LC1025/24FC1025 FIGURE 8-2: RANDOM READ S S BUS ACTIVITY T T S Control Address Address Control Data MASTER A A T R Byte High Byte Low Byte R Byte Byte O T T P SDA LINE S 1 0 1 0 B A A 0 S 1 0 1 0 B A A1 P 0 1 0 0 1 0 A A A A N BUS ACTIVITY C C C C O K K K K A C K FIGURE 8-3: SEQUENTIAL READ Control S BUS ACTIVITY T MASTER Byte Data n Data n + 1 Data n + 2 Data n + X O P SDA LINE P A A A A N C C C C O BUS ACTIVITY K K K K A C K  2005-2013 Microchip Technology Inc. DS20001941L-page 13

24AA1025/24LC1025/24FC1025 9.0 PACKAGING INFORMATION 9.1 Package Marking Information 8-Lead PDIP (300 mil) Example: XXXXXXXX 24LC1025 TXXXXNNN I/P e 3 13F YYWW 0928 8-Lead SOIC (3.90 mm) Example: XXXXXXXT 24L1025I XXXXYYWW SN e3 0928 NNN 13F 8-Lead SOIJ (5.28 mm) Example: XXXXXXXX 24LC1025 TXXXXXXX I/SMe3 YYWWNNN 0928 13F Legend: XX...X Part number or part number code T Temperature (I, E) Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code (2 characters for small packages) e3 Pb-free JEDEC designator for Matte Tin (Sn) Note: For very small packages with no room for the Pb-free JEDEC designator e 3 , the marking will only appear on the outer carton or reel label. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. * Standard marking consists of Microchip part number, year code, week code, traceability code (facility code, mask rev#, and assembly code). For marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. DS20001941L-page 14  2005-2013 Microchip Technology Inc.

24AA1025/24LC1025/24FC1025 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)(cid:15)(cid:16)(cid:6)(cid:10)(cid:8)(cid:17)(cid:18)(cid:3)(cid:4)(cid:13)(cid:18)(cid:5)(cid:8)(cid:19)(cid:9)(cid:20)(cid:8)(cid:21)(cid:8)(cid:22)(cid:23)(cid:23)(cid:8)(cid:24)(cid:13)(cid:10)(cid:8)(cid:25)(cid:26)(cid:7)(cid:27)(cid:8)(cid:28)(cid:9)(cid:15)(cid:17)(cid:9)(cid:29) (cid:30)(cid:26)(cid:12)(cid:5)(cid:31) 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) N NOTE1 E1 1 2 3 D E A A2 L A1 c e eB b1 b 6(cid:15)(cid:7)&! (cid:19)7,8.(cid:22) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:2)9(cid:7)’(cid:7)&! (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7"’)(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)(cid:31)(cid:7)(cid:15)! 7 < (cid:31)(cid:7)&(cid:8)(cid:11) (cid:14) (cid:20)(cid:30)(cid:4)(cid:4)(cid:2)1(cid:22), (cid:13)(cid:10)(cid:12)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)&(cid:7)(cid:15)(cid:17)(cid:2)(cid:31)(cid:16)(cid:28)(cid:15)(cid:14) (cid:25) = = (cid:20)(cid:3)(cid:30)(cid:4) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:25)(cid:3) (cid:20)(cid:30)(cid:30)(cid:29) (cid:20)(cid:30)-(cid:4) (cid:20)(cid:30)(cid:24)(cid:29) 1(cid:28)!(cid:14)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)&(cid:7)(cid:15)(cid:17)(cid:2)(cid:31)(cid:16)(cid:28)(cid:15)(cid:14) (cid:25)(cid:30) (cid:20)(cid:4)(cid:30)(cid:29) = = (cid:22)(cid:11)(cid:10)"(cid:16)#(cid:14)(cid:9)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:11)(cid:10)"(cid:16)#(cid:14)(cid:9)(cid:2)>(cid:7)#&(cid:11) . (cid:20)(cid:3)(cid:24)(cid:4) (cid:20)-(cid:30)(cid:4) (cid:20)-(cid:3)(cid:29) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)>(cid:7)#&(cid:11) .(cid:30) (cid:20)(cid:3)(cid:23)(cid:4) (cid:20)(cid:3)(cid:29)(cid:4) (cid:20)(cid:3)<(cid:4) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21) (cid:20)-(cid:23)< (cid:20)-?(cid:29) (cid:20)(cid:23)(cid:4)(cid:4) (cid:13)(cid:7)(cid:12)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)&(cid:7)(cid:15)(cid:17)(cid:2)(cid:31)(cid:16)(cid:28)(cid:15)(cid:14) 9 (cid:20)(cid:30)(cid:30)(cid:29) (cid:20)(cid:30)-(cid:4) (cid:20)(cid:30)(cid:29)(cid:4) 9(cid:14)(cid:28)#(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:8) (cid:20)(cid:4)(cid:4)< (cid:20)(cid:4)(cid:30)(cid:4) (cid:20)(cid:4)(cid:30)(cid:29) 6(cid:12)(cid:12)(cid:14)(cid:9)(cid:2)9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) )(cid:30) (cid:20)(cid:4)(cid:23)(cid:4) (cid:20)(cid:4)?(cid:4) (cid:20)(cid:4)(cid:5)(cid:4) 9(cid:10)*(cid:14)(cid:9)(cid:2)9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) ) (cid:20)(cid:4)(cid:30)(cid:23) (cid:20)(cid:4)(cid:30)< (cid:20)(cid:4)(cid:3)(cid:3) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)(cid:26)(cid:10)*(cid:2)(cid:22)(cid:12)(cid:28)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:2)+ (cid:14)1 = = (cid:20)(cid:23)-(cid:4) (cid:30)(cid:26)(cid:12)(cid:5)(cid:11)(cid:31) (cid:30)(cid:20) (cid:31)(cid:7)(cid:15)(cid:2)(cid:30)(cid:2) (cid:7)!"(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)#(cid:14)$(cid:2)%(cid:14)(cid:28)&"(cid:9)(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)((cid:2))"&(cid:2)’"!&(cid:2))(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)*(cid:7)&(cid:11)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)&(cid:8)(cid:11)(cid:14)#(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) +(cid:2)(cid:22)(cid:7)(cid:17)(cid:15)(cid:7)%(cid:7)(cid:8)(cid:28)(cid:15)&(cid:2),(cid:11)(cid:28)(cid:9)(cid:28)(cid:8)&(cid:14)(cid:9)(cid:7)!&(cid:7)(cid:8)(cid:20) -(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)!(cid:2)(cid:21)(cid:2)(cid:28)(cid:15)#(cid:2).(cid:30)(cid:2)#(cid:10)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)"#(cid:14)(cid:2)’(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:20)(cid:2)(cid:6)(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:2)!(cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:14)$(cid:8)(cid:14)(cid:14)#(cid:2)(cid:20)(cid:4)(cid:30)(cid:4)/(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)!(cid:7)#(cid:14)(cid:20) (cid:23)(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)#(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6).(cid:2)0(cid:30)(cid:23)(cid:20)(cid:29)(cid:6)(cid:20) 1(cid:22),2(cid:2)1(cid:28)!(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)&(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)$(cid:28)(cid:8)&(cid:2) (cid:28)(cid:16)"(cid:14)(cid:2)!(cid:11)(cid:10)*(cid:15)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)!(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17),(cid:4)(cid:23)(cid:27)(cid:4)(cid:30)<1  2005-2013 Microchip Technology Inc. DS20001941L-page 15

24AA1025/24LC1025/24FC1025 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS20001941L-page 16  2005-2013 Microchip Technology Inc.

24AA1025/24LC1025/24FC1025 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2005-2013 Microchip Technology Inc. DS20001941L-page 17

24AA1025/24LC1025/24FC1025 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8) (cid:24)(cid:6)(cid:10)(cid:10)(cid:8)!(cid:16)(cid:12)(cid:10)(cid:13)(cid:18)(cid:5)(cid:8)(cid:19) (cid:30)(cid:20)(cid:8)(cid:21)(cid:8)(cid:30)(cid:6)""(cid:26)#$(cid:8)(cid:22)%&(cid:23)(cid:8)(cid:24)(cid:24)(cid:8)(cid:25)(cid:26)(cid:7)(cid:27)(cid:8)(cid:28) !(cid:17)’(cid:29) (cid:30)(cid:26)(cid:12)(cid:5)(cid:31) 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) DS20001941L-page 18  2005-2013 Microchip Technology Inc.

24AA1025/24LC1025/24FC1025 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2005-2013 Microchip Technology Inc. DS20001941L-page 19

24AA1025/24LC1025/24FC1025 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS20001941L-page 20  2005-2013 Microchip Technology Inc.

24AA1025/24LC1025/24FC1025 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2005-2013 Microchip Technology Inc. DS20001941L-page 21

24AA1025/24LC1025/24FC1025 APPENDIX A: REVISION HISTORY Revision A (02/2005) Original release. Revision B (09/2005) Section 1.0 Electrical Characteristics: revised Ambient Temperature; Revised Table 1-1; Revised Section 2.1 and Section 2.5. Revision C (04/2006) Revised Features, Maximum Read Current and Table 1-1, D9; Revised Table 2-1, VCC; Revised Section 6.3. Revision D (01/2007) Revised Device Selection Table; Features Section; Changed 1.8V to 1.7V; Revised Tables 1-1, 1-2, 2-1; Revised Product ID System; Replaced Package Drawings. Revision E (03/2007) Replaced Package Drawings (Rev. AM). Revision F (10/2008) Corrections on the Device Selection Table; Corrections on the Description; Corrections on the AC Characteris- tics table; Corrections on the Pin Function Table; Corrections on the Product ID System; Updated Package Drawings. Revision G (01/2010) Added 8-Lead SOIC Package. Revision H (01/2011) Revised PDIP Package Type Diagram; Revised Section 1.0 Electrical Characteristics; Revised SOIC Package Marking Information (3.90mm). Revision J (07/2011) Revised Table 1-2: AC Characteristics. Revision K (04/2012) Revised document title (removed CMOS); Revised Section 5.1. Revision L (08/2013) Features Section: Revised ESD Protection to 4000V. DS20001941L-page 22  2005-2013 Microchip Technology Inc.

24AA1025/24LC1025/24FC1025 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at Users of Microchip products can receive assistance www.microchip.com. This web site is used as a means through several channels: to make files and information easily available to • Distributor or Representative customers. Accessible by using your favorite Internet • Local Sales Office browser, the web site contains the following informa- • Field Application Engineer (FAE) tion: • Technical Support • Product Support – Data sheets and errata, appli- cation notes and sample programs, design Customers should contact their distributor, representa- resources, user’s guides and hardware support tive or Field Application Engineer (FAE) for support. documents, latest software releases and archived Local sales offices are also available to help custom- software ers. A listing of sales offices and locations is included in the back of this document. • General Technical Support – Frequently Asked Questions (FAQ), technical support requests, Technical support is available through the web site online discussion groups, Microchip consultant at: http://microchip.com/support program member listing • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Micro- chip sales offices, distributors and factory repre- sentatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a spec- ified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Cus- tomer Change Notification” and follow the registration instructions.  2005-2013 Microchip Technology Inc. DS20001941L-page 23

24AA1025/24LC1025/24FC1025 NOTES: DS20001941L-page 24  2005-2013 Microchip Technology Inc.

24AA1025/24LC1025/24FC1025 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX Examples: Device Temperature Package a) 24AA1025T-I/SM: Tape and Reel, Industrial Range Temperature, SOIJ package. b) 24LC1025-I/P: Industrial Temperature, PDIP package. Device: 24AA1025 = 1024K Bit 1.7V I2C CMOS Serial EEPROM c) 24LC1025-E/SM: Extended Temperature, 24AA1025T = 1024K Bit 1.7V I2C CMOS Serial EEPROM SOIJ package. (Tape and Reel) 24LC1025 = 1024K Bit 2.5V I2C CMOS Serial EEPROM d) 24LC1025T-I/SM: Tape and Reel, Industrial 24LC1025T= 1024K Bit 2.5V I2C CMOS Serial EEPROM Temperature, SOIJ package. (Tape and Reel) e) 24FC1025-I/SN: Tape and Reel, Industrial 24FC1025 = 1024K Bit 1.8V I2C CMOS Serial EEPROM Temperature, SOIC package. 24FC1025T= 1024K Bit 1.8V I2C CMOS Serial EEPROM (Tape and Reel) Temperature I = -40°C to +85°C Range: E = -40°C to +125°C Package: P = Plastic DIP (300 mil Body), 8-lead SM = Plastic SOIJ (5.28 mm Body), 8-lead SN = Plastic SOIC (3.90 mm Body), 8-lead  2005-2013 Microchip Technology Inc. DS20001941L-page 25

24AA1025/24LC1025/24FC1025 NOTES: DS20001941L-page 26  2005-2013 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC, and may be superseded by updates. It is your responsibility to FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, ensure that your application meets with your specifications. PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash MICROCHIP MAKES NO REPRESENTATIONS OR and UNI/O are registered trademarks of Microchip Technology WARRANTIES OF ANY KIND WHETHER EXPRESS OR Incorporated in the U.S.A. and other countries. IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, INCLUDING BUT NOT LIMITED TO ITS CONDITION, MTP, SEEVAL and The Embedded Control Solutions QUALITY, PERFORMANCE, MERCHANTABILITY OR Company are registered trademarks of Microchip Technology FITNESS FOR PURPOSE. Microchip disclaims all liability Incorporated in the U.S.A. arising from this information and its use. Use of Microchip Silicon Storage Technology is a registered trademark of devices in life support and/or safety applications is entirely at Microchip Technology Inc. in other countries. the buyer’s risk, and the buyer agrees to defend, indemnify and Analog-for-the-Digital Age, Application Maestro, BodyCom, hold harmless Microchip from any and all damages, claims, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, suits, or expenses resulting from such use. No licenses are dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, conveyed, implicitly or otherwise, under any Microchip ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial intellectual property rights. Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O, Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA and Z-Scale are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. GestIC and ULPP are registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2005-2013, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 9781620773758 QUALITY MANAGEMENT SYSTEM Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and CERTIFIED BY DNV Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures == ISO/TS 16949 == are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.  2005-2013 Microchip Technology Inc. DS20001941L-page 27

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Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: M icrochip: 24AA1025-I/SN 24AA1025T-I/SN 24LC1025-E/SN 24LC1025-I/SN